TW320708B - - Google Patents

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Publication number
TW320708B
TW320708B TW086103615A TW86103615A TW320708B TW 320708 B TW320708 B TW 320708B TW 086103615 A TW086103615 A TW 086103615A TW 86103615 A TW86103615 A TW 86103615A TW 320708 B TW320708 B TW 320708B
Authority
TW
Taiwan
Prior art keywords
packet data
floating
point
instruction
register
Prior art date
Application number
TW086103615A
Other languages
English (en)
Chinese (zh)
Inventor
Mittal Millind
Eitan Benny
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of TW320708B publication Critical patent/TW320708B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30112—Register structure comprising data of variable length

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • General Preparation And Processing Of Foods (AREA)
  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
TW086103615A 1995-12-19 1997-03-21 TW320708B (index.php)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/575,686 US5857096A (en) 1995-12-19 1995-12-19 Microarchitecture for implementing an instruction to clear the tags of a stack reference register file

Publications (1)

Publication Number Publication Date
TW320708B true TW320708B (index.php) 1997-11-21

Family

ID=24301308

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086103615A TW320708B (index.php) 1995-12-19 1997-03-21

Country Status (4)

Country Link
US (1) US5857096A (index.php)
AU (1) AU1345197A (index.php)
TW (1) TW320708B (index.php)
WO (1) WO1997022920A1 (index.php)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211255B (zh) 1994-12-02 2012-07-04 英特尔公司 对复合操作数进行压缩操作的处理器、设备和计算系统
US6792523B1 (en) * 1995-12-19 2004-09-14 Intel Corporation Processor with instructions that operate on different data types stored in the same single logical register file
US5701508A (en) 1995-12-19 1997-12-23 Intel Corporation Executing different instructions that cause different data type operations to be performed on single logical register file
US5940859A (en) * 1995-12-19 1999-08-17 Intel Corporation Emptying packed data state during execution of packed data instructions
US6088786A (en) * 1997-06-27 2000-07-11 Sun Microsystems, Inc. Method and system for coupling a stack based processor to register based functional unit
US6405234B2 (en) * 1997-09-11 2002-06-11 International Business Machines Corporation Full time operating system
US6065114A (en) * 1998-04-21 2000-05-16 Idea Corporation Cover instruction and asynchronous backing store switch
US6247113B1 (en) * 1998-05-27 2001-06-12 Arm Limited Coprocessor opcode division by data type
US6212624B1 (en) * 1998-09-30 2001-04-03 Intel Corporation Selective canonizing on mode transitions
US7882325B2 (en) * 2007-12-21 2011-02-01 Intel Corporation Method and apparatus for a double width load using a single width load port
JP2010122787A (ja) * 2008-11-18 2010-06-03 Panasonic Corp 半導体集積回路及びレジスタアドレス制御装置

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US4418383A (en) * 1980-06-30 1983-11-29 International Business Machines Corporation Data flow component for processor and microprocessor systems
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US4707800A (en) * 1985-03-04 1987-11-17 Raytheon Company Adder/substractor for variable length numbers
JPS6297060A (ja) * 1985-10-23 1987-05-06 Mitsubishi Electric Corp デイジタルシグナルプロセツサ
US4992938A (en) * 1987-07-01 1991-02-12 International Business Machines Corporation Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers
US4989168A (en) * 1987-11-30 1991-01-29 Fujitsu Limited Multiplying unit in a computer system, capable of population counting
US5008812A (en) * 1988-03-18 1991-04-16 Digital Equipment Corporation Context switching method and apparatus for use in a vector processing system
US5241635A (en) * 1988-11-18 1993-08-31 Massachusetts Institute Of Technology Tagged token data processing system with operand matching in activation frames
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Also Published As

Publication number Publication date
AU1345197A (en) 1997-07-14
WO1997022920A1 (en) 1997-06-26
US5857096A (en) 1999-01-05

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