經濟部中央標準局貝工消費合作衽印製 319839 A7 —_____B? 五、發明説明（1 ) 發明背景 1. 技術領域 本發明概έ之係關於動恐電路，且更明確地説係關於如 何高效率地寫入至一動態電路以内之一暫存檔格。 2. 相關技術説明： 在現代之微處理器中，快速寫入至微處理器内部之暫存 器的能力非常重要。該等内邵暫存器通常是用以儲存微處 理器所執行之計算的結果。如果該等運算之結果無法快速 儲存於暫存器，則微處理器快速執行計算運作之能力將無 用武之地。 暫存器群組通常稱爲暫存檔。暫存檔是記憶體元件之陣 列’而該陣列之每一列表示一暫存器。例如，一暫存標可 由一 16*64之記憶體元件陣列所組成。此種暫存檔因此可包 含1 6個6 4位元之暫存器。如前所述，構成一暫存器之該等 個別儲存單元稱爲記憶體元件。如同幾乎所有之位記憶體 ’一記憶體元件可保存邏輯1 (亦即一高電壓位準）或邏輯〇 ( 亦即一低電壓位準）。 圖1展示一用以寫入一位元至一暫存檔格之以前技術裝置 。Ν Μ 0 S電晶體1 〇 6是用以使得寫入致能線〗〇 4可控制出現 於寫入資料線102之資料對於記憶體元件108之窝入。當窝 入致能線104是高時，出现於寫入資料線1〇2之資料窝入至 記憶體元件108。此種裝置在某些情形之下運作良好。但是 ’當電源電壓降低因而導致表示邏輯1之電壓降低時，則相 關於NMOS電晶體1 〇6之臨限電壓可使邏輯1無法可靠及快 ___- 4 - 本纸張尺度適用中國國家標準（CNS > Α4規格（2丨ΟX 297公釐） (請先聞讀背面之注意事項再填寫本頁) 裝 經濟部中央標率局員工消費合作社印製 319839 A7 ________B7 _ 五、發明説明（2 ) 速地寫入至記憶體元件丨〇 8。 圖2展示一種克服圖丨所示之電路之一些缺點的電路。但 是’藉由更正該等缺點，圖2所示之電路也造成新的問題3 相對於如同圖1所示之電路只具有單一 NMOS電晶體，圖2 所不之電路包含MMOS電晶體206及PMOS電晶體2〖0。加 入P N4 0 S電晶體2 1 0及其之伴隨反相器2〗2使得邏輯1可在 不導致跨於NMOS電晶體206之臨限電壓降低之下寫入至記 憶體元件208。 增加PMOS電晶體210及反相器2 12之好處並非未付出代 價’增加一 PMOS電晶體，相對於另一 NMOS電晶體，佔用 額外之表面面積且就整體而言使得電路效能變慢。這是因 爲PMOS電晶體通常是一對應之NMOS電晶體之二倍”弱"。 同時’增加反相器至跨越一暫存器全長之寫入致能線就整 體而言會對於寫入至暫存器增加額外之效能損失。 因此，需要一種電路且該種電路可快速及可靠地改變暫 存標格之狀態而不會使用過多之表面面積或就整體而言造 成電路之延遲或負載之大量增加=> 發明摘要 本發明之一目標是提供一種可快速寫入至一暫存檐格的裝 置。 本發明之另一目標是該種裝置只需最少量之表面面積且 很容易製造。 本發明之另一目標是提供一種裝置且該種裝置寫入邏輯1 至一暫存樓格之速度快於寫入邏輯0之速度。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shell Industry Consumer Cooperation 319839 A7 —_____ B? V. Description of the invention (1) Background of the invention 1. Technical Field The present invention is about the circuit of moving terrorism, and more specifically about how high Efficiently write to a temporary file within a dynamic circuit. 2. Relevant technical description: In modern microprocessors, the ability to quickly write to the internal register of the microprocessor is very important. These internal registers are usually used to store the results of calculations performed by the microprocessor. If the results of these operations cannot be quickly stored in the scratchpad, the microprocessor's ability to quickly perform calculation operations will be useless. The register group is usually called a temporary file. The temporary file is an array of memory elements' and each row of the array represents a temporary memory. For example, a temporary object may be composed of a 16 * 64 memory element array. This temporary file can therefore contain 16 64-bit temporary registers. As mentioned earlier, the individual storage units that make up a register are called memory elements. As with almost all bit memories, a memory element can store logic 1 (that is, a high voltage level) or logic 0 (that is, a low voltage level). Figure 1 shows a prior art device for writing one bit to a temporary file. NMOS transistor 106 is used to enable the write enable line to control the nesting of the memory element 108 with the data appearing on the write data line 102. When the nest enable line 104 is high, the data appearing in the write data line 102 nests into the memory element 108. Such devices work well under certain circumstances. But 'when the power supply voltage decreases and the voltage representing logic 1 decreases, the threshold voltage related to NMOS transistor 1.06 can make logic 1 unreliable and fast. ___- 4-This paper size is applicable to Chinese national standards (CNS > Α4 specification (2 丨 ΟX 297mm) (please read the notes on the back and then fill in this page) Printed by the Ministry of Economic Affairs Central Standardization Bureau employee consumer cooperative printed 319839 A7 ________B7 _ V. Description of invention (2 ) Write to the memory device quickly. Figure 2 shows a circuit that overcomes some of the shortcomings of the circuit shown in Figure 丨. But by correcting these shortcomings, the circuit shown in Figure 2 also causes new problems 3 Compared to the circuit shown in Fig. 1 which has only a single NMOS transistor, the circuit shown in Fig. 2 includes MMOS transistor 206 and PMOS transistor 2 〖0. Add P N4 0 S transistor 2 1 0 and its accompanying Inverter 2 2 enables logic 1 to be written to memory element 208 without causing the threshold voltage across NMOS transistor 206 to decrease. The benefits of adding PMOS transistor 210 and inverter 2 12 are not unpaid The price 'add a PMOS transistor, relative Another NMOS transistor occupies additional surface area and slows down the circuit performance as a whole. This is because the PMOS transistor is usually twice as weak as a corresponding NMOS transistor. At the same time 'inverter is added The write enable line that spans the full length of a register will add an additional performance loss to the write to the register as a whole. Therefore, a circuit is needed and this type of circuit can quickly and reliably change the scratch mark State without using excessive surface area or causing a large increase in circuit delay or load as a whole => Summary of the Invention An object of the present invention is to provide a device that can be quickly written to a temporary eaves. Another object of the present invention is that such a device requires only a minimum amount of surface area and is easy to manufacture. Another object of the present invention is to provide a device in which the speed of writing logic 1 to a temporary block in the device is faster than The speed of writing logic 0. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X 297mm) (please read the precautions on the back before filling in this page)
、1T 經濟部中央標準局負工消費合作、社印製 A7 __________B7 _ 五、發明説明（3 ) 該等及其他目標可如下達成。本案提供一具有一記憶體 元件之暫存檔格。第一切換器連接至該記憶體元件之一節 點’且第二切換器連接至該3己憶體元件之另一節點3該等 切換器可爲N Μ 0 S電晶體。第一切換器施加高電壓或低電 I至該記憶體元件，決定於要寫入之二元値。第二切換器 施加一電壓至該記憶體元件之另一節點。第二切換器所施 加之電壓是第一切換器所施加之電壓的邏輯補數，以此方 式’ 一”推挽效應"產生於該記憶體元件之相對節點，且二 元値可高效率地寫入該暫存檔格。 閲讀下列詳細之書面說明應可明瞭本發明之前述以及其 他目標，特點，及優點。 附圖簡短説明 據k爲本發明之特徵的新奇特點說明於附加之申請專利 範圍。但是當參照下列附圖來閱讀一示範實例之下列詳細 説明時應可最容易瞭解本發明本身，以及一較佳使用模式 ，其他之目標與優點，其中： 圖1展示一用以寫入至一暫存樓格之以前技術電路； 圖2描寫另一用以寫入至暫存檔格之前技術電路； 圖3展示一根據本發明用以窝入至暫存檔格之電路；且 圖4展示一根據本發明具有多重讀取埠及寫入埠之電路。 較佳實例詳細說明 圖3展示一根據本發明來寫入至暫存檔格之電路。暫存檔 格300提供一對>4“〇3電晶體，NM〇s電晶體3i〇&nm〇s 電晶體312。NMOS電晶體31〇在節點311連接至記憶體元 本紙張尺度適用中國國家標隼（CNS ) A4規格（21〇>< 297公嫠 (請先閱讀背面之注意事項再填寫本頁) 裝 經濟部中夬標準局貝工消費合作杜印装 A7 _________B7 五、發明説明（4 ) 件3 14，而NMOS電晶體3 U在節點3 13連接至記憶體元件 。同時，提供反相器308於寫入資料補數線3〇4(出現於 資料補數線3 〇 4之訊號是出現於寫入資料線3 〇 2之訊號的補 數）。如圖3所示之該等元件的配置使得資料可利用一快速 及高效率之方式寫入至記憶體元件3 1 4。 如前所述，寫入資料線3 02爲反相器3 1 6所反相。相較於 反相器308，反相器316是相當大之裝置，因爲反相器316 必須提供其之輸出至未展示於圖3之一些其他記憶體元件， Ν Μ Ο S電晶體3 1 0是用以施加寫入資料補數線3 〇 4至記憶體 元件3 1 4之節點3 1 1。NMOS電晶體3 1 0是由寫入致能線 3 0 6來控制寫入致能線3 0 6也控制Ν Μ 0 S電晶體3 1 2之切 換。NMOS電晶體3 12施加一訊號至記憶體元件3 14之節點 3 1 2，且該訊號是Ν Μ 0 S電晶體3 1 0所施加之訊號的補數。 此互補訊號是由位於寫入資料補數線3 04之反相器3 08所造 成。 Ν Μ Ο S電晶體3 1 0及Ν Μ Ο S電晶體3 1 2之淨效應是對於記 憶體元件3 1 4產生"推挽效應”。當Ν Μ 0 S電晶體3 1 0或 Ν Μ 0 S電晶體3 1 2施加高訊號至記憶體元件3 1 4之節點3 1 3 時，另一電晶體則施加低訊號至記憶體元件3 1 4之另一節點 。施加互補訊號至記憶體元件3 1 4之淨結果是以一快速且高 效率之方式來切換記憶體元件3 1 4之狀態。 暫存檔格3 00相對於圖2所示之電路的另一優點是反相器 308是置於寫入資料線而非寫入致能線。因爲暫存檔之寬度 通常遠大於他們之深度（例如一暫存檐格可包含1 6暫存器， 本紙張尺度適用中國國家標隼（CNS)A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝 經濟部t夬標準局貝工消費合作社印裝 318839 A7 ------------B7_ 五、發明説明（5 ) — 且每一暫存咨是6 4位元，則該暫存器是6 4格寬及1 6格深）， ^加一反相益至資料線對於效能之衝擊低於增加一反相器 窝入致能線所造成之效能衝擊。 暫存標格3 0 0之另一優點是寫入邏輯1之速度快於寫入邏 輯〇之速度。這很重要，因爲在許多動態邏輯電路中，電路 之啓始輸出是邏輯〇。如果特定之動態邏輯電路最終許估爲 * 0 ’則該電路之輸出將永遠無需改變。同時，通常寫入致能 線306料會在寫入資料線3 〇2之資料變爲有效之前變爲有效 °因此’當請求暫存檔格300寫入邏輯0至記憶體元件3 14 時，暫存檔格3 00通常擁有寫入致能訊號是高之全部時間來 寫入邏輯0至記憶體元件3 1 4。 另一方面，暫存檔格3 〇 〇擁有遠較少之時間來寫入邏輯1至 記憶體元件3 1 4。此種時間減少之發生是因爲寫入資料線 3 0 2之訊號可在寫入致能線3 〇 6之訊號受到致能之時段末端 自邏輯0變爲邏輯1。在此種情形之下，暫存檔格3 〇 〇所擁有 之可用以窝入邏輯1至記憶體元件3 1 4的時間只是其所擁有 之可用以寫入邏輯0至記憶體元件3 1 4之時間的一小部份。 當寫入致能線3 0 6之訊號受到致能且正寫入邏輯1至寫入 資料線3 02時’寫入資料線302之高訊號將由反相器316反 相成爲一低電壓。因爲反相器316是較反相器30S更具威力 之裝1，反相器3 1 6能夠拖拉相當大量之電流通過N Μ 0 S電 晶體3 1 0而其淨效應是設定記憶體元件3 1 4成爲邏輯0。 NMOS電晶體3 12在此過程中會協助NMOS電晶體3 10,但 是主要之工作仍是由NMOS電晶體310來達成= 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 訂 319839 經濟部中央標準局負工消費合作社印製 A7 ____B7五、發明说明（6 ) 當一邏輯〇寫入至寫入資料線3〇2時，此低電壓是由反相 器3 0 8反相成爲一高電壓。在此種情形之下，N Μ 0 S電晶體 3 1 0施加一高電壓至記憶體元件3 1 4。但是，此高電壓由於 跨越NMOS電晶體3 10之臨限電壓降而衰減。另一方面，反 相器3 08拖拉電流通過NMOS電晶體3 1 2並致能一通往記憶 體元件3 1 4之低訊號。但是，因爲反相器3 08小於反相器 3 16，反相器308無法如同反相器3 16經由NMOS電晶體 3 10拖拉記憶體元件3 1 4至一較低電壓一樣快速來經由電晶 體；3〗2拖拉記憶體元件3 1 4至一低電壓=淨結果是寫入邏輯 0至記憶體元件3 14之速度低於寫入邏輯1至記憶體元件3 14 的速度。但是，如此並不會造成問題，因爲通常可用以寫 入邏輯0之時間遠多於可用以寫入邏輯1之時間。 圖4展示根據本發明之另一暫存檔格。展示於圖4之暫存 檔格具有多重讀取蜂及寫入埠。連接至寫入資料線4 1 4之反 相器（如所示之反相器3]6)未展示於圖4 °選擇適當之寫 入資料線或適當之寫入致能線所需的解碼器也未受到展示 ，因爲該等裝置在本技術領域爲眾所知。 寫入致能線4 12連接至NMOS電晶體408及NMOS電晶體 4 10之閘極。爲一給定循環所致能之特定寫入致能線將指明 那一寫入資料線4〇6能夠寫入資料至記憶體元件404，讀取 電路402是用以自記憶體元件4〇4擷取資料。 雖然本發明一直特別參照一較佳實例來展示及説明，熟 悉本技術領域者應可瞭解在不脱離本發明之精神及範疇以 下可對本發明之型式及細節進行各種改變。 --- —.______- 9 ~ 本紙張尺度朝巧Μ規格（210>< 297公釐) "—— H-— ·‘·1.....- - _ (請先閱讀背面之注意事項再填寫本頁) 裝 訂1. 1T Ministry of Economic Affairs Central Bureau of Standards, Consumer Labor Cooperation, Social Printing A7 __________B7 _ V. Description of Invention (3) These and other objectives can be achieved as follows. This case provides a temporary file with a memory element. The first switch is connected to a node of the memory element 'and the second switch is connected to another node 3 of the memory element. The switches may be NMOS transistors. The first switch applies high voltage or low power I to the memory device, depending on the binary value to be written. The second switch applies a voltage to another node of the memory device. The voltage applied by the second switch is the logical complement of the voltage applied by the first switch. In this way, a "push-pull effect" is generated at the opposite node of the memory device, and the binary value can be highly efficient Please write the following detailed written description to understand the aforementioned and other objectives, features, and advantages of the present invention. Brief description of the drawings According to k is a novel feature of the features of the present invention is described in the attached patent application However, when reading the following detailed description of an exemplary example with reference to the following drawings, it should be easiest to understand the present invention itself, as well as a preferred mode of use, other objectives and advantages, among which: Figure 1 shows a Before the technical circuit to a temporary storage grid; FIG. 2 depicts another technical circuit before writing to the temporary storage grid; FIG. 3 shows a circuit for nesting to the temporary storage grid according to the present invention; and FIG. 4 shows A circuit with multiple read ports and write ports according to the present invention. Preferred Example Detailed Description FIG. 3 shows a circuit for writing to a temporary file cell according to the invention. Temporary file cell 300 One pair for > 4 "〇3 transistor, transistor 3i〇 NM〇s & nm〇s transistor 312. The NMOS transistor 31 is connected to the memory element at node 311. The paper size is in accordance with the Chinese National Standard Falcon (CNS) A4 specification (21〇 < 297) (please read the precautions on the back before filling out this page). The Ministry of Economic Affairs, China Bureau of Standards, Beigong Consumer Co., Ltd. Du Printed A7 _________B7 V. Description of the invention (4) Part 3 14 and the NMOS transistor 3 U is connected to the memory element at node 3 13. At the same time, an inverter 308 is provided at Write data complement line 3〇4 (the signal appearing in data complement line 3 〇4 is the complement of the signal appearing in write data line 3 〇2. The configuration of these components as shown in Figure 3 makes The data can be written to the memory element 3 1 4 in a fast and efficient manner. As mentioned above, the write data line 3 02 is inverted by the inverter 3 16. Compared to the inverter 308, Inverter 316 is a relatively large device, because inverter 316 must provide its output to some other memory elements not shown in FIG. 3, ΝΜ Ο S transistor 3 1 0 is used to apply write data supplement Number line 3 〇4 to the node 3 1 1 of the memory element 3 1 4. The NMOS transistor 3 1 0 is composed of the write enable line 3 0 6 to control the write enable line 3 0 6 also controls the switching of NMMOS transistor 3 1 2. NMOS transistor 3 12 applies a signal to the node 3 1 2 of the memory element 3 14 and the signal is The complement of the signal applied by Ν Μ 0 S transistor 3 1 0. This complementary signal is caused by the inverter 3 08 located in the write data complement line 3 04. Ν Μ Ο S transistor 3 1 0 and The net effect of Ν Μ Ο S transistor 3 1 2 is the "push-pull effect" for the memory element 3 1 4. "When NM MOS transistor 3 1 0 or Ν Μ 0 S transistor 3 1 2 is applied high When the signal is applied to the node 3 1 3 of the memory element 3 1 4, another transistor applies a low signal to the other node of the memory element 3 1 4. The net result of applying the complementary signal to the memory element 3 1 4 is A fast and efficient way to switch the state of the memory devices 3 1 4. Another advantage of the temporary storage cell 3 00 over the circuit shown in FIG. 2 is that the inverter 308 is placed on the write data line instead of writing Into the enable line. Because the width of the temporary files is usually much greater than their depth (for example, a temporary eaves grid can contain 16 registers, the paper size is suitable for China Home Standard Falcon (CNS) A4 Specification (210X297mm) (Please read the precautions on the back before filling out this page) Printed by the Ministry of Economic Affairs Tsing Standards Bureau Beigong Consumer Cooperative Printed 318839 A7 --------- --- B7_ 5. Description of the invention (5)-and each temporary storage is 64 bits, then the temporary storage is 6 4 grids wide and 16 grids deep), ^ adds an inverse benefit to the data line The impact on performance is lower than that caused by adding an inverter into the enable line. Another advantage of temporary storage grid 3 0 0 is that the speed of writing logic 1 is faster than the speed of writing logic 0. This is important because in many dynamic logic circuits, the initial output of the circuit is logic 0. If a particular dynamic logic circuit is finally allowed to be * 0 ', then the output of that circuit will never need to be changed. At the same time, normally the write enable line 306 is expected to become valid before the data written into the data line 3 〇2 becomes valid. Therefore, when the temporary storage cell 300 is requested to write logic 0 to the memory element 3 14, the temporary The archive grid 3 00 usually has all the time that the write enable signal is high to write logic 0 to the memory element 3 1 4. On the other hand, the temporary file cell 3 00 has far less time to write logic 1 to the memory element 3 1 4. This time reduction occurs because the signal written to the data line 302 can change from logic 0 to logic 1 at the end of the period when the signal written to the enable line 306 is enabled. In this case, the time that the temporary file cell 300 can use to nest logic 1 to the memory element 3 1 4 is only available to write logic 0 to the memory element 3 1 4 A fraction of time. When the signal of write enable line 306 is enabled and logic 1 is being written to write data line 302, the high signal of write data line 302 will be inverted by inverter 316 to a low voltage. Because the inverter 316 is a more powerful device 1 than the inverter 30S, the inverter 3 16 can draw a considerable amount of current through the N M 0 S transistor 3 1 0 and its net effect is to set the memory element 3 1 4 becomes a logic 0. NMOS Transistor 3 12 will assist NMOS Transistor 3 10 in this process, but the main work is still achieved by NMOS Transistor 310 = This paper size is applicable to China National Standard (CNS) A4 specification (210X297mm) (please Read the precautions on the back first and then fill out this page) Binding 319839 Printed by the Ministry of Economic Affairs Central Standards Bureau Negative Consumers Cooperative A7 ____B7 5. Invention Description (6) When a logic 〇 is written to the write data line 3〇2, this The low voltage is inverted by the inverter 308 into a high voltage. In this case, the N MOS transistor 3 10 applies a high voltage to the memory device 3 1 4. However, this high voltage is attenuated by the threshold voltage drop across the NMOS transistor 310. On the other hand, the inverter 3 08 draws current through the NMOS transistor 3 1 2 and enables a low signal to the memory device 3 1 4. However, because the inverter 3 08 is smaller than the inverter 3 16, the inverter 308 cannot pass through the transistor as quickly as the inverter 3 16 drags the memory element 3 14 to a lower voltage through the NMOS transistor 3 10. ; 3〗 2 Dragging memory element 3 1 4 to a low voltage = the net result is that the speed of writing logic 0 to memory element 3 14 is lower than the speed of writing logic 1 to memory element 3 14. However, this does not cause a problem, because it usually takes more time to write logic 0 than it can write logic 1. Fig. 4 shows another temporary frame according to the present invention. The temporary file shown in Fig. 4 has multiple read and write ports. The inverter connected to the write data line 4 1 4 (inverter 3 as shown) 6) is not shown in Figure 4 ° Decoding required to select the appropriate write data line or the appropriate write enable line Devices have not been shown because these devices are well known in the art. The write enable line 4 12 is connected to the NMOS transistor 408 and the gate of the NMOS transistor 4 10. The specific write enable line enabled for a given cycle will indicate which write data line 406 is capable of writing data to the memory element 404, and the read circuit 402 is used from the memory element 40 Retrieve data. Although the present invention has been shown and described with particular reference to a preferred example, those skilled in the art should understand that various changes can be made in the types and details of the invention without departing from the spirit and scope of the invention. --- --.______- 9 ~ The size of this paper is toward the specifications of Qiao M (210 > < 297mm) " —— H-— · '· 1 .....--_ (Please read the back Matters needing attention before filling this page)