KR19980032268A - Register File Cell Circuit Compatible with Dynamic Logic - Google Patents

Abstract

The present invention relates to a cell circuit which is a basic unit of a register memory embedded in a microprocessor. In the configuration of the register cell circuit according to the present invention, a first switch is connected to one node of the memory element, and a second switch is connected to the other node. These switches can be NMOS transistors. The first switch applies either high potential or low potential to the memory element depending on the binary value to be written. The second switch applies a voltage to the other node of the memory element. The voltage applied by the second switch is a logical complement of the voltage applied by the first switch. In this way, a push-pull effect is generated between nodes opposite to the memory element, so that binary values can be efficiently written to the memory element.

Description

Register File Cell Circuit Compatible with Dynamic Logic

The present invention relates generally to dynamic circuits, and more particularly to efficient writing to register file cells in a dynamic circuit.

In modern microprocessors, the ability to quickly write to the registers inside the microprocessor is very important. This internal register is often used to store the result of the calculation performed by the microprocessor. If the result of such an operation cannot be quickly stored in a register, the ability of the microprocessor to perform computational operations at high speed may be impaired.

Groups of registers are often known as register files. A register file is an array of memory elements, each row of which represents one register. For example, the register file can be an array of 16 x 64 memory elements. This register file will contain 16 individual 64-bit registers. As mentioned above, the individual storage units that make up one register are referred to as memory elements. As with almost all digital memories, one memory element can store either logic 1 (ie, high potential level) or logic 0 (ie, low potential level).

Figure 1 illustrates one of the prior art configurations for writing a single bit into a single register file cell. An NMOS transistor 106 is provided to allow the write enable line 104 to control the writing of data in the write data line 102 to the memory element 108. If the write enable line 104 is at high potential, data in the write data line 102 is written to the memory element 108. This configuration works satisfactorily in some situations. However, if the power supply voltage decreases, and thus the voltage representing logic 1 decreases, logic 1 can be reliably and quickly written to memory element 108 by a threshold voltage associated with NMOS 106. It may be missing.

FIG. 2 illustrates one circuit that can overcome some of the shortcomings of the circuit shown in FIG. 1. However, the circuit shown in Fig. 2 solves this disadvantage, but causes a new problem. Instead of including a single NMOS transistor such as the circuit shown in FIG. 1, the circuit shown in FIG. 2 includes an NMOS transistor 206 and a PMOS transistor 210. Logic 1 may be written to memory element 208 without causing a threshold voltage drop across NMOS transistor 206 by the addition of PMOS transistor 210 and thus accompanying inverter 212.

The advantage of adding the PMOS transistor 210 and the inverter 212 is not without sacrifice. Adding PMOS transistors, unlike other NMOS transistors, occupies an additional surface area and slows the overall performance of the circuit. This is because PMOS transistors are generally twice as weak as their corresponding NMOS transistors. In addition, adding an inverter to the write enable line adds across the entire width of the register, thereby adding additional performance penalties to the write of the register as a whole.

Accordingly, there is a need for a circuit that can reliably change the state of a register file cell at high speed without consuming excessive amounts of surface area or adding a significant delay or load to the circuit as a whole.

One object of the present invention is to provide an apparatus capable of writing to a register file cell at high speed.

It is a further object of the present invention to provide a device that is easy to fabricate while requiring a minimum surface area.

It is still another object of the present invention to provide an apparatus capable of writing logic 1 at higher speed than being able to write logic 0 into a register file cell.

This object, together with other objects, is achieved as follows. A register file cell containing a memory element is provided. The first switch is connected to one node of the memory element and the second switch is connected to the other node of the memory element. Such switches may be NMOS transistors. The first switch applies either high potential or low potential to the other node of the memory element, depending on the binary value to be written. The second switch applies one voltage to the other node of the memory element. The voltage applied by the second switch is a logical complement of the voltage applied by the first switch. In this way, a kind of push-pull effect is created on the opposite nodes of the memory element, and binary values are efficiently written to the resist file cell.

The above objects, aspects, and advantages of the present invention will become apparent from the following detailed description in conjunction with others.

1 is a circuit diagram according to the prior art for writing to a register file cell.

2 is a circuit diagram according to another prior art for writing to a register file cell.

3 is a circuit diagram for writing to a register file cell in accordance with the present invention.

4 is a circuit diagram including multiple read and write ports in accordance with the present invention.

Explanation of symbols for main parts of the drawings

102, 202: write data line 104, 204: write enable line

106,206: NMOS transistors 108,208: memory elements

210: PMOS transistor 212: inverter

300: register file cell 302: write data line

304: write data inversion line 306: write enable line

308, 316: Inverter 310, 312: NMOS transistor

311, 313: node 314: memory element

402 read circuit 404 memory element

406: Write data line 408, 410: NMOS transistor

412 record enable line

Features and aspects of the invention are set forth in the appended claims. However, the preferred embodiments and the additional objects and advantages of the invention, as well as the invention itself, will be best understood by reference to the following detailed description of exemplary embodiments described below when taken in conjunction with the accompanying drawings.

3 illustrates a circuit for writing to a register file cell, in accordance with the present invention. The register file cell 300 provides a pair of NMOS transistors NMOS transistor 310 and NMOS transistor 312. NMOS transistor 310 is connected to memory element 314 at node 311. In addition, an inverter 308 is provided to the write data inversion line 304 (data on the write data inversion line 304 is a complement value of a signal on the write data line 302). This arrangement of components as shown in FIG. 3 allows data to be written to the memory element 314 in a fast and efficient manner.

As described above, the write data line 302 is inverted by the inverter 316. Inverter 316 is a relatively large device when compared to inverter 308 because its output must be supplied to a number of other memory elements not shown in FIG. An NMOS transistor 310 is provided to supply the write data inversion line 304 to the node 311 of the memory element 314. NMOS transistor 310 is controlled by a write enable line 306. The write enable line 306 also controls the switching of the NMOS transistor 312. NMOS transistor 312 applies a signal to node 312 of memory element 314 that is an inverted value of the signal applied by NMOS transistor 310. This inversion signal is generated by the inverter 308 located on the write data inversion line 304.

The overall net effect of NMOS transistor 310 and NMOS transistor 312 is to create a push-pull effect on memory element 314. While either the NMOS transistor 310 or the NMOS transistor 312 is applying a high potential signal to the node 313 of the memory element 314, the other transistor is low on another node of the memory element 314. Will apply a potential signal. Applying a complementary signal to the memory element 314 results in the state of the memory element 314 being switched in a fast and efficient manner as a whole.

Another advantage that the register file cell 300 has over the circuit shown in FIG. 2 is that the inverter 308 is located on the write data line rather than the write enable line. Because register files are often much wider than their depths (for example, a register file that contains 16 registers, each register is 64-bit, is 64 cells wide and 16 cells deep), so the inverter can be placed on the data line. In addition, it has less impact on performance than adding an inverter to the write enable line.

Another advantage of register file cell 300 is that logic 1 is written faster than logic zero. This is important for many dynamic logic circuits because the initial output of the circuit is logic zero. If a particular dynamic logic circuit finally calculated a value of zero, the output of that circuit would never have changed. It is also common for the write enable line 306 to first become valid before the data on the write data line 302 becomes valid. Thus, when register file cell 300 is required to write zeros to memory element 314, register file cell 300 often writes zeros to memory element 314 as the write enable signal is at a high potential. You have the whole time.

On the other hand, register file cell 300 will have much less time when writing logic 1 to memory element 314. This shortened amount of time occurs because the signal on the write data line 302 will change from 0 to 1 at the end of the time interval at which the signal on the write enable line 306 will be finalized. In this case, the register file cell 300 will only have a smaller amount of time when writing 1 to the memory element as compared to the time when writing 0 to the memory element 314.

When the signal on the write enable line 306 is asserted and logic 1 is written on the write data line 302, the high potential signal on the write data line 302 is lowered by the inverter 316. Will be reversed. Because inverter 316 is a more powerful device than inverter 308, it is possible to draw a relatively larger amount of current through NMOS transistor 310, and have the effect of setting memory element 314 to logic zero. Cause. In this process, the NMOS transistor 312 assists the NMOS transistor 310, but the main effect is that generated by the NMOS transistor 310.

When logic 0 is written on write data line 302, this low potential is inverted to high potential by inverter 316. In this case, NMOS transistor 310 applies a high potential to memory element 314. However, this high potential is attenuated by the threshold voltage drop across the NMOS transistor 310. On the other hand, inverter 308 draws current through NMOS transistor 312 and determines low potential with memory element 314. However, because inverter 308 is not as large as inverter 316, inverter 308 is faster than inverter 316 drawing memory element 314 to low potential through NMOS transistor 310. The memory element 314 is not drawn to low potential through the transistor 312. Overall, writing zeros to the memory element 314 results in slower than writing ones. However, this usually does not cause a problem because recording zero takes much more time than recording one.

4 illustrates another register file cell in accordance with the present invention. The register file cell shown in FIG. 4 includes multiple read and write ports. The inverters (shown as inverter 316 in FIG. 3) to be connected to the write data lines 414 are not shown in FIG. 4. Also, the decoder needed to select the appropriate write data line and the appropriate write enable line is not shown, as these devices are well known in the art.

The write enable line 412 is connected to the gates of the NMOS transistor 308 and the NMOS transistor 410. The particular write enable signal established in a given cycle will specify which write data line 406 can write data to the memory element 404. Read circuitry 402 is provided to extract data from memory element 404.

Although the present invention has been specifically described and illustrated with reference to preferred embodiments, those skilled in the art will understand that various changes may be made in form and detail without departing from the spirit and scope of the invention.

The present invention relates to a cell circuit which is a basic unit of a register memory embedded in a microprocessor. In the configuration of the register cell circuit according to the present invention, a first switch is connected to one node of the memory element, and a second switch is connected to the other node. These switches can be NMOS transistors. The first switch applies either high potential or low potential to the memory element depending on the binary value to be written. The second switch applies a voltage to the other node of the memory element. The voltage applied by the second switch is a logical complement of the voltage applied by the first switch. In this way, a push-pull effect is generated between nodes opposite to the memory element, so that binary values can be efficiently written to the memory element.

Claims (17)

A circuit for storing binary values in a memory element, the circuit comprising: ① memory elements, A first switch connected to a first node of the memory element and controlled by a write enable signal, the first switch applying a first voltage to the first node; A second switch connected to a second node of the memory element and controlled by a write enable signal, the second switch applying a second voltage to the second node; The binary value can be efficiently stored in a memory element. The method of claim 1, Wherein the first switch and the second switch are NMOS transistors. The method of claim 1, The first voltage applied by the first switch to the first node of the memory element represents logic 1, the second voltage applied by the second switch to the second node of the memory element represents logic 0, and by the memory element Circuit whose voltage level is logic one. The method of claim 1, The first voltage applied to the first node by the first switch represents logic 0, the second voltage applied to the second node by the second switch represents logic 1, and the voltage level held by the memory element is logical. Circuit representing zero. The method of claim 1, The circuit, A first inverter connected to the second switch, Further comprising a data line connected to the first switch and the first inverter, The data line communicates a binary value to be written to the memory element to a first switch, wherein the first voltage applied by the first switch represents the binary value, and the first inverter returns the complement of the binary value. And communicate with a second switch such that a second voltage applied by the second switch represents a complementary value of the binary value. The method of claim 5, And a second inverter connected to the data line, wherein the second inverter is larger than the first inverter. A multi-port circuit for writing binary values into memory elements, the multi-port circuit comprising: ① memory elements, ② includes multiple switch pairs, The first switch of the pair of switches is connected to a first node of a memory element to apply a first voltage to the first node, and the second switch of the switch pair is connected to a second node of the memory element to a second node to the second node. A voltage is applied, the switch pairs are controlled by a write enable signal, and the write enable signal enables a switch pair selected from the plurality of switch pairs to write a binary value to a memory element Circuit. The method of claim 7, wherein And the plurality of switch pairs receive a plurality of data signals such that the selected switch pair communicates the selected data signal to a memory element. The method of claim 8, And a plurality of first inverters, wherein one first inverter is connected between the first and second selected switches to invert the data signal such that the second node receives the logical complement value of the first node. The method of claim 7, wherein And the switches of the switch pairs are NMOS transistors. The method of claim 7, wherein The circuit further comprises a plurality of second inverters for inverting the data signal received by the pair of switches, wherein the second inverter is larger than the first inverter such that logic 1 is written to a memory element faster than logic 0. Multi-port circuit. A circuit for storing binary values in a memory means, the circuit comprising: ① memory means, (1) first switching means connected to a first node of the memory means and controlled by a write enable signal, for applying a first voltage to the first node; ③ second switching means connected to a second node of the memory means and controlled by a write enable signal, for applying a second voltage to the second node; The binary value can be efficiently stored in the memory means. The method of claim 12, Circuit wherein the first switching means and the second switching means are NMOS transistors. The method of claim 12, The first voltage applied by the first switching means to the first node of the memory means represents logic 1, and the second voltage applied by the second switching means to the second node of the memory means represents logic 0, the memory means Circuit wherein the voltage level held by is logic one. The method of claim 12, The first voltage applied to the first node by the first switching means represents a logic zero, and the second voltage applied to the second node by the second switching means represents a logic one and the voltage level held by the memory means. The circuit representing this logic zero. The method of claim 12, A first inverter connected to the second switching means, Further comprising a data line connected to the first switching means and the first inverter, The data line communicates the binary value to be written to the memory means to the first switching means, wherein the first voltage applied by the first switching means represents the binary value, and the first inverter complements the binary value. And communicate with the second switching means such that the second voltage applied by the second switching means indicates the complement of the binary value. The method of claim 16, And a second inverter connected to the data line, wherein the second inverter is configured to be larger than the first inverter, so that logic 1 can be written to the memory means faster than logic zero.