TW313686B - - Google Patents
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- TW313686B TW313686B TW085115933A TW85115933A TW313686B TW 313686 B TW313686 B TW 313686B TW 085115933 A TW085115933 A TW 085115933A TW 85115933 A TW85115933 A TW 85115933A TW 313686 B TW313686 B TW 313686B
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- lead
- wafer
- frame
- wire
- lead wire
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- Engineering & Computer Science (AREA)
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- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
五、發明説明(1 ) 經濟部中央襟準局員工消費合作社印製 發明之背景 養明之技術範圍 本發明係關於-薄塑料封裝半導體包裝及其製法。 習知技術之概述 在半導體錄之製財,—料體晶料常目定在屬於 引出線框架之-部分之金屬托架上。導線在半導體晶片上 之塾片及引緣框架之5丨出線祕接。接著晶片導線 部分引出線框架之引出線被封裝,通f採用轉及一模 方法來封裝,且引出線向外伸展出封裝之外。所得到的包 裝之厚度係取㈣每-金屬托架及在其上之晶片厚度,= 晶片頂端到導線f曲部分之頂端之距離包含—小的餘裕以 容忍誤差及任何源自於封裝之顧外,的厚度。 隨著電子裝置之持績小型化,例如膝上型電腦、大哥大 電話等’需要製造歧前更薄之半導體&。達到 的 之明類的方法並不永遠可行及/或不能提供所需之g裝寬 度縮減量。雖然可減少金屬托架之厚度,但會導致托架難 以處理,故此法大體上並不可行。同樣之問題在將丰導體 晶片製造得更薄時也會出現。例如,矽,最廣泛用於半導 體裝置製造之半導體材料,其非常的易碎,如果太薄時常 常會在製造時破裂。欲使矽變薄,通常在製造後及封裝前 研磨矽晶片之後表面,然而,此背面研磨通常限於不小於 約10至12密爾(mil)厚之矽以最小化現行以更昂貴方法製 造之裝置之破裂,此裝置仍需接受包裝及其他可能的製造 步驟。更進一步之研磨被發現會造成不可接受之晶圓破裂 (請先閑讀背面之注意事嗲再填寫本頁」 m -I— - - i n -- -- ί ·
,----—I— II - -- . 1 I 訂--- 气 .I · n fn nn 經濟部中央橾準局員工消費合作社印裝 313686 Δ7 Α7 ___ Β7 五、發明説明(2 ) 之風險。背後研磨步驟亦出現將污染物導入晶圓製造環境 之問題’其可能導致正在製造之裝置產生缺陷。吾人皆知 半導鱧装置必需在非常乾淨的環境中製造,囡爲即使微量 之直徑爲微米的極小粒子降落在正在製造之裝置上也會引 起問題,例如短路,原因在於正在製造之裝置的尺寸。當 一部分之業者致力於最小化半導鱧裝置包裝厚度時,導線 之弩曲及/或包裝也可望在未來改進,在此不考慮這些製 造步踩。 . ,-發明之综合説明 依照本發明,前迷之問題被最小化且提供一比習知技術 類似之包裝更薄之半導體裝置包裝,且仍保有相對較厚之 晶片及相對較厚之引出線框架所得到之良好的特性。 簡言之,此目的係藉由從晶片之背後除去金屬托架及將 引出線框架配置在一具有包含晶片表面之構件之上表面及 一包含對立於構件所包含之表面之晶片表面之下表面之空 間中。 如前所述者係藉由提供一用於相對於一半導體晶片來定 位引出線框架之工具而達成,其中引出線框架與晶片隔開 一段距離。一半導體晶片具有一包含電子成份在其上之表 面且其在垂直於該表面之方向上之厚度遠小於其長度及寬 度尺寸。一引出線框架配置在該工具上,其具有一基底部 分及從基底部分伸展出來之引出線,且與該晶片隔開,該 引出線框架從基底部分至引出線之厚度尺寸不大於晶片之 厚度。導線在引出線及晶片間熔接,導線與一部分之引出 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) ----------、 ^ M 為— (請先閲讀背面之注意事項再填寫本頁) B7 五 '發明説明(3 ) —--- 線框架係密封的。引出線框架紀置在工具上之—*間中, 此空間係以晶片表面做爲其中―表面並以與該其^一表面 對政晶片表面做爲-相對之表面。導線具有足夠之硬度 以防止引出線框架移出該空間之外。 圖式之簡單 圖1係-0.5毫米厚之半導髏裝置及使用習知技術之製 造技術所製造包裝之示意圖; 圖2係-0.5毫米厚之半導體裝纽㈣本發明所製造 之包裝之示意圈; 圖3&係一用於本發明之工具的頂視圖,在其上配置有一 引出線框架條狀物;及 _圖31)係一沿著圖3a中之31)^31)線之剖視圖。 較佳實施例之#細描谏 經濟部中央標準局員工消費合作社印製 雖然現行之塑膠半導體裝置包裝係毫米(4〇密爾)厚 ,但希望能夠建構約0.5毫米(20密爾)厚之包裝。—可以 習知技術製造之0.5毫米包裝之例子顯示在圖1中。該包 裝包含一被背面研磨至6密爾厚之矽晶圓】。具有此等尺 寸之晶圓當它們亦具有6、8或12英吋之直徑時係非常難以 提供的,而此等直徑係現行技術水準中最經濟可得之晶圓 尺寸。引出線框架3通常爲具有或不具有額外電鍍(鎳、 鈀等)之銅且被縮減至3至4密爾之厚度。導線5 (可爲 金、銅、紹等)被彎曲且需要4至5密爾之彎曲高度。如 此在晶片之下及彎曲之導線最頂端之上只留下约3密爾之 塑膠7。如此之包裝不只囡前述之薄的晶圓及引出線框架 本紙乐又度適用中國國家標準(CNS ) A4规格(210X297公嫠) A7
而產生問題,另外,塑膠7會產生些許力量以將包裝固定 在一起,囡此會造成不足之熱性能(即散熱)。在引出線框 架位於墊片9下方之區域,在銅的下方可能沒有塑膠因此 應力可能會更嚴重。因此,依照現行技術水準,顆而易知 圖1所示之型式之實施例並非一在商業上提供厚度约〇5 毫米之包裝可行之方法。因此,需要另一方法。 現在參考圖2,其顯示一依照本發明之半導體包裝。該 包裝包含一厚度約11密爾之晶片21,此厚度之晶片係在半' 導體製造中常用者,藉此最小化使用比前述之晶圓更薄之 曰曰圓之間題。而且,省略背面研磨以達到6密爾厚度之步 碟,藉此可節省此步驟之花費,並最小化前述之製程污染 。頦外的矽之可利用性(當晶片是矽時)提供一熱分散/熱 下降’減少引出線框架之成本且除去晶粒附著運作所需之 成本/時間。晶片21之背面可在包裝之表面,藉此提供直 接接觸以额外地向外散熱。 弓丨出線框架23沒有晶片墊片且可完全位於晶片之厚度尺 寸中,藉此容許使用傳統之金屬厚度。引出線框架23在熔 接操作期間可以"塊狀物"或其他支撐物支撐,如後所述。 餘接係傳統之引出線框架23及墊片25在晶片21上之低f 曲稼接,且高度或厚度約4至6密爾(只要高度容許)。因 此’球烊或點焊係與習知技術中的相似且不比它困難。另 〜種較佳之熔接型式係帶狀熔接(鋁、铜),可得到高硬度 及高強健性。球焊間距可能低於4密爾且趨近於2密爾。 假如銅導線被用於溶接,可選擇薄的(用於特别小的球焊) 一 6 - 本紙張尺度適用中國國家榡準(CNS ) M規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁} 經濟部中央榡準局員工消費合作社印製
經濟部中央揉準局員工消費合作社印裂 A7 ________B7 _ 五、發明説明(5 ) 或厚的U .2至1.5密爾)以降低電阻及感應係數。總之,銅 之硬度會增加包裝之強健。藉由適當的燒化可仍然維持球 的小尺寸。導線27所需之特性爲它需有足夠的硬度v乂支撐 引出線框架及晶片在導線熔接之前及導線熔接之後大體上 有相同的關係,即兩者必需在同樣的平面。接著以標準的 方法進行塑膠封裝。 欲依照本發明建構半導體裝置,參考圖3a及3b,一工具 41係用於接受引出線框架45之條狀物43,該X具包含〜位. 於每一引出線框架中間部分之凹處47及一對向上伸展之手 指49’其相對於每一引出線框架且設計用於契合在條狀物 45中之孔51以準確地對齊在工具上之條狀物及每一引出線 框架。凹處47相對於晶片厚度义寸,爲小尺寸,凹處之深度 僅足以在導線熔接製造步驟中維持晶片在其中且維持引出 線框架在晶片之厚度尺寸中。晶片21係置於凹處47中且導 線27接著以前述之方法在引出線框架佔之引出線23及晶片 21上之熔接墊片25間熔接(以球焊或較佳者爲帶狀焊接技 術焊接)。導線有足夠之硬度以維持在晶片21及引出線框 架23間之平面性,其中平面性係以工具41提供。導線之硬 度係以帶狀熔接及//或修改導線之成份以得到所需之硬度 量:該裝置可接著沿著在引出線框架間之區域53被分開並 接著以塑膠29封裝或整個條狀物可在所有的裝置被同時封 裝時從工具41處移開。條狀物之邊緣部分31接著被移除且 引出線框架之引出線被切斷(如果需荽時)及彎曲(如果需要時) 以提供疋成之裝置。結果是—可以一0.5毫米之厚度提供 本紙張碰適财II ) A«1 (請先閱讀背面之注意事項再填寫本頁) ί. mu nfn nfl nn ^ϋϋ I^lll mu —flu— fn^ • —^n 111 n^— nn nn 313686 A7 --- B7 五、發明説明 之薄的包裝,仍然保有一厚的晶片及一厚的引出線框架, 以提供此等結構之優點。 在以上詳細説明中所提出之具體的實施態樣或實施例僅 爲了易於説明本發明之技術内容,本發明並非狹義地 於該實施例,在不超出本發明之精神及以下、 圍之情況,可作種種變化實施。 〈請專利載 (請先^^^^^:北^:-面之注意事^再填蹲本1^
、π 0 Bam mu vm a^it— 1^1 經濟部中央標準局舅工消費合作社印製
« mK ^im nn m -nil 1--1 i···— In ---n— .—----
Claims (1)
- A8 B8 C8 D8 '申請專利範圍 I —種半導體包裝,包含: (a) —具有一包含電子成分在其上之表面及一對立之 表面之半導體晶片’該晶片在垂直於該表面之方向上之 厚度遠少於在長度和寬度之尺寸; (b) —具有一基底部分及從該基底部分伸展出來之引 出線之引出線框架’該引出線框架被與該晶片隔開,該 5丨出線框架從該基底部分至該引出線之厚度尺寸不大於 該晶片之該厚度; 、 (c) 導線,在該引出線及該晶片間熔接;及 (d) —密封物,封裝該晶片、該導線及一部分該引出 線框架。 2. 如申請專利範園第1項之包'裝,其中該弓丨出線框架係釔 置在一空間中,該空間包含該晶片及包含在其對立之表 面之該表面。 3. 如申請專利範圍第2項之包裝,其中該導線具有足夠之 硬度以防止該引出線框架在製造該包裝之期間移出該空 間之外。 一 4· 一部分建構之半導體裝置,包含: (a) —具有一包含電子成分在其上之表面及一對立之 表面之半導體晶片,該晶片在垂直於該表面之方命上之 厚度遠少於在長度和寬度之尺寸;及 (b) —具有一基底部分及從該基底部分伸展出來之引 出線之引出線框架,該引出線框架被與該晶片隔開,該 弓丨出線框架從該基底部分至該引出線之厚度尺寸不大於 本紙張尺度適用中國國家標準(CNS ) Α4规格(210 X 297公釐〉 «- ----- 1-.. --------、裝—— (請先閲讀背面之注意事項再填寫本頁) 、1T 經濟部中夬檩準局員工消費合作社印製六、申請專利範圍 經濟部中央標準局員工消費合作社印製 該晶片之該厚度。 5‘如申請專利範園第4項之裝置,其中該引出線框架係配 置在一空間中,該空間包含該晶片及包含在其對立之表 面之該表面。 6. 如申請專利範園第5項之裝置,其中該導線具有足夠之 硬度以防止該引出線框架在製造該裝置之期間移出該空 間之外。 7. —種製造半導體包裝之方法,包含下列步驟: 〜 (a) 提供一用於相對於一半導體晶片定位一 5丨出線框 架之工具,其中該引出線框架與該晶片隔開; (b) 在該工具上配置一具有一包含電子成分在其上之 表面及一對立之表面之半導'體晶片,該晶片在垂直於該 表面之方向上之厚度遠少'於在長度和寬度之尺寸; (c) 在該工具上置一具有一基底部分及從該基底部 分伸展出來之引出線之引出線框架,該引出線框架被與 該晶片隔開,該引出線框架從該基底部分至該引出線之 厚度尺寸不大於該晶片之該厚度; (d) 在該引出線及該晶片間熔接導線;及 (e) 封裝該晶片、該導線及一部分該引出線框架。 8. 如申請專利範圍第7項之方法,其中該引出線框架係配 置在一空間中,該空間包含該晶片及包含在其對立之表 面之該表面。 9. 如申請專利範園第8項之方法,其中該導線具有足夠之 硬度以防止該引出線框架在製造該包装之期間移出該空 喊.d.旬 -10 - 私衆 ------^---| 裝-------- 訂------^ , (請先閲讀背面之注意事項再填寫本頁) 本^張尺度適用中關( CNS ) Α4^_ ( 210X297^^1 '" 313686 A8 B8 C8 ----—__ D8 申為專利範圍 間之外。 10·—種製造半導體包裝之方法,包含下列步驟: (a) 提供—用於相對於一半導體晶片定位一引出線框 架之工具,其中該引出線框架與該晶片隔開; (b) 在該工具上配置一具有一包含電子成分在其上之 表面及一對立之表面之半導體晶片,該晶片在垂直於該 表面之方向上之厚度遠少於在長度和寬度之尺寸; (0在該工具上配置一具有一基底部分及從該基處部 分伸展出來之引出線之引出線框架,該引出線框架被與 該晶片隔開,該引出線框架從該基底部分至該引出線之 厚度尺寸不大於該晶片之該厚度;及 (d)在該引出線及該晶片間熔接導線。 如申請專利範圍第10項之方法,其中該引出線框架係 配置在一空間中,該空間包含該晶片及包含在其對立之 表面之該表面。 12.如申請專利範圍第11項之方法,其中該導線具有足夠 之硬度以防止該引出線框架在製造該包裝之期間移出該 空間之外。 ------------<装---·,---^ I 訂------^、 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員Η消費合作社印製f榡 【家 -國 國 中 用 - 尺 張 紙 公 7 29 X ο 21 /(V 格 規
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US740995P | 1995-11-21 | 1995-11-21 |
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TW313686B true TW313686B (zh) | 1997-08-21 |
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JP (1) | JPH09172032A (zh) |
KR (1) | KR970030730A (zh) |
SG (1) | SG54391A1 (zh) |
TW (1) | TW313686B (zh) |
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JPH01319953A (ja) * | 1988-06-21 | 1989-12-26 | Nec Corp | 半導体装置の製造方法 |
JPH03157944A (ja) * | 1989-11-15 | 1991-07-05 | Sony Corp | 半導体パッケージ |
EP0690499A3 (en) * | 1994-06-30 | 1997-05-28 | Digital Equipment Corp | Molded plastic packaging for semiconductor chip without support |
-
1996
- 1996-11-16 SG SG1996011333A patent/SG54391A1/en unknown
- 1996-11-18 JP JP8306291A patent/JPH09172032A/ja active Pending
- 1996-11-20 EP EP96308408A patent/EP0776039A3/en not_active Withdrawn
- 1996-11-20 KR KR1019960055539A patent/KR970030730A/ko not_active Application Discontinuation
- 1996-12-24 TW TW085115933A patent/TW313686B/zh active
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JPH09172032A (ja) | 1997-06-30 |
SG54391A1 (en) | 1998-11-16 |
KR970030730A (ko) | 1997-06-26 |
EP0776039A2 (en) | 1997-05-28 |
EP0776039A3 (en) | 1999-04-07 |
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