TW312072B - An error detection and correction system for a stream of encoded data - Google Patents

Abstract

The invention provides a decoder of symbols of received data, the data being encoded according to a convolutional encoding scheme and transmitted through a communications channel. The data is punctuated according to a puncturing matrix, and has a plurality of state values which describe a sequence of state transitions. The decoder has a generation unit that accepts the received data for calculating metrics of the transitions thereof. A selector responsive to the generation unit selects a path of transitions corresponding to the path produced by a transmitter of the data stream. A traceback unit maintains historical information representative of sequential decision operations of the selector. A counter is provided for counting illegal state transitions of the path selected by the selector, and a control unit, responsive to the counter, determines a puncture rate and adjusts a puncture phase of the received data. The decoder can be used in a VLSI receiver circuit which is adapted to the reception of QPSK modulated data.

Description

A7 B7 312072 V. Description of the Invention (彳) The present invention relates to processing signals received from communication channels. More specifically, the present invention relates to an integrated signal processing system that receives signals used in video, "Hi-Fi" audio, video, or other high-bit transmission rates. Due to advances in signal processing technology, today's analog signal coding transmission is increasing, and the bit transmission rate in the channel is also increasing. At the same time, new data compression techniques tend to reduce the bandwidth required for acceptable performance of analog information. At present, in the application of digital TV such as digital TV, this technology pursues more efficient transmission of video and audio materials. Various modulation techniques have been applied in digital communications. For example, Quadrature Amplitude Modulation (QAM) is an advanced technology favored by digital communication companies. This method consists of two separate symbol streams, each symbol stream modulating one of the two orthogonal carriers. In fact, QAM is effectively used in applications with low signal-to-noise ratio (snr). In applications with high signal-to-noise ratio, the multi-order QAM format is also used to achieve the spectral effect. For example, 64- and 256-QAM can achieve a spectrum effect of 5-7 bits / sec-Hz in an Internet TV network. The quadrature phase shift key (QPSK) is a special use condition of the general quadrature amplitude modulation (QAM) method, and is effectively used in low signal to noise ratio applications. ITU-T has adopted the DVB QPSK modulation method as the international standard for direct digital transmission of satellites. In Europe, 16-QAM and 64-QAM are used in the DVB standard for digital cable broadcasting. In QPSK, a signal constellation consisting of four symbols is transmitted. Each symbol has a different phase and a fixed amplitude. This method is implemented with the sum of orthogonal components and is expressed by the following formula.

Am = bejQm 7 paper size is applicable to China National Standard (CNS) A4 specification (210X297mm) '---- (please read the note # on the back side first and then fill in this page) -Installation_ Employees Consumption Cooperative of Central Bureau of Standards, Ministry of Economic Affairs Printing 312072 A7 -----__ J1_ V. Description of the invention (2) ~ '-where 6m can be any number in {〇, 疋 / 2, π, 3; r / 2}. Therefore, two sidebands must be transmitted to maintain orthogonal information. Therefore, the main object of the present invention is to improve the device for receiving the stacked coded data at a high transmission rate and issuing an error correction output data stream. A further object of the present invention is to economically implement the miniaturization of a receiving device used for satellite broadcast transmission. This invention provides a transmission and reception system for quadrature phase-shift key data streams. The data stream is randomized, overlapped, interleaved and leaked at the leak rate The device is aligned with the leaky phase, where the data is transmitted in the symbol and in the signal constellation at the symbol rate. The system outputs an error correction data stream. The system has a Q demodulator that receives data at the transmitted symbol rate for conversion i, the analog digital converter of the analog output of the Q demodulator, and the interpolator that receives the sample from the analog digital converter. The timing recovery circuit has a first digital value controlled oscillator, which is under the period τ Operation; a first loop filter, which is coupled to the interpolator and the first digital value controlled oscillator, and has an output that can respond to the difference between the period τ and the received symbol rate. The first digital value The control oscillator responds to the first loop filter and generates a signal representing the interpolation distance between consecutive samples. The interpolator interpolates the received samples according to the interpolation distance and generates a representation The output signal of the sample value is interpolated. A coupled NyquisU wave filter is coupled to the interpolator "Control |," the carrier recovery circuit of the demodulator has a second digital value controlled oscillator. The digital removal rotation circuit is the second digital value. The controlled oscillator generates a response, and receives the in-phase component and the quadrature-phase component of the sampled signal; the phase error estimation circuit is coupled to the output of the derotation circuit, and the second loop filter and the output of the phase error estimation circuit Coupled. The second value-controlled oscillator produces the second loop filter

A7 B7 312072 V. Description of the invention (3 response). The present invention provides a second control device for controlling the interaction between the demodulator, timing recovery circuit, carrier recovery circuit, chopper and output interface. In the first mode In the second mode of operation, there is a constellation rotation unit (concentration of the signal constellation used to rotate the symbol) and the m step internal decoder. The m step internal decoder includes a branch metric calculation unit. It is used to output the branch metric for the selected leakage rate and the selected leakage phase and a plurality of bonus-comparison-selection boxes, which are used to output the value of the metric derived after the path of the same branch metric, and compare the value with all The selected minimum value ... The readjustment unit (ReSCa 丨 丨 ng υηΚ) operates on the output of the add-compare-select block according to the minimum value to readjust the outputs. The state transition module can operate in the first mode to detect The unreasonable state transition of the path measurement metric value, which is selected by the addition, comparison, and selection blocks. The state transition module can output corrections for symbol leakage rate, leakage phase, and rotation And the control branch metric calculation unit to change the selected leakage rate and selected leakage phase according to the estimation of the leakage rate and leakage phase. The state transition module uses the rotation-corrected estimated control conformation to rotate the unit. Synchronization The search unit is enabled in the second mode of operation and responds to the state transition module to identify the synchronization information in the data stream. The traceback module is connected to the addition-comparison_selection box and has a continuous traceback line , Where each row represents all the history data of the selected value of the path determined by the addition_comparison selection box at the same time. Each backtracking row has multiple backtracking elements to accept m bits of each backtracking data, The retrace element is addressed by the pre-decoded selection line according to the content of at least one previous retrace line. The deinterleaver (Deinterleave) is coupled to the m-step internal decoder. An external decoder receives the interleaved data of the deinterleaver , Coupled with a de-randomizer and an external decoder. An output interface is used to output the error correction data stream and is combined with the de-randomizer. This paper size is applicable National Standard (CNS > A4 threat (21Gx297 public envy) I ·-~ Binding line I- (please read the notes on the back first and then fill in this page) Central Bureau of Economic Affairs, Ministry of Economic Affairs, Beige Consumer Cooperative Printed by the Ministry of Economic Affairs Central Sample Printing Bureau Consumer Consumption Cooperation Du Printing 312072 V. Description of the invention (4) — According to the present invention n When the reasonable state transition of the material exceeds the pre-two-state transition module control branch metric calculation material to change the selected leakage rate and The selected leakage phase. According to this article, the “secret” readjustment unit operates on domain comparison_selecting outputs to readjust these outputs to non-negative values. The readjustment of the output should preferably be a function of the previous state. * 2 According to In other aspects of the invention, the output of each chase line is placed on the precharge line, and the branch metric calculation unit processes ⑺ bits at this time. The synchronous search unit provides the information system -_ unit to indicate the search result, where the first control unit resumes the state of the first mode of operation when the number and 7F search results fail. Synchronous search unit money #reverse sequence (sync) byte. The timing recovery circuit and the carrier recovery circuit use feedback technology to process the data previously filtered by the coupled Nyquist filter. The timing recovery and carrier recovery error signals are derived from the following related recovery circuits. According to the diurnal encoding method, the present invention provides a decoder for receiving symbols of encoded data. Mark the data according to the leakage matrix, and there are a plurality of state values describing the continuous state transition from the first state to the subsequent state, where a path is defined by the continuous state transitions. The decoder has a generating unit that accepts the received data for calculation The state transition metric from the first state to the subsequent state 'where the metric reflects a possibility' is that the measurement path follows the path generated by the data transmitter. The selector that responds to the generating unit selects a path generated by a transmitter that conforms to the data stream. The backtracking unit will keep a record of the green selector's experience of continuous decision-making operations. The private paper scale is applicable to China National Standard (CNS) A4 (210X297mm) ----------- t ------ IT ------ 0 (please read the back page first (Note 3 and fill this page again) A7

The counter provides an illegal transition of the path selected by the count selector and the control unit responds to the counter and will determine the leak rate and leak phase of the corrected & received data. --I. (Please read the notes on the back before filling this page) The branch metric generator that generates early yuan includes pre-calculated branch metric, where the branch metric is all suitable for receiving data from the first state to the subsequent state The probability value of the transition is measured, and it also includes a path metric generator, which receives the pre-calculated branch metric from the branch metric generator. According to another aspect of the present invention, the path metric generator and the selector estimate m operation cycles Subsequent transitions, and include a plurality of addition / comparison selection blocks. Each addition / comparison-selection block transmits m symbols of data to the retrace unit in a clock cycle. In order to understand the present invention further For other purposes, the following embodiments will be a detailed description of the present invention. Please refer to the drawings when referring to the drawings, where: FIG. 1 is a block diagram of a part of the receiver of the embodiment of the present invention; FIG. 2 shows FIG. Detailed block diagram of the timing recovery circuit and carrier recovery circuit in the receiver; Printed by the Employee Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economic Affairs. Figure 3 shows the reception of Figure 1. Another detailed block diagram of the timing recovery circuit in Figure; Figure 4 shows the digitally controlled oscillator of the timing recovery circuit in Figure 3; Figure 5 shows the detailed block diagram of the DC removal circuit in the receiver of Figure 1; Figure 6 shows the figure 5 Part of the DC removal circuit part of the icon; this paper scale is applicable to the Chinese National Standard (CNS & A4 specifications (210 X297 mm) printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 312072 at _B7_ V. Invention description ( 6) Figure 7 shows a more detailed electronic circuit diagram of part of the DC removal circuit in Figure 6; Figure 8 shows the electronic circuit diagram of the third-order adder used in the DC removal circuit in Figure 7; Figure 9 shows the reception of Figure 1 A diagram of the carrier recovery circuit in the carrier recovery circuit of the receiver; FIG. 10 shows a diagram of an adaptive loop circuit used in another embodiment of the carrier recovery circuit; FIG. 11 shows an automatic gain control circuit of the receiver of FIG. Block diagram; Figure 10-~~ is the timing diagram of the AGC level and Sigma-Delta modulator output generated by the circuit shown in Figure 11; Figure 13 shows the first-order Vitobi decoding process (〇ne_Step Viterbi Decoding) simple transition trellis diagram; FIG. 14 is a partial illustration of the transition trellis diagram of the Vitobi decoding process performed according to the preferred embodiment of the present invention; FIG. 15 is the Vito of the receiver shown in FIG. 1 The block diagram of the decoder; Figure 16 is the electronic circuit diagram of the partial automatic gain control circuit shown in Figure 11; Figure 17 is the electronic circuit diagram of the control unit in the Vito decoder shown in Figure 15 ; This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) 11 nnn I n I 111 line (please read the note on the back side before filling in this page) A7 B7 printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Description of the invention (7) Figure 18 is an electronic circuit diagram of the control block of the automatic gain control circuit shown in Figure 11; Figures 19, 20 and 21 illustrate the control unit shown in Figure 17 Decoding logic in Figure; Figure 22 illustrates the electronic circuit diagram of the branch metric generation block of the Vitobi decoder in Figure 15; Figure 23 is the electronic circuit diagram of some of the more detailed circuits in Figure 22Figure 24 is a detailed electronic circuit diagram of the calculation unit in the circuit of Figure 23; Figure 25 is an electronic circuit diagram of the logic network used by the circuit shown in Figure 24; Figure 26 is Figure 23 is the electronic circuit diagram of the addition unit of the circuit shown in Figure 23; Figure 27 is the electronic circuit diagram of the addition-comparison-selection unit in the path metric generation block of the Vitobi decoder in Figure 15; Figure 28 is an illustration of path metric calculation; Figure 29 is a partial block diagram of the addition-comparison-selection unit in the path metric generation block of the Vitobi decoder in Figure 15; Figure 30 is Figure 2 The path measurement of the Vitobit decoder in the Seventeenth Middle School generates a portion of the addition-comparison-selection unit's electronic circuit diagram; this paper scale applies the Chinese National Standard (CNS) Α4 specification (210X2.97mm)- ------- 1 ^ .------ ίτ ------ 0 (Please read the notes on the back of VT first and then fill in this page) 312072 Printed by the Central Consumers ’Cooperative Staff A7 --------- B7 V. Description of the invention (8) Figure 31 is the control of the Vitobi decoder in the Fifteenth Middle School Continuous operation flow chart of block making; Figure 22 is a diagram of the electronic circuit of the control block shown in Figure 31; Figure 22 is a traceback of the traceback unit in the Vito decoder shown in Figure 15 The electronic circuit diagram of the line; Figure 24 is an analog block diagram used to explain the operation of the traceback unit in Figure 23; Figure 25 is a diagram illustrating the synchronous search of the Vitobi decoder shown in Figure 15 State diagram of the operation of the unit; Figure 26 is a schematic diagram of the logic electronic circuit of the synchronous search unit described in Figure 35; Figure 27 is a randomizer used in the deinterleaver of the receiver shown in Figure 1 Logical organization chart of access memory; Figure 38 is the electronic circuit diagram of the partial deinterleaver shown in Figure 37; Figure; Figure 29 is the deinterleaver shown in Figure 38 Block diagram of Figure 40 is the block diagram of the central control block of the receiver shown in Figure 1; Figure 41 is the electronic circuit diagram of the control decoding block in the circuit of Figure 40 Figure 4 is the circuit diagram; Figure 12 is depicted in Figure 40 Electronic paper size of the register used in the middle circuit Applicable to the Chinese National Standard (CNS) 八 4 鄕 _ (21〇χ297 Reading

V. Description of the invention (9-way diagram; Figure 43 shows the more detailed electronic circuit of Figure 4 cut towel center_block and Figure 44 the electronic circuit diagram of the money forty-three towel sewing material; Figure 45 is @ Forty-three bit bit error rate calculation unit, the printed road map of the Central Consumers ’Bureau of the Ministry of Electronics, Electricity and Economics, the outline of the printed road map, first refer to the figure-, which shows a block diagram of a part of the receiver 2 according to an embodiment of the present invention. The European telecommunications standard P "ETS300421 states that it can be easily implemented with other standards at the same time. In addition to the Q demodulator 4 and its associated analog-to-digital converter, the receiver 2 series is completely combined according to the CM〇s design. And it can be implemented as a single VLS 丨 chip. So its operation method is much more efficient than the traditional circuit board design method. The well-known telecommunications standard provides internal traditional coding and external Reed-Solomon coding for transmitting data symbols. In order to restore the transmitted data, receive The receiver 2 provides internal decoding and external decoding as disclosed below. The receiver 2 receives quadrature phase shift key data from a channel such as a satellite downlink. According to the well-known European telecommunications standard, the data has been waved and coded in some defined stages, including: synchronization randomization and synchronization byte transposition; Reed-Solomon coding; Forney interleaving method; and satellite transmission status, stack coding In particular, the telecommunications standards provide shallow leaky product codes with a limited length K = 7, and allow code rates of 1/2, 2/3, 3/4, 5/6, and 7/8. Many defined leaky matrices It is recognized by these standards. It should be noted that the good paper standard is applicable to the Chinese National Standard (CNS) Α4 specification (210X297 mm) (please read the notes on the back ST before filling this page) -install

'-IT-line · Printed by Aigong Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs A7 ________B7 V. Description of the invention (1〇) Before modulation, 丨 and Q signal have a factor of 0.35 frequency down (roH-off) Root mean square rising cosine filtering (Cosine-Filtered). After the front-end processing of the convolution, there is the in-phase data stream 6 and the quadrature BER data stream 8. The Q demodulator 4 provides a coded, quadrature demodulated, signal near the fundamental frequency. The feedback timing recovery is completed in the timing recovery circuit 10. The processed in-phase and quadrature-phase data are sent to lines 14 and 16 of the DC removal block, respectively. The symbol timing is restored and the display is presented by the control signal line 18 after T / 2 sampling. The feedback carrier recovery is completed in the carrier recovery circuit 20, wherein the aforementioned carrier recovery circuit receives an error signal from a point in the feedback loop that crosses the carrier recovery circuit 20. According to the control signal 26, the DC bias of the in-phase and quadrature-phase data signals has been removed and transmitted to the carrier recovery circuit 20 on lines 22 and 24, respectively. The timing recovery circuit 10 and the carrier recovery circuit 20 may be those circuits disclosed in the joint assignee of US Patent No. 08 / 480,976 and British Patent No. 9511551.5, which are incorporated herein by reference. Then, the carrier is recovered, and the in-phase and quadrature-phase signals generated according to the control signal 34 are transmitted to the consuming Nyquist chopper 28 on lines 30 and 32, respectively, and the two signals are sent to the block 36 that follows. By feedback Lines 38, 40, 42 and 44 provide feedback to the timing recovery circuit 10 and the carrier recovery circuit 20. The receiver 2 includes an automatic gain control circuit 46, which receives partial signals from the bus 48 and 50 according to the control signal 52, respectively The removed in-phase and quadrature phase data are provided on line 54 to the front end of the receiver (not shown), and the in-phase and quadrature phase data processed on bus 48 and 50 are also provided to the Viterbi Decoder (Viterbi Decoder ) 56 ^ The current leak rate of the received stacked coded data is indicated on the bus 58. The transposition of the received signal constellation indicates a signal on line 60. This paper scale applies the Chinese National Standard (CNS) A4 specification (210X297 Cli) --- --------- 1 ^ ------ 1T ------ ^ (please read the notes on the back 3 before filling out this page) Employees of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the consumer cooperative 312072 A7 _______B7 V. Description of invention (1Ί) When passing l The data processed by the Q demodulator 4 is Forney-interleaved, and the data must be provided to the deinterleaver 62 to receive the data from the line 64. The effective control signal and the end-of-packet signal are online 66 and 68, respectively It is provided to the deinterleaver 62 through the Vitobi decoder 56. The deinterleaved data stream is then sent to the Reed-Solomon decoder 70 on line 72. The effective control signal and packet-end signal are provided to Reed-line on lines 74 and 76, respectively. Solomon decoder 70. The number of bit error corrections in the current byte is indicated on the bus 78. Λ Using the control signals on lines 84, 86 and 88, the decoded data is sent to the derandomizer and output interface on line 82 80. These control signals indicate whether the effective decoding is completed, the state of the packet end, and whether there are errors in the data. The signal on line 92 indicates when the sync byte is output. Lines 94 and 96 indicate the error condition and valid data, respectively. The control block 98 manages the continuous operation of other stages of the receiver 2. The timing recovery circuit 10 and the carrier recovery circuit 20 are shown in detail in FIG. 1. The configuration of these circuits allows the receiver 2 to operate in many different ways. Work under the rate or various symbol rate technologies. Traditional " off-chip " (0ff_Chip) |, Q baseband demodulator, such as GEC Plessey SL1710 l, Q demodulator is commonly used as |, q demodulator 4 'timer The logic operation of the system has a fixed frequency system clock 87. The clock must be at least equal to the Nyquist of the data, or ensure that it can meet the Nyquist frequency of the data. Under the control of the timing recovery loop 100, the "On-Chip" (On-Chip) interpolation unit 89 generates synchronous down / 2 separated by the sampling value. Each time the system clock changes, the interpolation unit 89 generates a τ / 2 sample of 1 or 0. In the case that the sample has been generated, the next hardware module is notified by determining a " valid " control strobe 128 (Figure 3). This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X2.97mm) -------_-- 1 ^ ------, order ------ ^ (please read first Note on the back ΪΓFill in this page) A7 _______ B7 printed by Beigong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs V. Invention description (12) Fixed frequency external crystal oscillator 1 〇2 is common with a digital removal rotator 104 on a chip In operation, the oscillator operates T / 2 before the Nyqujst filter 28 and the on-chip carrier recovery circuit 106. The Nyquist filter 28 is preferably a finite impulse response (FIR) filter. The carrier recovery loop 106 works with D / 2 interval samples.丨 and Q outputs 108, 110 are removed by half in the removal block 36 (Figure 1), and then applied to the error detection and correction circuits, which are shown in the lower half of Figure 1. Timing recovery Figures 3 and 4 further show the timing recovery circuit 10 (Figure 1). The quadrature demodulation data is sampled at the system clock frequency. The clock rate must be at least equal to the Nyquiest frequency of the input data as described above. Figure 4 shows most clearly that the on-chip number control vibrator 112 continues to count the number of symbols. Number control The state W of the vibrator 112 represents the fixed point count of the symbol period that has elapsed. As each system clock changes, the state value in the register 114 increases. The increment is equal to (rated baud rate / system clock rate), and the control signal 116 is used to adjust the rated value. The reciprocal value in the temporary memory 114 is obtained in the reciprocal generator 118. In the multiplier 120, the reciprocal value is multiplied by [(2W) mod 1] / 2 'and a value is defined. This value is less than 1 in the saturation region 122. A dissipative wave removal rotator 129 includes coupling filters 124,126. The coupling filters 124 and 126 are preferably implemented as finite impulse response filters and are enabled by the effective signal generated in the carrier recovery circuit 20 (Figure 1).

Sine interpolator unit 130 receives signals 137 and 139. The interpolator element includes individual sine interpolators 118, 115 for each in-phase and orthogonal phase component. Then, the interpolator unit 130 generates a value based on the interpolation distance. The value of △ is greater than or equal to 0 and less than 1, but it is a fixed number of points. The paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) -------;-1 ^- ----, order ------ ^ (please read the note on the back Ϋ-fr before filling in this page) 312Q72 A7 _ B7 printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Description of the invention (13) . Values greater than or equal to 1 are less than 1 after saturation. It is instructed that a sine interpolator unit 130 generates leading or trailing samples according to whether the value of △ is 1 or 0, respectively. The distribution of sampling time covered by the interpolator is a system clock cycle. Based on the conventional Gardner algorithm, the value-controlled oscillator 112 operates in a time loop. Other timing recovery algorithms such as Mil Her and Mmier algorithms can also be used. Part 132 includes a second-order loop filter, which is implemented as a proportional positive integral controller 134. The proportional and integral gain constants selected by this controller can give the required resistance factor and loop bandwidth. In order to minimize the lock time and ensure identification, it is best to use a relatively wide band for the initial channel identification. After that, the coefficients are changed to reduce the loop bandwidth 'and are therefore less sensitive to noise and chatter. This "gear shifting" operation improves the bit error rate of the entire system. Because the Gardner algorithm assumes that the data does not contain internal symbol interference (Intersymbollnterference), it is better to include dissipation filters 124, 126 that are lighter than the cosine of the root mean square rise. Since the design of the hard and complex circuit is based on T / 2 sample data, the coupling frequency cannot be placed before the interpolator unit 130. As mentioned above, the Gardner algorithm uses τ / 2 sampling to lock the timing sampling points. Preferably, the loop can obtain the sampling point, so that the odd samples are located at the zero crossing of the input data, and the even samples are used as data samples. Adding a delay value between the signal represented by the sine interpolator unit 130 and the appearance of the interpolated samples is calculated according to the following equation: delay = D + k < 5, ^ —binding line / ^ (please read the back Pay attention to things and fill out this page)

A7 B7 printed by the Employee Consumer Cooperative of the Central Ministry of Economic Affairs of the Ministry of Economy V. Description of the invention (14) where <5 is (system clock cycle / N); N is the number of sine interpolation points; k is the (integer) interpolation distance , An; and D are fixed delays hidden in the hardware. The operation of the sine interpolator unit 130 is based on a finite pulse response filter. This filter is clocked under the system clock, and its coefficients are selected from N groups, where each group of coefficients is interpolated with a different delay value. . When the delta value changes from 0 to 1, the interpolation distance from the digitally controlled oscillator output determines which coefficient bank to use to generate a given sample. Sinc interpolation is based on the sampling theory operation, which shows that the signal sampled by Nyquist can be reconstructed by sine pulses. This is equal to the low-pass filter operation in the frequency domain, and the output value is determined by the following formula y (〇 = Σ x (kT) smc [^ Y11] k = ~ 〇〇 'As mentioned above, the timing recovery circuit 10 (Figure 1) indicates that the timing recovery circuit receives an error signal from the feedback loop across the timing recovery circuit. DC removal is shown in Figure 5. Further illustrating the DC removal block 12 (Figure 1), this block contains three modules 113, 117, and 122. The module 122 is mainly used to test circuits and will not be discussed further. However, module 113 will be discussed, and Modules 113 and 117 are the same and applied to 丨 and Q data streams respectively. Figure 6 shows the detailed module 113. The input data arrives at the 7-bit bus 124 and is recorded in the flip-flop 123. The bus 125 is at 128 Provided to the addition unit. The sub-module 127 monitors the feedback data stream that arrives at the bus 133, and calculates that the paper size is applicable to the Chinese National Standard (CNS) A4 specification (2 mm 297 mm) ------ --- 1 medicine ------, order ------ line C, please read it first Surface deposit of precautions ί Complete this page) Ministry of Economic Affairs Bureau of the Central prospective employees consumer cooperatives like India with S12Q72 A7 B7 V. DC invention is described in (left foot 5) data streams shift, and placed on bus 136. Then, the addition unit 128 subtracts the DC offset from the input data. The addition unit eg is a conventional arrangement and operates at 60MHz. The output of the addition unit 128 is output to the 7-bit bus 138. Figure 7 shows the structure of the sub-module 127. The structure mainly includes a 24-bit addition unit 140, which has a carry storage structure. Its input signal on the bus 133 is the final output from the module 113 (Figure 5). When the full addition cannot be evaluated in the earlier data cycle, a carry storage structure is required for timing considerations. Each carry output is recorded in flip-flop 142 before being sent to the next adder. In order to complete the addition, all 24 carry must be resolved, which allows the carry to be passed. In the circuit, the general reference is 144, and the carry transfer is completed in three columns of the same circuit 146 and the adder 155. In the preferred embodiment, only an offset value of up to seven significant bits is required. For the lower sixteen bits, you only need to estimate the carry. This is implemented in circuits 144, 146 with each row of four adders. The selection of multipliers 148, 150, and 152 is based on whether their associated circuit 146 passes a carry from the previous stage, whether a carry will be generated, or whether a zero carry output will be generated. When the addition unit operates at 60 MHz, it is recorded in the last addition unit 154 due to time constraints. Within the addition unit 154 is a three-level addition block 156, the structure of which is shown in FIG. This is a fast adder in which the carry state can be quickly selected in the combinational logic circuit 158, allowing the substitution ripple to pass through the three addition classes 160,162,164. Carrier recovery The following describes the carrier recovery loop. Please also refer to Figures 9 and 10, the solution of Costas algorithm phase error estimation area 166, the second-order loop filter. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm):-丨 ^- ---- 、 玎 ------ 0 (please read the note on the back first and then fill in this page) Printed 3120 (2 A7 -------- B7_____, Beigong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs V. Description of the invention (16) 168. Digital value controlled oscillator 170 and digital removal rotation circuit 172. This circuit tracks the frequency error and phase shift in the external modulation and demodulation chain. Based on least squares (LMS) calculation Method to operate an additional adaptive loop circuit 174 'to adaptively estimate the demodulation phase noise error caused by β hum and jitter. The adaptive loop circuit 174 is not included in the optimal In the embodiment, sin Θ and cos Θ control the removal rotation circuit 172. The two values are generated by the checklist stored in the ROM (not shown in the figure). The triangle checklist is generally used. The removal rotator rotates the input signal 0 angle. Given (l, Q) represents the vector size (丨 2+ Q2), and Degree tan-1 (丨 / Q) = Φ. Therefore 丨 = βίηφ and 0 = ί: 〇3φ. We need to remove the rotation | = Γ and remove the rotation Q = Q ', as follows: l' = sin (Φ + Θ) and Q '= cos (Φ + 0) Ι ^ βίηφοοβθ —οοεφβΙηβ = lcos0 —QsinQ; and Q ′ = Qcos0 + Isin0 I · and Q' can be used to remove the multiplier and adder network in the rotation circuit 172 Implemented in the circuit. The phase error estimation area 166 is sealed to complete this loop. The rotator 172 that operates in conjunction with the phase estimation area 166 is also used to correct phase noise and jitter. This jitter is affected by the phase error LMS. The paper size of this paper is suitable for the Chinese National Standard (CNS) A4 (210x297mm) (Please read the notes on the back ντ before filling in this book). · -S Printed by the Beigong Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs B7 V. Description of the invention (17) Tracking. Please refer to Figure 10, remove the rotation | and Q values, which are expressed as fixed points with fractional parts and are limited by the limiters 176 and 178 respectively to the nearest applicable conformation values For QPSK, this constellation value is +1 or -1. It can be subtracted by 180, 1 82 is obtained by removing the difference between the rotation value and the limiting value, and forming an error. The Q and Q error values are converted into angle errors to estimate the θ error. In the QPSK modulation system, according to the following table 1, from The Θ error is obtained from the switch network covered by the angle meter 184. The output value of the angle meter 184 indicates the appropriate LMS estimation of the phase jitter or the estimated value of the hum error θ. The phase error estimation circuit can use the circuits disclosed in the joint assignee of US Patent No. 08 / 481,107 and British Patent No. 9511568.9, which are incorporated herein by reference, and other phase error estimation circuits can also be applied , Such as the circuit configured with Costas algorithm. The LMS algorithm and its sign variables are generally well-known, so they are not discussed in depth in this article. You can refer to Chapter 11 in the D / g / ia / Com / m / mcai / o /? — Book (Second Edition) published by Kluwer Academic Publishers, Massachusetts. The authors of this book are Edward A. Lee and David G. . The adaptability algorithm has been slightly modified from the standard LMS algorithm, where the estimated value of Θ is not listed. Normally, this missing column indicates a zero value, but it is-(sign (0 estimated value)) every Nth cycle. This avoids an error of 0. The value exceeds the operating limit.

The Costa circuit locks the axial constellation points, such as (1, 〇), (0, 1), (-1, 0), (0, -1). Therefore, in a given example, the error can be estimated by using 0e / ror = sirr1 (/ em) r ·). The above formula can be approximated as the paper size, which is applicable to the China National Standard (CNS) Α4 specification (210X297 mm ) ^ ^ —I install I order I line- (please read the notes on the back before filling in this page) 3 V. Description of the invention (18 Θρ / ΤΏΓ = / erroi

erTOr = ierror. Similarly, for other conformation points "or QenOr, as shown in Table 1 below. For + or an error

Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. As shown in the example of the timing recovery control tour described above, the proportional and integral gains of the proportional integral controller 186 in the second-order loop 168 are applied to the broadband value. In order to make the acquisition time to a minimum, and the white low-frequency loop sets the value offset 'g | once locked, the M bit: error rate can be optimized. The value can be quickly selected according to the needs of special applications. During channel acquisition, the bandwidth is preferably repeatedly added to a constant value for scanning on line 151 to integrate the gain constant in adder 153. Hold the frequency during the scan. Automatic Gain Control Referring to Figures 1 and 14 ', the automatic gain control (AGC) circuit 46 includes an AGC error block 183, which determines the error between the Q input signal on the buses 48, 50 and the desired average value. An error signal is generated on the bus 190 and sent to the AGC control block 192. The AGC control block 192 calculates the control voltage output on the bus 194. The control voltage depends on the error signal on the bus 190 and is averaged in time. Applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) (Please read the notes on the back VO before filling in this page) • Installed.-Ordered • m — ^ 1 ϋ 312072 A7 B7 Central Bureau of Standards, Ministry of Economic Affairs Printed by Beigong Consumer Cooperative V. Description of invention (19

After processing by the Sigma-Delta Modulator 196, the control voltage is sent to the output line 198 at the front end (not shown) of the receiver. Error box 183 calculates the error value, eA7Or =-| / 丨-丨 Q | + 2 * y ^ ean ’(where * refers to multiplication), which is illustrated in detail in Figures 16 and 16. The inputs on the bus bars 48 and 50 are recorded in the flip-flops 200 and 202, respectively, and the complements are taken. If necessary, the mutex or gates 204, 206 are used as part of the absolute value function. The column of the adder 208 adds the absolute value of the input and the absolute value of the Q input. In the case where a complement occurs, adder 210 is used, and two adders 212, 214 add 1 to at least two significant bits of the sum. The aforementioned adder can be found in the second column of adder 216. The addition of 1 completes the absolute value function. Therefore, at binary 01000000, the expected value of the signal is added to the modified output of the column of the adder 208, and the result is output on the bus 190. Figure 18 shows the structure of the AGC control block 192. At label 218, the error signal on bus 190 is added to the bus control voltage using a 22-bit adder. The addition in the first level 220 uses the smallest 8 significant bits and the second level 222 uses the highest 14 significant bits. To improve performance, the individual adder 224 is a fast adder that uses carry pass. The logic circuit 226 determines the overflow and non-overflow conditions. Then, the final control voltage is output on the bus 194 and fed back to the 22-bit adder 218 as a new control voltage. In the preferred embodiment, the feedback function of the control voltage (cv) can be expressed by the following formula: 〇νΜ = 〇νί + ψ Applicable to the Chinese National Standard (CNS) Α4lin (210X297mm: Ί 装-(please Read the notes on the back 3 first and then fill out this page) .1T Line Ministry of Economic Affairs Central Standards Bureau Negative Consumers Cooperative Printed A7 B7 V. Description of Invention (2〇) Refer to Figure 11 again, Sigma-Delta Modulator 196 is It is known and in the preferred embodiment to perform refjme at 7-5 MHz. The development of the AGC level signal 234 is to use the reverse most significant bit of the control voltage on the bus 194 (indicated by line 230) and the lower of the control voltage 7 bits (denoted by 232). Figure 12 is the timing diagram of the AGC level signal 234 and the output of the Sigma-Delta Modulator 196 (Figure 11) on the output line 198, which are indicated by a solid line 163 and a series of Pulse 165. Vitobi decoder The following discussion will refer to FIG. 13, which is based on the first-order Vitobi decoding process at an encoding rate of 1/2, with the use of a limited length κ = 3 and the generator polynomial G (X) = (x2 + x + i, χ2 + 1) stacked encoder (not shown) Variable lattice diagram 167. The 1/2 rate indicates that for each bit input, the encoder generates two bits. The limit length K is the maximum number used to generate the output signal. Use the transition lattice diagram shown in Figure 167 and enter The data sequence may produce an output stream that follows the sequence state S. In Figure 167, the special state 3 can be represented as two bits. For example, suppose the state labeled 169 & 2 is 2 (binary is 10), In the representation of FIG. 167, the bits of state St in state St + 1 are shifted by one position, and the entered data bit occupies the rightmost position (least significant bit). Therefore, state value 169 can be reasonably in state St The transition from +1 to values 171 and 173. For these two transitions, the stacked code will produce the values 175 and 177 indicated as xtyt, respectively. All possible state transitions can be calculated by the encoder, that is, given to St and the data bit dt , Then the next state St + 1, xt and yt can be estimated. The road metric is a measure of the likelihood that the state is on the original coding state sequence. The smaller the path metric, the more likely this state is Vice-based paper New Zealand applies to Zhongguan Family Standard (CNS) M specifications ( 2 丨 Gx297 Gongdong) ------- one-- 丨 install ------ order ------ line I (please read the notes on the back first \ then fill in this page) 312072 Ministry of Economic Affairs A7 printed by Beigong Consumer Cooperative of Central Bureau of Standards V. Description of invention (21)

The Versa λ support measure is the probability of connecting each branch that depends on the input. The knife measure is the Han power (Hamm 丨 Wejght), which is shifted along each shift shown in Figure 13. Each branch receives a different number of bits between the symbol xyrx and the desired symbol xy. Backtracking is a trellis! ^ Back method that produces the initial state of the minimum path metric state. In the preferred embodiment, a two-step encoding procedure is used, which conforms to the two steps of moving through the grid. This doubles the calculation time for each step, and each backtracking produces two bits instead of one. However, when there are four possible paths to be calculated for each state, the number of calculations required for each state will also be doubled. There is only one path in memory to maintain for each state. As is known, Surviving Path (Surviving Path) is a path with the smallest metric, so it is the most likely path. The leakage method (Puncturmg) is approved in the well-known European telecommunications standard. This method should be a more efficient encoding and can have the efficiency of high-speed data transmission. In the example in Table 2, the encoder code (unjie) encodes the data to produce the symbols xt and yt. The symbols are separated according to the leakage matrix to X: 10 Υ.Ί1 to generate xt and y't, and then record \ and Y \ is transmitted as I and Q in the modulation of the quadrature phase shift key. When decoding the data, the calculation of the support metrics is ignored. m promote Μ (CNs ^ A4 ^ (210X297 ^) Pack — II order — I —— I. '— line (please read the notes on the back side 5 before filling out this page) 312072 A7 —________ B7 V. Description of the invention (22) Table 2 Data do ---- ^^ ι d2 d3 d4 xy x〇y〇x3y3 x4y4 xy, x〇y〇Yi x2y2 y3 x4y4 IQ x〇y〇yix2 乂 2 乂 3 x4y4 In the above simple example, use Calculate the branch metric using the Hanmin bit: the improvement of whether or not we receive the multi-bit table that does not replace each received, * the relative possibility of the signal shown by the aforementioned heart and ^ class. Therefore, in the 16th order ( 4 bits) in software decoding, 1 is used to represent 15 (binary 1111). In the 16th order decoding, for example, if you receive 7χ, χ = (314), the calculation of the branch metric is shown in the table. When calculating the new secret When measuring, the individual path complex metric is calculated by using the branch metric calculated by these software to get an effective improvement in the execution of decoding. In the best embodiment, software decoding of 8th order (3-bit) is used . The following discuss in detail the use of pulse beating array (Systolic Array) to achieve backtracking. Table 3 Ministry of Economic Affairs Printed and printed by the Central Consumers ’Cooperative of the Provincial Bureau of Examination xy ^ branch calculation result 〇0 ---— 0 | 0-3 | + | 0-14 | 17 〇1 1 | 0-3 | + | 15-14 | 4 10 2 | 15-3 | + | 0-14 | 26 1 1 ---— 3 | 15-3 | + | 15-14 | 13 This paper button is suitable for China National Building Standard (CNS) A4 specification (21〇297 Sauce) A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs

V. Description of the invention (23) In the preferred embodiment, the data uses a limit length K = 7 to make the volumetric code. The limit length corresponds to a grid with 64 states. Figure 14 shows a partial representation of the two-stage transition lattice diagram in this case. Referring now to Figures 1 and 15, the Vitobi decoder 56 has a rotation adjustment block 179, which receives in-phase and quadrature-phase data on lines 48, 50. In the previous stage, the demodulator can lock the signal constellation of any eight carrier rotation phases, and consider that the received signal spectrum may be transposed when the received l, Q symbols are regarded as Q, i symbols. However, this situation is discussed in the rotation adjustment block 179. This rotation phase is placed on the bus bar 181. For all possible branches (in the preferred embodiment, using the limit length K = 7 and two-stage decoding to 256 branches), the branch metric is calculated every operation cycle in the branch metric generation block 186, which is affected by the phase Control with block control block 188. The current leak rate on the bus 185 and the current leak phase on the bus 187 are output from the Vitobi control block 195 and input to the phase and mark control block 188. The state of the leakage and phase adjustment in the block 186 is generated corresponding to the branch metric generation block 186 according to the state of the lines 197, 199, 201, and 203. The phase and mark control block 188 is shown in detail in FIG. The maximum number of phases is placed on the bus 207 by the combinatorial logic circuit 205 processing the leakage rate from the bus 185. The three-bit adder labeled 211 in section 209 performs phase counting, and the 4-bit subtractor labeled 213 follows the adder. The phase count, which calculates the maximum number of phases according to the modulo, is determined and supplied to the phase calculation section 215. In section 209, the current leakage phase is added to the phase count in the same manner. The current phase with the largest number of phases according to the modulo appears on the bus 217. When the data transmission rate of the marked data stream ---------- II ------ 1Τ ------ ^-(please read the note 3 on the back before filling this page) 312072 A7 ____B7 5. When there is a difference between the invention description (24) and the processing rate of the system, it is necessary to enable and disable the Vitobi decoder 56 according to the mark phase. A small logic circuit 221 generates the global enable signal 219. In block 223, the output of the phase calculation section 215 is also used to decode the phase and ratio information on the buses 187 and 217 and are generated on the buses 197, 199, 201, and 203. The signal, which is connected to the branch metric generation block 186 (Figure 15). Plots 19, 20, and 21 show the decoding logic of buses 197 and 199, where the individual bit positions are marked on lines 225, 227, 228, 229, 231, 233, and 236, respectively. The signals on bus 201 and 203 (Figure 15) complement the signals on bus 197 and 199, respectively. As described below, during the branch generation, bus 199 selects 1, Q input selection, and bus 203 indicates where a leak occurs, so that the data of the leak location is not provided to the path metric calculation. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. Figure 22 shows the branch measurement generation block 186 in detail (Figure 15). Lines 238 and 240 receive l and Q data pairs, respectively, and are processed in four combined logic units 242 according to selection lines 225, 227, 228, and 229. These selection lines are the complements of line 197 (labeled as lines 244, 246, 248, and 250). The previous l and Q data are online 252 and 254. From this data, in order to generate all 16 possible branch metrics on line 266, two symbol pairs XY are formed on line 258,260,262,264 and supplied to block 256. Obtain the previous Q data from the two delay flip-flops 268,270. Block 256 is illustrated in detail in Figure 23 and contains 16 identical computing units 272, each corresponding to one of the 16 branches. Figure 24 has the calculation unit 272 represented further. Each computing unit 272 includes four modules 274. The expected data in these modules is fixed wiring. The paper size is applicable to China National Standards (CNS) A4 specifications (2i〇x297 mm). Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs System A7 B7 5. Description of the invention (25) (hard-wired). The module 274 will add up the absolute difference between the input value and the expected value of the specific branch by the method shown in Table 3; and force the data of the relative mark position to be 0 to match the status of lines 201 and 203. As shown in Figure 25, the module 274 includes a simple logic circuit that can determine the absolute difference value by transposing the swap bits. Therefore, the four difference values obtained on the lines 278, 280, 282, and 283 will be summed in the summing unit 284 as the output of the branch metric on the line 266. The summing unit 284 will be described in detail in Figure 26. Turning now to the discussion of Figures 15 and 27, the path metric is calculated in the path metric generation block 189 and the pre-calculated branch metric obtained from the branch metric generation block 183 on line 288 is applied. This pre-calculated branch metric can greatly simplify the calculation of the path metric. The path metric generation block 189 can process two symbols in one clock cycle. With near hardware design choices, branch metric generation block 186 and path metric generation block 189 can selectively process m symbols using an m-order Vitobi decoder in a single clock cycle. The organization of the road metric generation block 189 is initially displayed by way of the example of Figure 28, and the calculation of the state 0 path metric is shown in the figure. Illustrated in Figure 14 is the complete expansion of the trellis diagram, showing that at St + 1 state 0 can reasonably accept transitions from states 0, 16, 32 and 48 corresponding to 290, 292, 294 and 296, respectively. These transitions can refer to the two most significant bits in Table 4 respectively represented by paths 0-3 and corresponding to their status numbers. Table 4 reveals the branch metrics for each reasonable transition in the transition lattice diagram of Figure 14. It can also be seen from Table 4 that in the state 〇: path 0 has 0 expected branch data; path 1 expected data is 14; path 2 expected data is 3 and path 3 expected data is 13 ° using the above accepted data, for each Branch data is expected to calculate branch metrics. To calculate the four possible candidates for the next path metric for state 〇, the previous path metric for state 0, use adder 298. The paper size given on line 300 applies to the Chinese National Standard (Cns) A4 (210X297 mm)- -----:-1 ^-(please read the note 3 on the back first and then fill in this page) Order A7 printed by Beigong Consumer Cooperative of Central Bureau of Standards of the Ministry of Economy V. Invention description (26) Hou Bu 0, and add the expected data to the branch metric. Then, after comparing the four candidate values on block 302, the next path metric for state 0 will be the smallest candidate value and output on line 304. When other candidates are not the best path, they will be abandoned. Two data bits pass through the backtracking to indicate that the selected path has the smallest path metric, that is, path 0, 1, 2, or 3 is required to be backtracked in time. Table 4 ------------ installed ------, 玎 ------ ii / (please read the notes 3 on the back before filling this page)

State 0: path 0 = 0 1 = 14 2 = 3 3 = 13 State 32: path 0 = 8 1 = 6 2 = 11 3 = 5 State 1: path 0 = 12 1 = 2 2 = 15 3 = 1 State 33 : path 0 = 4 1 = 10 2 = 7 3 = 9 State 2: path 0 = 7 1 = 9 2 = 4 3 = 10 State 34: path 0 = 15 1 = 1 2 = 12 3 = 2 State 3: path 0 = 11 1 = 5 2 = 8 3 = 6 State 35: path 0 = 3 1 = 13 2 = 0 3 = 14 State 4: path 0 = 13 1 = 3 2 = 14 3 = 0 State 36: path 0 = 5 1 = 11 2 = 6 3 = 8 State 5: path 0 = 1 1 = 15 2 = 2 3 = 12 State 37: path 0 = 9 1 = 7 2 = 10 3 = 4 State 6: path 0 = 10 1 = 4 2 = 9 3 = 7 State 38: path 0 = 2 1 = 12 2 = 1 3 = 15 State 7: path 0 = 6 1 = 8 2 = 5 3 = 11 State 39: path 0 = 14 1 = 0 2 = 13 3 = 3 State 8: path 0 = 15 1 = 1 2 = 12 3 = 2 State 40: path 0 = 7 1 = 9 2 = 4 3 = 10 State 9: path 0 = 3 1 = 13 2 = 0 3 = 14 State 41: path 0 = 11 1 = 5 2 = 8 3 = 6 state10: path 0 = 8 1 = 6 2 = 11 3 = 5 State 42: path 0 = 0 1 = 14 2 = 15 3 = 13 State11: path 0 = 4 1 = 10 2 = 7 3 = 9 State 43: path 0 = 12 1 = 2 2 = 15 3 = 1 State12: path 0 = 2 1 = 12 2 = 1 3 = 15 State 44: path 0 = 10 2 = 4 2 = 9 3 = 7 State13: path 0 = 14 1 = 0 2 = 13 3 = 3 State 45: path 0 = 6 1 = 8 2 = 5 3 = 11 State14: path 0 = 5 1 = 11 2 = 6 3 = 8 State 46: path 0 = 13 1 = 3 2 = 14 3 = 0 State15: path 0 = 9 1 = 7 2 = 10 3 = 4 State 47: p ath 0 = 1 1 = 15 2 = 2 3 = 12 State16: path 0 = 3 1 = 13 2 = 0 3 = 14 State 48: path 0 = 11 1 = 5 2 = 8 3 = 6 State17: path 0 = 15 1 = 1 2 = 12 3 = 2 State 49: path 0 = 7 1 = 9 2 = 4 3 = 10 State18: path 0 = 4 1 = 10 2 = 7 3 = 9 State 50: path 0 = 12 1 = 2 2 = 15 3 = 1 State19: path 0 = 8 1 = 6 2 = 11 3 = 5 State 51: path 0 = 0 1 = 14 2 = 3 = 3 = 13 State20: path 0 = 14 1 = 0 2 = 13 3 = 3 State 52: path 0 = 6 1 = 8 2 = 5 3 = 11 State21: path 0 = 2 1 = 12 2 = 1 3 = 15 State 53: path 0 = 10 1 = 4 2 = 9 3 = 7 State22: path 0 = 9 1 = 7 2 = 10 3 = 4 State 54: path 0 = 1 1 = 15 2 = 2 3 = 12 State23: path 0 = 5 1 = 11 2 = 6 3 = 8 State 55: path 0 = 13 1 = 3 2 = 14 3 = 0 State24: path 0 = 12 1 = 2 2 = 15 3 = 1 State 56: path 0 = 4 1 = 10 2 = 7 3 = 9 State25: path 0 = 0 1 = 14 2 = 3 3 = 13 State 57: path 0 = 8 1 = 6 2 = 11 3 = 5 State26: path 0 = 11 1 = 5 2 = 8 3 = 6 State 58: path 0 = 3 1 = 13 2 = 0 3 = 14 State27: path 0 = 7 1 = 9 2 = 4 3 = 10 State 59: path 0 = 15 1 = 1 2 = 12 3 = 2 State28: path 0 = 1 1 = 15 2 = 2 3 = 12 State 60: path 0 = 9 1 = 7 2 = 10 3 = 4 State29: path 0 = 13 1 = 3 2 = 14 3 = 0 State 61: path 0 = 5 1 = 11 2 = 6 3 = 8 paper The scale is applicable to China National Standard (CNS) A4 specification (210X 297mm) Department of the Central Bureau of quasi-ladder HIGHLAND consumer cooperatives printed 312C72 at - B7 V. invention is described in (27)

State30: path 0 = 6 1 = 8 2 = 5 3 = 11 State 62: path 0 = 14 1 = 0 2 = 13 3 = 3 State31: path 0 = 1〇1 = 4 2 = 9 3 = 7 State 63: path 0 = 2 1 = 12 2 = 1 3 = 15 The path metric generation block 189 contains 64 addition-compare-select blocks 306 (add-compare-select block), one of which fully displays the part of FIG. 29 , Each bonus_comparison_select block 306 generates a path metric. In the actual layout, a more convenient method is to arrange 64 bonuses in two groups of 32-comparison · selection box 3〇6 ^ such a tighter design can reduce the length of the "jumper" and the path metric Driving demand has also decreased. The path metric generation block 189 determines the smallest path metric among 64. Each addition compare-select block 306 accepts the four path metrics of the previous state at the 6-bit bus 308, 310, 312 314, corresponding to the transition shown in FIG. The corresponding branch metrics are accepted at the 5-bit bus 316, 318, 320, and 322. Figure 27 describes the arrangement of the addition-comparison-selection block 306 in more detail, where the decision is input to the smallest path metric among the four candidate road service metrics. The adder 324 obtains the candidate path metric by adding the path metric and the branch metric input to the bus bars 326 and 328, respectively. Then, in the comparison module 330, the minimum path metric is determined. The comparison module 33 shows further details in Figure 20, in which four values are compared to find the smallest value. In the six units 332 on the left in Figure 30, all possible comparison values are completed and output on lines 334 and 336. The output on line 336 is a simple transpose of the output on line 334 for each individual unit 332. Then, the result is decoded in the logic circuit 338 and placed on the 4-bit selection bus 34. The advantages of this arrangement method of the present invention will be described below as the addition, comparison and rescale operation can be pipelined to save time. Referring again to Figures 15 and 27, the two bits of data can be operated for each data cycle on each addition-comparison-selection block 306 to this paper size New Zealand National Standard (CNS) (- ： \ ~ ^ IT ------ 0 (please read the note 3 on the back before filling in this page) A7 __B7 printed by the Consumer Labor Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (28) Lines 342 and 344 The upper traceback unit 191. The selection of the minimum path metric is done using the multiplier of reference 346. To reduce the hardware requirements and allow the path metric to be represented by 6 bits, the readjustment unit 348 readjusts the minimum path in the adder 350 The value of the metric. The value of the minimum path metric is adjusted according to the following formula; where X is the minimum path metric, RV is the readjustment value and Z · 1 and Z · 2 are 1 and 2 of the addition-comparison · selection block 306, respectively The period of operation is delayed by x. The application of this delay is because it takes two cycles to calculate the minimum path metric. The use of the readjustment function ensures that the readjustment value CV is not negative. The readjustment path metric is output in the bus 352. One and fifteen, the Vito must understand The device 56 has a control block 195, which has several functions. In the first operating mode, the reasonable state transition path with the smallest path metric will be counted to measure whether the estimated leakage rate, leakage phase, and carrier phase have been correctly Decision. A new combination of leakage rate, leakage phase, and carrier phase can be selected based on the count of reasonable state transitions. If the unreasonable state count is within a specific tolerance, the second mode of operation will be initiated, where the output data stream is enabled And the synchronization pattern is searched. However, the end state (end_state) of the first operation mode is retained. Therefore, if the synchronization state cannot be achieved, the first operation mode will be restarted at the end state. Understand the above actions. In step 354, both the initial reasonable state counter and the wait counter are reset. In decision step 356, the execution is immediately confirmed to determine the allowable number of transitions beyond the reasonable state. Then in step 370, perform Tests where a reasonable state transition occurs. If an unreasonable state transition does not occur, control is immediately Skip to decision step This paper standard is applicable to Chinese national standards (CNS & A4 specifications (210X297 Gongdong ')-I ~ install I line (please read the notes on the back VT before filling in this page) A7 B7 Central Ministry of Economic Affairs Printed by the Bureau of Standards and Staff Consumer Cooperative

5. Description of the invention (29) 360. If an unreasonable state transition occurs, the unreasonable state transition counter is incremented at step 372. Otherwise, control will jump to step 358. The cumulative number test for another logical state transition will be performed in step 374. If the number of inconsistent state transitions is still within tolerance, control will jump to step 358. Step 366 will be performed as described below. Wait for the counter to increase in step 358. Then, at step 36, to determine whether the 256 cycles have been estimated according to the state of the wait counter and the unreasonable secret changes are kept within the tolerance range, the synchronization search step 362 is executed. Then the control proceeds to the decision step 364, in which the action of the synchronization is tested. Until the synchronization action fails, control will be maintained at step 362. When the synchronization action fails, control returns to the first operation mode at step 366. If the number of unreasonable state transitions in step 356 is not within the tolerance range, control will also move to step 366 ^ step bare 366 is a decision step 'its t pair' & all possibilities of leaky phase and carrier phase , Combination will be tested. If all these tests are not completed, the carrier phase will change at step 368 and control will return to step bare 354. If the detailed test of the decision step fails, the further test is performed at the decision step 376 to determine whether all_levels are difficult to calculate. If all tests have not been performed completely, the leak rate and leak phase will change at step 378. If all leak rates and phases have been estimated, the tolerance is incremented at step 38 and control will return to step 354 again. The understanding of the flow chart in the thirty-one circle can be described by Figure 32. = The counter is incremented in the incrementer 382 and the value is placed in the M row 384. The counter is tested in combinational logic 386. Tolerable unreasonable changes and

.; ^^, order ------ ^ 1 f (please read the notes on the back ντ before filling out this page)} Α4Μ (2Τ ^ ~

Printed by the Central Sample Bureau of the Ministry of Economic Affairs of the Employees Consumer Cooperative, the invention description (30) sends a signal in the bus 388, and the unreasonable state count is tested in the bus 390 of the comparator unit 392. Then a pulse is generated on line 394 and output on line 396 and fed back to the controller unit 400 through the delay circuit 398. The controller unit 400 then outputs the new carrier phase, leakage rate, leakage phase, and new tolerable limit according to the procedure discussed in FIG. 31 on the line labeled 402. The unreasonable state sends a signal on line 404 and takes the previous state as an input to be decoded by the logic circuit 406. The transitions on line 404 are counted in incrementer 408 and the new count value is placed on bus 41. A second mode of operation for searching sync bytes on the data stream is initiated on line 412. The line is the output of the combinational logic circuit 414 managed by a plurality of control signals. The aforementioned control signals are the state of the tolerable test line 396, the state of the waiting counter on line 416, and the second mode of operation of the designated decoder in line 418. 'S state. The clock trace back array element (systolic traceback array umt) 191 (Figure 15) operates in a preferred embodiment using a 21-cycle history and can be further understood from Figure 33. The traceback array 191 is connected to the addition / comparison-selection block 306 of the path metric generation block 189 (Figure 29), and includes successive traceback lines 420, each traceback line 420 representing the entire servo process continued Save path 'The path is determined at the same time by the addition-comparison_selection block 306 and the path metric generation block 189, each backtracking line 420 has a plurality of backtracking elements 422 and each backtracking element 422 can M bits of data 424 are received. As shown therein, m is equal to 2 in the presently preferred embodiment. The traceback element 424 of the traceback line is addressed by three predecode selection lines 426, 427 and 430 based on the content of at least one previous traceback line (not shown) and decoded by three decoders 432. The output of each traceback line 420 is placed on the pre-charge line 434. The size of this paper is suitable for China National Standard (CNS) A4 (210X297mm) I ------:-1 # ------ 1T ------ ^ (please read the back page first Please pay attention to ΛΝ and then fill out this page) A7 --------------- B7 printed by the Employee Consumer Cooperative of the Central Bureau of Samples of the Ministry of Economy V. Invention description (31) — According to the second-order dimension Bettor decoding theory requires two bits in each backtracking line 420 to become the two most significant bits of the next backtracking line. In each phase of the backtracking, the 6-bit state will address one of the 64 addresses to get the content of the backtracking element and establish the next state in the backtracking. By precharging the two data lines 434 to perform 64-to-1 multiplexing. As described above, selection lines 426, 428, and 430 are connected according to the number of states of the previous traceback element, where line 426 is designated as the decoding state corresponding to the number of states [1: 0], and line 428 is designated as state [3: 2 ] And line 430 is designated as state [5: 4]. At clock ph1 436, the two pre-charge lines 434 are pulled to VDD. At the clock PhO 438, only one of the traceback elements 424 is selected by the selection lines 426, 428, and 430 and the precharge line 434 is pulled down according to the traceback data. The state of the pre-charge line 434 is held in the latches 440, 442 to be used by the two most significant bits of the next retrace line (not shown). Examples have found that the use of the pre-charge line 434 can greatly reduce the area required by the recovery unit 191. When the last traceback element arrives, the I, Q data two bits are completely decoded and output on the pre-charge line 434 for use by the synchronization block 193 (Figure 15). The total number of traces (the size of the window) and the number of levels in the quantized Q data stream have a certain influence on the performance of the Vebitto decoder 56 (Figure 1). Example The method of quantifying these parameters is by simulation. The design of the simulation method is shown in Figure 34. Only the analog methods of the ratios 1/2 and 7/8 are performed because they exhibit two extreme cases of encoding overhead. The curve is named RrHhQq, where r is the bit rate and h is the factorial history of (K-1), where K is the quantitative length and q is the number of quantitative layers used in software decoding. It is like using software to decode the number. The size of this paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm);-;-Meal ------ ίτ ------ 0 (please read the notes on the back 6 before filling in this Page) Sheet ----- 1_J The Central Ministry of Economic Affairs rented the second father Φ 作 社 ί

The Chinese national standard for collapse ^ 297 mm) 3I2G72 A7 B7 5. Description of the invention (32) Gold Uh-style process description For example, the quantitative number Q = 8 is expressed as a 3-bit quantitative number. Explanation history The factorial of (K-1) is equal to 6, where K is the quantitative length. Therefore, the history H = 4 represents a 6 * 4 = 24 1st-order transition window, where * is the multiplication sign. In order to determine the required quantification level, the history H is set to a large window with H = 8. The results of Boshe are available in Table 5 and Table 6 and are marked. The results for% contrast ratio 1/2 show almost zero improvement between the 8 and 16 quantification levels (3 and 4 bits). The result of the contrast ratio of 7/8 has some improvement between the 8 and 16 levels. The quantification of moving from 3-bit to 4-bit results in a maximum branch metric value shift from 28 (5 bits) to 60 (6 bits). Such sequential changes can result in a block 189 (Figure 15) in the path metric, which is a larger bit width in the timing-critical block in the entire decoder. The gain caused by moving 3-bit to 4-bit quantization is not considered, and it may be decided to use 8-level quantization in the preferred embodiment. The quantification is maintained in 8 levels, and the course of backtracking is further simulated and changed. The results from the above are shown in Tables 7, 8, 9 and 10. The result of the contrast ratio 1/2 shows that a history greater than 3 (for example, 3 * (k_1) = 18) has a very small gain. However, for the ratio 7/8 code by increasing the history, there is a stable improvement when the level leaves Oeveling at 7 (for example, 7 * (κ _ ”= 42). Adding the history by adding extra lines is more Simple way, but the price increase required by the Zengcai Office from 7 to 8 (please read the notes 5 on the back and then fill in this page)-Install. Order Α7 Β7 Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Printing 5. Description of invention (33) Table 6 SNR (dB) R78H8Q4 R78H2Q4 R78H2Q16 R78H8Q16 -9 4.99e-2 -9.5 5.21e-2 1_94e-2 -10 2.30e-2 6.26e-2 2.56e-2 6.28e -3 -10.5 9.00e-3 3.31e-2 1.17e-2 2.29e-3 -11 3.62e-3 1.98e-2 5.64e-3 6.53e-4 -11.5 9.58e-4 1.13e-2 2_82e- 3 2.50e-4 -12 2.50e-4 5.88e-3 9.39e-4 1.61e-5 -12.5 8.87e-5 3.27e-3 6_93e-4 -13 8.47e-5 1.33e-3 2.90e-4 -13.5 5.78e-4 1.69e-4 -14 2.64e-4 -14.5 1.53e-4 -15 7.66e-5 Table 7 SNR (dB) R12H8Q8 R12H8Q2 R12H2Q8 R12H2Q2 -4 -4.5 2.37e-2 6.72e-2 -5 8_89e-3 3.62e-2 -5.5 3.01e-3 1_80e-2 -6 6.90e-4 7.41e-3 -6.5 2.49e-4 1 _46e-2 2.73e-3 4.43e- 2 -7 2.68e-5 4.84e-3 9.37e-4 2.18e-2 -7.5 2.05e-3 3.90e-4 1.13e-2 -8 4_25e-4 8.39e-5 4.52e-3 -8.5 5.36e -5 3.65e-6 1_41e-3 -9 3.94e-4 -------: --Ί Install-(please read the notes 6 on the back first and then fill out this page) Order -7 117e-4 6.33 e-4 2.54e-4 5.11e-5 -7.5 1.70e-5 2.148-4 6.05e-5 -8 5.6e-5 The paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) Economy Printed by the Central Bureau of Standards of the Ministry of Employees Consumer Cooperative 312072 A7 B7 V. Description of invention (34) Table 8 SNR (dB) R78H8Q8 R78H8Q2 R78H2Q8 R78H2Q2 -8.5 1.28e-1 1.96e-1 -9 4.83e-2 1.31Θ-1- 9.5 2.92e-2 7.40e-2 -10 1.05e-2 3.94e-2 -10.5 3.90e-3 4.73Θ-2 1.98e-2 -11 1_38e-3 2.35e-2 1.04e-2 7.75Θ-2 -11.5 3.87e-4 1.16e-2 5.08e-3 5.34e-2 -12 4.84e-5 4.65e-3 2.48e-3 3.42e-2 -12.5 1.54e-3 1.29e-3 1.89e-2 -13 5.52e-4 6.73e-4 1.03e-2 -13.5 1.05e-4 3.02e-4 5.69e-3 -14 4.03e-5 3.63e-5 2.50e-3 -15 3.25e-5 2.82e -5 1.41e-3 -15.5 2.98e-4 Table 9 SNR (dB) R12H7Q4 R12H6Q8 R12H5Q8 R12H4Q8 R12H3Q8 4.5 2.37Θ-2 2.5 5e-2 3.06Θ-2 3.86Θ-2 5 8.76e-3 9.21Θ-3 1.00e-2 1.18e-2 1.56e-2 5.5 3.13Θ-3 3.25e-3 3.63e-3 3.43e-3 6.27 e-3 6 6.97e-4 7.51e-4 8.50Θ-4 1.18e-3 1.90e-3 6.5 2.68e-4 2.76e-4 2.80Θ-4 3.49e-4 5.25Θ-4 7 2.68e-5 2.68e-5 2.68e-5 3.06e-5 7.30Θ-6 7.5 7.30e-6 Table X SNR (dB) R78H7Q8 R78H6Q8 R78H5Q8 R78H4Q8 R78H3Q8 ------------ ^ ------ , Order ------ ^ (Please read the precautions on the back before filling in this page) -9.5 1.75e-4 -10 1.02e-4 -10.5 1.182e-5 This paper size is applicable to China National Standards (CNS ) A4 specifications (2 丨 0 侂 2.97mm) A7 __________B7 5. Description of the invention (35) 9 6.88Θ-2 9.5 3.02e-2 3.93e-2 4.04Θ-2 4.64e-2 5.31 θ_2 10 1.10e-2 1.33e-2 1.67e-2 2.31e-2 2.59e-2 10 1.10e-2 1.33e-2 1.67e-2 2.31e-2 2.59e-2 10.5 4.01e-3 5.00e-3 6.71e-3 9.16e-3 1.10e-2 11 1.32e-3 1.71e-3 2.57e-3 3.73e-3 5.07e-3 11.5 5.31e-4 7.99e-4 1.12e-3 1,66e-3 2.19e- 3 12 7.12e-5 1.31e-4 2.96e-4 5.25e-47 7.83e-4 12.5 7.12e-5 1.09e-4 2.13e-4 3_45e-4 5.14e-4 13 4_93e-5 1.15e-4 1.97e-4 13.5 3.28e-5 Synchronization (Please read the notes on the back 3. Please fill in this page. J) The strategy of synchronization-assumes that there is a regularly spaced synchronization byte in the data stream. According to the known European telecommunications standard, the transposed sync bit is transmitted at the position of every eighth sync byte. The synchronized search unit 193 (FIG. 15) also combines the 2_bit outputs received on the line 161 from the tracking unit 191 into bytes. This is achieved by initializing the combination of 9-bits and estimating two 8-bit bytes with each byte offset by one bit position. Therefore, the two combined bytes are estimated and decided to be output based on the two bytes with a predefined synchronization bit pattern. Figure 15 shows the synchronized search unit 193. The synchronization search unit 193 starts searching for effective synchronization bits after receiving the start synchronization signal 159 from the control block 95. The search unit reports the status on the synchronous action line 157 to the control unit. "As previously discussed, the control unit enables the search unit in an unreasonable state within the tolerance range.

The operation status block of the synchronization search unit 193 is described in FIG. 35. The inactive state as shown is represented in the INACTIVE state 452 of the search unit. When receiving the signal IN_START_SYNC from the control unit, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X297mm) ', !! Line-Printed by the Ministry of Economic Affairs, Central Standards Bureau, Negative Consumer Cooperative A7 B7 312G72 V. Invention Explanation (36) 444, the search unit starts to search for the synch byte pattern of 47h or B8h in the SEARCH ANYWHERE state 446. This bit group 47h is in accordance with a positive synchronization pattern and B8h is a transposed synchronization pattern. The Vitobi decoder can operate on the transposed data, the state determined by paying attention to the number of sync bytes, and the number of transposed sync bytes found by the sync search unit 193 (Figure 15). The data received from the tracking unit 191 (Figure 15) is a 2-bit symbol. Because the decoder applies second order processing, the beginning of the byte will be in one of the two bit positions. The search unit starts searching for positive and negative sync byte patterns in the two starting bit positions. The search continues to process the bit length of the data packet with a display such as NOT FOUND AND NOT DONE ALL PACKET status 448. If all the data packets have been searched and the synchronization bit is not found or transposed as shown by NOT FOUND DONE ALL PACKET status 450, the search unit will return to the NACTIVE state 452 and be on the synchronous action line 157 (fifteen) The signal is transmitted to the control unit 195 (Figure 15) to indicate that the search is unsuccessful. When a synchronization pattern is detected, the search unit follows step FOUNDSYNC 456 to enter the LOCKED SEARCH state. In this state, the search unit assumes that a valid positive or transposed synchronization byte is found and attempts to validate the synchronization by searching for the synchronization pattern by successive packet segments in the location where the synchronization is expected to be found. In this state, continuous counting is valid and invalid bytes are found to continue. The search remains in this state until one of the two conditions meets the condition indicated by the loop SEARCHING SYNC + NSYNC &lt; 8, which is labeled 458 in the figure. If three or more sync bytes are incorrect in the search range, the LOCKED SEARCH state 454 ends and the search unit returns to the SEARCH AYNWTLERE state 446 by displaying the path ERROR> 3,460. Redo from the relative position of the previous packet Bit-by-bit search. If 8 sync or transposed sync bytes are found to be valid and do not result in three or more errors, the search unit enters this paper standard and applies the Chinese National Standard (CNS) A4 specification (210X297mm): -(Please read the precautions on the back &amp; fill in this page first) -Subscribe-line · Printed by the Ministry of Economic Affairs, Central Bureau of Economic and Technical Affairs, Beigong Consumer Cooperative Printed by the Ministry of Economic Affairs, Central Bureau of Standardization, Beigong Consumer Cooperative, A7 __B7_ Description (37) SYNCHRONIZED state 462. Valid information is output immediately. The search unit remains in the aforementioned state until the bus change occurs. Referring now to Figures 35 and 36, a logical block diagram of the synchronous search unit is shown. The combinational logic used to decode the sync byte pattern from the input data can be understood by the logic gate 464. These gates decode the positive and transposed sync byte patterns from the two-bit starting position in the known 9-bit combination described above. SEARCH_COUNTER466 is a counter linked with SEARCH ANYWHERE state 46. During the LOCKED SEARCH state 454, using LOOK_COUNTER468, when the search unit is in the LOCKED SEARCH state 454, the counter 470 maintains the count of transposed sync bytes found, the counter 472 counts the positive sync bytes found, and the counter 474 counts errors Of sync bytes. The IN_START_SYNC signal from the control unit 195 (Figure 15) shows line 476. The synchronous action signal to the control unit is displayed in OUT_ACTIVE 478. Deinterleaver Deinterleaver 62 will be discussed based on Figures 1, 37 and 38. The twelve Forney de-interlacing of the transmitted data is specified in the aforementioned European signal standard. According to the interleaving procedure, the first byte flows through the interleaver without delay; the second byte is delayed by 17 cycles; the third byte is delayed by 2 × 17 cycles ... and so on. In the deinterleaver, the first byte is delayed by 11X17 cycles; the second byte is delayed by 10X17 cycles; the third byte is delayed by 9X17 cycles ... and so on. In the preferred embodiment, the 11 separate shift registers used for deinterleaving are used for deinterleaving as a single block of three-cycle synchronous static random access memory (RAM) 480. Point to the base address in the memory 480. The paper size applies to the Chinese National Standard (CNS) A4 (210X2.97mm) (please read the notes on the back ¾. Fill in this page) -installation. Order 3ί2υν2 A7 B7 is generated by the circuit five, the invention description (38 indicator, such as 482 and 484 486 representing the base address. The first 11 X 17 bytes in the record 480 are used to implement 11 X 17 bytes Group shift register 488. The subsequent blocks of memory 480 are configured in 10 × 17 byte shift register 490, etc. Therefore, memory 48 is logically divided into 11 different sections and its capacity is gradually reduced. In Figure 38, the adder 492 outputs a valid address for accessing the memory 480. The first input 494 of the adder 492 is the base address of the current shift register (such as _482). The second input 496 is the output of the byte counter 498, which is represented by the module 17. The third input 500 is 11 &gt; &lt; 4 bit shift register 502 multiplied by 17 to shift out the handsome value 6 (1-〇1 ^ 3 丨 116), which refers to the packet index pointing to the current shift register, and the module length of the current shift register. The organization of the deinterleaver 62 in FIG. 1 can refer to FIG. 39, in which the memory 480 has 1122 bytes. The operation of the memory 480 is controlled by timing, block 504, and the block initiates a memory read and write cycle And it increments the address counter 506. The memory is connected to the write data bus 508 and the read data bus 510. The control signal includes a valid signal on line 512 which is transmitted from the previous stage and on line 514 The valid signal for reading data indicates whether the memory read operation is successful. The central control block 98 (Figure 1) makes a preliminary discussion with reference to Figure 40. The block ^ is a 2 C bus (not shown) The control decoding block is mainly used for writing or reading the register. Block 516 is discussed with reference to Figure 41, which shows the serial data bus and includes according to the control signal -------: 丨丨 丨 ^ ------ tT ------ 0 ί (please read the notes on the back ¾. Then fill out this page) Printed by Beigong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs

Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy and printed in the first shift register 520 for decoding data and the second shift register 522 for decoding addresses. The output of the shift register 522 is placed on a dagger bus 524. The first four bits are used to decode the current block, which considers the use of logic circuit 526. ', Figure 42 describes all the registers used in the central control block 98. The registers 528, 53〇, 534, 536, 538, and 54 are written by the 2C bus to set the central control block 98 (the registers in the columns in Fig. 1 are usually marked as 542, used to monitor the central The internal state of the control block 98 and used to monitor the input signals marked on lines 544, 546, and 548. For the 2c bus, reading the central control block 98 is possible, just as the tendency to use external control elements, For example: a microprocessor to query and control the central control block 98. The central control block 98 maintains a circuit compatible with the digital satellite equipment control DiSEqC (trademark). Further details of the central control block 98 will be described in FIG. 43 Several clock buffers are marked with 550. The input retiming from the other parts of the receiver 2 (Figure 1) will occur in five flip-flops 552. Two multipliers 554, 556 according to the bus The state of the bank lock state device 562 selects the timing recovery circuit 10 and the carrier recovery circuit 20 that are output to the bus bars 558 and 560 (FIG. 1) The reciprocal value on the bus bar 564 is calculated in block 566, which is generated by the reciprocal 118 (figure 4) Consistent and used for timing recovery. The continuous and cumulative packet errors detected in the Reed-Solomon decoder 70 (Figure 1) are counted in block 568. In addition, the counter block 507 is immediately processed by Vitobi decoding 56 The decoder symbol is counted and input is accepted on line 52 (Figure 1). Control signals are generated on lines 572, 574, and 576 to instruct the bus lock stater 562 to transition to its next state. (CNS) Eight 4 secrets (2i〇X297 male thin) (Please read the notes on the back Γ &gt; 'before filling out this page j • Installed--Ordered-Printed by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 312072 A7 ______B7 5. DESCRIPTION OF THE INVENTION (4 ()) The details of block 566 are depicted in Figure 44. A row of fast adders 578 repeatedly retrieves data from the bus 580 and inputs it as a value held in the shift register 582. If this The operation did not cause an overflow, and the result is selected in a plurality of multipliers 584. However, if an overflow occurs, the original value in the shift register 586 is selected. Then, the data is directed to the left Shift register 580 The effective bit position is shifted in the direction, and the aforementioned deletion operation is repeated. Overflow detection after a series of shift-subtract operations in the shift register 582 will be described next. Unless temporary storage The register 588 is at the least significant bit position, otherwise the second shift register 586 will be initialized to 0. The shift register 586 receives the last carrier output from the line of the adder 578 on line 590. The shift register The register 586 includes an additional register 592. The bits that were set in the register 588 following the successive cycles of the shift register 582 are obtained in the register 594. Then, the processing register 591 tests the occurrence of the current overflow bit. If the overflow bit is currently stored in the register 591, the saturation signal is asserted on line 595 and all contents of the shift register 586 are set to 1. After the shift register 582 exceeds one period, the original bit setting in the register 588 is obtained in the register 592. Then, the shift register 582 is disabled according to the control lines 596 and 599. The countdown is output from the shift register 586 to the bus 598. The bus lock stater 562 (Figure 43) is partially controlled by the input of block 570 and the symbol count. Block 562 drives the bus to change the control state signal to different parts of the receiver 2 (Figure 1), and interrupts the signal according to different failures on the interrupt line 600. Block 562 controls the multipliers 554, 556 at the same time. Block 602 provides a bit error rate indicator and incorporates an infinite impulse response filter, as shown in Figure 45. The flip-flop 604 is based on the chip I ^ ~ -I. — ^-(Please read the precautions on the back &quot; 'then fill in this page) order

A7 ------------ B7 5. Description of the invention (41 ^ &quot; 一 &quot; Event control line 608 and line 610 interrupt military shield settings to record the main interrupt line 606 to the receiver. Block 6〇2, which is used to monitor the output from the Reed-Solomen decoder 70 (Figure 1), is further described in detail in Figure 45. The detected bit errors for each byte are counted in the bus Received in 612. A group of subtractors 612 subtracts the fractional part of the error rate (1/213) per 64 symbol bits, which is almost equal to the subtraction of the bit error rate per symbol (1 / 219). This arrangement reduces the demand for the module area, and the number of adders can also be reduced. It is worth mentioning that in each valid symbol, the module estimates the scale bit error rate (BER) according to the following formula : BERi + 1 = BERj + MErrorCount-ridge

The actual bit error rate is equal to 3.8X10-6 XBER. The structure of the present invention is disclosed according to the above description, but the present invention is not limited to the details described in the description of the invention, and the application of the present invention also includes the modifications made within the following patent application gardens And change. (Please read the precautions on the back ¾. Then fill in this s')-Binding · Order Printed by Employee Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs

• —4 I IJ This paper scale is applicable to Guomujia County (CNS) A4— (21GX297 public

Claims (1)

The A8 B8 C8 D8 'Patent Scope 1 printed by the National Bureau of Standards of the Ministry of Economic Affairs and Consumer Cooperatives 1. A decoder for receiving data symbols, the data symbols are coded according to the #product coding method, the data is marked according to the ship matrix, the data It has a plurality of state values and describes a continuous state transition from the first state to the subsequent state, wherein a path is defined by the continuous state transition, the decoder includes: a generating unit that receives the aforementioned received data to calculate the first state The transition metric of the state to the subsequent state, wherein the aforementioned metric conforms to the possibility that the measurement path follows the path generated by the encoder of the data; a selector is generated by the transmitter that responds to the aforementioned generating unit to select the transmitter that conforms to the data stream The path of the path; a backtracking unit used to maintain the history information of the continuous decision operation indicated by the selector; a counter used to count the reasonable state transition of the path selected by the selector; and a control unit Respond to the aforementioned counter to determine the leakage rate and adjust the leakage of the received data Leaky phase. 2. A decoder for receiving data symbols, the data symbols are coded according to the overlapping coding method, the data is marked according to the leakage matrix, the data has a plurality of state values and describes the continuous state from the first state to the subsequent state Transition, wherein a path is defined by the continuous state transition, the decoder includes: a generating unit that receives the received data to calculate the transition metric from the first state to the subsequent state, wherein the metric conforms to the measurement path followed by the Possibility of the path generated by the encoder of the data; a selector that responds to the aforementioned generating unit to select the path generated by the transmitter that conforms to the data stream; the private paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) I— I n I binding I ϋ line (please read the precautions on the back and then fill out this page) A8 B8 C8 D8 / 、 Patent application for the fan garden once-recovery unit, used to maintain the aforementioned selector Represents the process information of the continuous determination operation, in which the aforementioned traceback unit has continuous traceback lines, and each line maintains a part According to the history information, each backtracking line has a plurality of backtracking elements' wherein the backtracking element of the aforementioned backtracking line is addressed by a pre-decoding selection line according to the content of at least one previous backtracking line, wherein the The output is placed on the pre-charge line. 3. An error detection and correction system for the data stream, which is randomized, interleaved and leaked at the leak rate and leak phase, where the data is in the symbol and in the signal The constellation is transmitted at the symbol rate and includes: an m-step internal decoder operating in the first mode and the second mode. The m-step internal decoder includes a branch metric calculation unit to output the selected leak rate and all The branch metric of the selected leakage phase; a plurality of addition-comparison-selection blocks are used to output the value of the path metric derived from the aforementioned branch metric, and compare the aforementioned value with the selected value corresponding to the minimum value; a readjustment unit, Operate on the output of the aforementioned bonus-comparison-select block based on the minimum value to readjust the output; Printed by the Consumer Labor Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (Please read the note on the back before filling in this page) A state transition module, which can be operated in the aforementioned first operation mode to detect the unreasonable value of the path measurement selected by the aforementioned addition-comparison-selection box State transition, the state transition module can output estimates of symbol leakage rate and leakage phase, used to control the aforementioned branch metric calculation unit to change the selected leakage rate and selected leakage phase; CNS) A4 specification (210X297 company director) D8 hole, patent application scope: &quot; &quot; one * ---- a synchronous search unit, (iv) described in the second operation mode enabled and respond to the state transition module to identify Synchronous information in the data stream, the “recovery module” is connected to the aforementioned bonus comparison-selection search with continuous retracement, where each line represents borrowing &amp; threatening_comparison · selector j at the same time All the history data that determines the choice value of road service states that the backtracking line has a plurality of backtracking elements, each of which is m bits of the backtracking data, where the backtracking element is based on at least one The content of the retrace line is addressed by the pre-decoded selection line; a deinterleaver, which is coupled to the m-step internal decoder; an external decoder, which receives the interleaved data of the deinterleaver; and a derandomizer , Is coupled with the aforementioned external decoder. 4. A transmission and receiving system for a positive and phase-shift key data stream, the data stream is randomized at the leak rate and leak phase, interleaved and interleaved, wherein the data is in the symbol and the symbol in the signal constellation Rate transmission, and output error correction data stream, including: Printed by Employee Consumer Cooperative of Central Bureau of Standards of the Ministry of Economic Affairs (please read note f on the back before filling in this page) 1. l, Q demodulator, with the aforementioned transmission symbol Receive the data rate; an analog-to-digital converter to convert the analog output of the aforementioned l, Q demodulator; a sine interpolator to receive samples from the aforementioned analog-to-digital converter at a sampling rate; a timing recovery circuit Contains: This paper standard is suitable for financial standards (CNS) A4 specification (21GX297 mm) Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 312072 A8 B8 C8 ---- --D8 VI. Patent application number one The value-controlled oscillator operates under the period τ; a first loop filter is coupled with the aforementioned interpolator and the first value-controlled oscillator, and has an output that can The difference between D and the received symbol rate generates a response, wherein the first digital value controlled oscillator responds to the aforementioned first loop filter and generates an output signal representing the interpolation distance between consecutive samples, and the interpolator is based on The interpolation distance interpolation describes the received samples and generates an output signal representing the aforementioned interpolated samples; a coupled Nyquist filter coupled to the aforementioned interpolator; and a carrier recovery circuit for controlling the demodulator, including : A second digital value controlled oscillator; a digital removal rotation circuit, which responds to the aforementioned second digital value controlled oscillator and receives the in-phase and quadrature phase components of the sampled signal; a phase error estimation circuit, which is The output of the derotation circuit is coupled; a second loop filter is coupled to the output of the phase error estimation circuit; wherein the second value-controlled oscillator responds to the second loop filter; a constellation rotation The unit is used to rotate the signal constellation of the symbol; the one-step internal decoder is operated in the first mode and the second mode, the m-step naked inside The decoder includes: ------ Γ I installed ------ ordered ------- line (please read the precautions on the back before filling this page) Α4 »(210X297 ^) --- A8 B8 C8 D8 A branch metric calculation unit for the patent application scope printed by the Employee Consumer Cooperative of the Central Escalation Bureau of the Ministry of Economic Affairs, which is used to output the branch metric of the selected leakage rate and the selected leakage phase; multiple bonus-comparison-selection The block is used to output the value of the path metric derived from the aforementioned branch metric, and compare the aforementioned value with the value corresponding to the minimum value selected; a readjustment unit, operating on the output of the aforementioned addition-comparison-selection block according to the minimum value To readjust the outputs; a state transition module, operable in the first operation mode to detect an unreasonable state transition of the path metric value selected by the addition-comparison-selection block, the state transition mode The group can output estimates of symbol leakage rate, leakage phase, and rotation correction. The state transition module controls the branch metric calculation unit to change the selected leakage rate and selection based on the aforementioned shallow leakage rate and leakage phase estimation. Phase leakage module, and the state transition module uses the rotation correction estimate to control the constellation rotation unit; a synchronous search unit that is enabled in the second operation mode and responds to the state transition module to identify the data stream Synchronization information in; a backtracking module, connected to the aforementioned bonus comparison-selection block with continuous backtracking, and each _line represents the selection of the path determined by the bonus comparison selection block at the same time For all historical data of the value, the aforementioned traceback line has a plurality of traceback elements, each of which is m bits of the traceback data, wherein the traceback element is based on the content of at least one previous traceback line by Decoded selection line addressing; — — — — — — ^ 1! 11 Order ^ ~~ line (please read the precautions on the back and then fill out this page) 7. Apply for a patent to consume a deinterleaver, which is the same as the above m Step internal decoder is coupled. An output decoder receives the de-interlacing data of the deinterleaver; a de-randomizer coincides with the external decoder;-output interface Solutions of the aforementioned combined random relative consumption round out error correction data stream; and a second control means for controlling the system demodulator, the timing recovery circuit, the carrier recovery circuit and the interaction of the output interface. 5. A method of decoding the symbol of the received data, the data symbol is encoded according to the overlapping coding method, the data is marked according to the leakage matrix, the data has a plurality of state values and describes the continuous state from the first state to the subsequent state Transition, where a path is defined by the continuous state transition, the method includes: receiving the data and calculating a transition metric from the first state to a subsequent state 'where the aforementioned metric conforms to the measurement path following the path generated by the encoder of the data Possibility; Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the note on the back before filling in this page) In response to the preceding calculation steps, select the path generated by the transmitter that matches the data flow; maintain the aforementioned selection The continuous decision operation information represented by the controller; counting the reasonable state transition of the path selected by the selector; and determining the leakage rate and adjusting the leakage phase of the received data in response to the counting step. 6. An error detection and correction method for the data stream, the data stream is randomized, coded by overlap, leaked and interleaved at the leak rate and leak phase, of which the data S12072 Scope of patent application The Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs is printed with a wide symbol and transmitted at the symbol rate in the signal conformation. The steps included in the naked m step t decoding in the first and second modes are: For the selected _Leak rate riding selected &amp; leaky phase (iv) Calculate the sub-meter weight; calculate the material diameter measurement from the aforementioned expected shirt; compare the aforementioned road volume _ fixed rule, path measurement; readjust the value according to the aforementioned minimum path measurement; detect Do not consider the unreasonable state transitions in the aforementioned first-mode that conform to the aforementioned minimum path metric; the estimated symbol rhythm and domain phase response to the number of unreasonable state transitions in the occupation test; change the aforementioned selected leak rate and selected The leaky phase responds to the aforementioned estimation step; the synchronization information of the material in the aforementioned second assignment responds to the unreasonable state transition to the detection; executes the “recovery” while processing the m bits of the recovered data, according to at least -The content of the other backtracking lines is addressed by the selection line in the first backtracking line to address its backtracking elements; deinterleaving the m-step internally decoded data; externally decoding the deinterlaced data; and The random external decoding data. 7. A transmission and receiving system for random data streams with orthogonal phase shift keys, which are stacked and interleaved and are leaked at the leak rate and the non-leak phase. The standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297 meal) 312G72 A8 B8 C8 D8 The Ministry of Economic Affairs Central Standards Bureau employee consumer cooperative printed the patent application number and transmitted it at the symbol rate in the money configuration, and output the error correction data The system includes:-a Q demodulator that accepts the data like the aforementioned transmission symbol rate; an analog-to-digital converter that converts the analog output of the aforementioned 丨, demodulator; a sine interpolator, It receives samples from the aforementioned analog-to-digital converter at a sampling rate; a timing recovery circuit; a round Nyquist waver coupled to the aforementioned Sjncrt inserter; a carrier recovery circuit used to control the demodulator; A constellation rotation unit, which is used to rotate the signal constellation of the symbol; an m-step internal decoder, which operates in the first mode and the second mode; Steps internal decoders are converged; a round of output decoders receives the deinterleaved data of the deinterleaver; a derandomizer is coupled with the external decoder; a round of output interfaces is coupled with the deinterleaver The error correction data output of the output is beneficial; and ~ the second control device is used to control the interaction of the demodulator, the timing recovery and the carrier recovery circuit. The size of this paper is applicable to China-$ Standard (CNS) A4 specification (210X297mm) · i ^ ------, lamp ------- ^ (please read the precautions on the back before filling in this page)