/002 五 經濟部中央棟準局員工消費合作.社印¾ A7 B7 、發明説明（丨） 本發明是有關於半導體元件的製造方法，且特別是有 關於一種自動對準矽化物（salicide)的製造方法。 隨半導體元件的積集度增加’元件的設計尺寸越來越 小，使得MOS元件的汲極與源極的電阻値逐漸上升到與 MOS通道的電阻相當，爲了調整汲極與源極的片阻値 (sheet resistance)，並確保金屬與MOS間的淺接面的完整， 一種稱爲自動對準砂化物Uefl-jligned silicide;salicide)製 程的應用，使漸漸地走入〇·5 # m以下的VLSI製程。 鈦是現在salicide製程中最常用的一種耐熱金屬材料 (其他還有鉑、鈷、鎳以及鈀），其製程主要是在已完成閘 極定義的晶片上以濺鎪方式形成一薄金屬鈦層，接著利用 高溫使得鈦與MOS之閘極及源/汲極上的複晶矽反應，形 成矽化鈦。而未反應的鈦則以溼蝕刻法去除，在MOS的三 個極表面留下一薄矽化鈦層。由於自動對準矽化物製程不 但可在矽及複晶矽的表面製造低阻質的金屬矽化物（如矽 化鈦），且整個過程不需要經過光學微影，製程上相當簡 單，唯需注意矽化過程的快速熱回火之操作條件。 以習知一種自動對準矽化物之製造方法爲例來說明 其製造過程。 請先參照第1A圖，提供一半導體矽基底1〇，其上形 成有一場氧化區12 ' —電晶體，包括閘極之間氧化層14 和複晶矽電極16以及源/汲極擴散區20;並在閘極兩側壁上 形成一側壁間隔層18。 接著，請參照第1B圖，以DC濺鍍方式在基底上形成 -----Γ--I--^ 农------訂 (請先閲讀背面之注意事項再填寫本頁) 本呔诔心度滴用中阈阈家標專（CNS ) Λ4規格（210 < 公犛） 05 8 5twf doc/002 A7 B7 五、發明説明（2 ) 一耐熱金屬層（例如鈦、鉛、鈷、鎳以及鈀），在本說明是 形成一金屬鈦層22。 最後，請參照第1C圖，在高溫環境下以快速加熱製 程使鈦與閘極和源/汲極擴散區相連之區域產生矽化反 應，分別在閘極和源/汲極表面形成一薄矽化鈦層24和 26，其他區域的金屬鈦層則未反應，可以溼蝕刻法去除。 元件尺寸小於0.4 // m時，自動對準矽化鈦已變成一 必需的製程，因爲其提供一較低的片阻値及接觸阻値 (contact resistance)，對於一高速及低能消耗的元件來說非 常重要。 習知製程中以較厚的金屬鈦層通常可形成較佳的砂 化鈦層，其具有較佳的片阻値及接觸阻値，然卻造成接面 深度的降低，使得遺漏電流（leakage current)升高，且製程 所涉及的高溫矽化步驟並不易控;雖然快速加熱製程 (RTP)已廣泛應用在這個步驟上，但受到RTP的成熟度及 其製程上的因素，現在自動對準矽化物製程的良率都較傳 統的製程來得低。 有鑑於此，本發明提出一種自動對準矽化物形成的方 法，其步驟包括：一種自動對準矽化物形成的方法，提供 一矽基底，其上形成有一隔離用的增氧化區’及一電晶體 之閘極，包含有閘極導電層、閘極介電層和閘極側壁之側 壁間隔層；於該側壁間隔層及該場氧化層之間的該基底表 面以及該閘極導電層上選擇性成一磊晶矽層’其形成過程 中並以雜質同步摻雜之；形成一耐熱金屬層於該矽基底 4 (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印焚 __£ · 本紙張尺度適用中國國家標隼（CNS ) Λ4;見格（2丨(）':2(厂7公犛） 3087S1 05 8 5twrdoc/002 A7 B7 五 '發明説明（多） 上；進行一快速熱回火程序，使該耐熱金屬層與該磊晶矽 層相連之區域產生矽化反應，形成一耐熱金屬矽化物層， 而與該側壁間隔層及該場氧化區接觸的該耐熱金屬層則 未反應，且在快速熱回火過程中，並使該磊晶矽層中的雜 質擴散進入該閘極導電層及其兩側之矽基底表面，以增加 該閘極導電層之導電度，並形成該電晶體之源/汲擴散 區；以及去除未反應之該耐熱金屬層。此方法之優點在於 省略源極/汲極離子摻雜佈植步驟，而是在磊晶矽層形成 時同步摻雜之，於耐熱金屬與矽產生反應時，磊晶矽內之 雜質再擴散進入閘極兩側之矽基底表面，形成源/汲極擴 散區，一方面使製程更加便利，且又可改善因矽化反應的 高溫環境使接面深度降低，而造成漏電流（leakeage current)升高之缺點。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A〜1C圖是習知一種半導體之自對準矽化物之剖 面製造流程圖。 第2A〜2D圖是根據本發明以製造半導體之自動對準 矽化物之流程圖。 實施例 首先，請參照第2 A圖，提供一如第1A圖所示的半導 體元件，其中相同功能的元件以相同標號標標示之；其包 II - - -- _! i^n —^ϋ - - I = I (請先閱讀背面之注意事項再填寫本頁) 經濟部中失標隼局員工消費合作社印繁 本紙张尺度適叫中阀阀京標，1M C:NS ) A4tiL格（210 O'r公棼） S082S1 Γ doc/002 A7 B7 經濟部中央榡隼局員工消t合作，社.2-¾ 五、發明説明（毕） 括一 P型矽基底10，其上形成有一場氧化區12、一電晶 體，包括閘極介電層14及閘極導電層16，並在閘極兩側 壁形成一側壁間隔層18，其中閘極導電層之材料例如是複 晶矽，而閘極介電層及側壁間隔層之材料例如是二氧化 矽。 其次，請參照第2B圖，利用HC1/SiC12H2/H2/PH3所組 成的氣體，以化學氣相沈積法（CVD)選擇性地於矽基底表 面及閘極之複晶矽電極表面各沈積一磊晶矽層 (epitaxial Si)19及21，且在沈積過程中並以N型離子 例如：碟或砷同步摻雜之（in-situ doping)。 接著，請參照第2C圖，以直流滕鍍方式（DC sputtering) 形成一耐熱金屬層於矽基底上，耐熱金屬例如是：鈦、鉑、 鈷、鎳及鈀；本實施例是形成一金屬鈦層22。 然後，請參照第2D圖，金屬鈦層形成後，進行第一次 快速熱回火，使金屬鈦層與磊晶矽層相連之區域產生矽化 反應，在閘極複晶矽電極之其兩側之基底表面各形成一自 動對準矽化鈦層24及26 ;其中，快速熱回火之條件是在 氮氣環境下，溫度約介於600〜900 °C時回火約20〜120 秒。此外，在進行快速熱回火過程中，磊晶矽層中所摻雜 的雜質會擴散進入複晶電極及其兩側之矽基底表面，以增 加閘極複晶矽電極之導電度，並且形成電晶體之源/汲極 擴散區20，而不需另一離子摻雜佈植以形成源/汲極擴散 區之步驟。與側壁間隔層及場氧化區接觸的鈦則未產生矽 化反應，可以反應性化學触刻法（r e a c t i v e c hem 1 c a 1 e t c h ) ------τ--.--F^.------訂 (請先閲讀背面之注意事項再填寫本頁) 表4氏張反度適州中阈阐家標準（C.NS ) Λ4規格（：Μ〇κ2<ί7公筇） 0$85twf.doc/002 Λ 7 B7 五、發明説明（t;) 蝕刻去除掉。如此，本實施例依據本發明完成NMOS元件的 製造，具有低片阻値（sheet resistance)且矽化反應後又 不會使接面深度降低，升高漏電流，製程比習知方法方便， 效果又較佳；而PMOS元件之製造則與_0S之步驟大致相 同，惟其提供一 N型矽基底，而摻雜之離子源則是P型離 子，其詳細製程在此不再贅述。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 I- - - 111 I - - - - ΊΙ— 11 ^^1 I - - -.. n (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作杜印裝 7 本紙張尺度適闲中國國家標隼（CNS ) Λ4吡格（2丨Ox、2叩公缔）/ 002 Fifth Ministry of Economic Affairs, Central Bureau of Industry and Commerce Employee Consumer Cooperation. Social Print ¾ A7 B7 、 Invention Description (丨) The present invention relates to the manufacturing method of semiconductor components, and in particular it relates to an automatic alignment of salicide Production method. As the accumulation of semiconductor devices increases, the design size of the devices becomes smaller and smaller, so that the resistance value of the drain and source of the MOS device gradually rises to be equivalent to the resistance of the MOS channel. In order to adjust the sheet resistance of the drain and source (Sheet resistance), and to ensure the integrity of the shallow junction between the metal and the MOS, an application called Uefl-jligned silicide; salicide) process, which gradually entered into the VLSI manufacturing process. Titanium is the most commonly used heat-resistant metal material in the current salicide process (there are also platinum, cobalt, nickel and palladium). Its process is mainly to form a thin metal titanium layer by sputtering on the wafer that has completed the gate definition. Next, using high temperature, titanium reacts with the polysilicon on the gate and source / drain of the MOS to form titanium silicide. The unreacted titanium is removed by wet etching, leaving a thin layer of titanium silicide on the surface of the three electrodes of the MOS. Since the automatic alignment silicide process can not only produce low-resistance metal silicide (such as titanium silicide) on the surface of silicon and polycrystalline silicon, and the entire process does not need to undergo optical lithography, the process is quite simple, only need to pay attention to silicide Operating conditions for rapid thermal tempering of the process. The conventional manufacturing method of self-aligned silicide is taken as an example to illustrate the manufacturing process. Referring first to FIG. 1A, a semiconductor silicon substrate 10 is provided, on which a field oxide region 12′-transistor is formed, including an oxide layer 14 between gates and a polycrystalline silicon electrode 16 and a source / drain diffusion region 20 ; And a sidewall spacer 18 is formed on both sidewalls of the gate. Next, please refer to Figure 1B, the DC sputtering method is formed on the substrate ----- Γ--I-^ Agriculture ------ order (please read the precautions on the back before filling this page) This standard for the threshold threshold of the heart rate drops (CNS) Λ4 specifications (210 < public yak) 05 8 5twf doc / 002 A7 B7 5. Description of the invention (2) A heat-resistant metal layer (such as titanium, lead, Cobalt, nickel and palladium), in this description, a metallic titanium layer 22 is formed. Finally, please refer to Figure 1C, under a high temperature environment, a rapid heating process is used to cause the silicidation reaction between the titanium and the gate and source / drain diffusion regions, forming a thin titanium silicide on the surface of the gate and source / drain respectively Layers 24 and 26, and the metal titanium layer in other regions are unreacted and can be removed by wet etching. When the component size is less than 0.4 // m, automatic alignment of titanium silicide has become a necessary process, because it provides a lower sheet resistance and contact resistance (contact resistance), for a high-speed and low energy consumption device Very important. In the conventional manufacturing process, a thicker titanium layer can generally form a better titanium sand layer, which has better sheet resistance and contact resistance, but it causes a reduction in the depth of the junction, resulting in leakage current (leakage current) ), And the high-temperature silicidation step involved in the process is not easy to control; although rapid heating process (RTP) has been widely used in this step, due to the maturity of RTP and factors in the process, it is now automatically aligned to the silicide The yield of the process is lower than that of the traditional process. In view of this, the present invention proposes a method for automatically aligning silicide formation, the steps of which include: a method for automatically aligning silicide formation, providing a silicon substrate on which an isolated oxidation-increasing region is formed and an electrical The gate of the crystal includes a gate conductive layer, a gate dielectric layer and a sidewall spacer layer of the gate sidewall; the substrate surface and the gate conductive layer are selected between the sidewall spacer layer and the field oxide layer In the process of forming an epitaxial silicon layer ', it is doped with impurities simultaneously; a heat-resistant metal layer is formed on the silicon substrate 4 (please read the precautions on the back before filling this page) Cooperative printing and burning __ £ · This paper scale is applicable to China National Standard Falcon (CNS) Λ4; see grid (2 丨 () ': 2 (factory 7 male yak) 3087S1 05 8 5twrdoc / 002 A7 B7 Five' invention description (more ) On; a rapid thermal tempering process is carried out to cause a silicidation reaction between the heat-resistant metal layer and the epitaxial silicon layer to form a heat-resistant metal silicide layer, which is in contact with the sidewall spacer and the field oxidation region The heat-resistant gold The layer is unreacted, and during the rapid thermal tempering process, the impurities in the epitaxial silicon layer diffuse into the gate conductive layer and the surface of the silicon substrate on both sides to increase the conductivity of the gate conductive layer And form the source / drain diffusion region of the transistor; and remove the unreacted heat-resistant metal layer. The advantage of this method is to omit the source / drain ion implantation step, but when the epitaxial silicon layer is formed Simultaneously doped, when the heat-resistant metal reacts with silicon, the impurities in the epitaxial silicon re-diffuse into the surface of the silicon substrate on both sides of the gate to form the source / drain diffusion area, on the one hand, the process is more convenient, and To improve the shortcomings caused by the reduction of the junction depth due to the high temperature environment of the silicidation reaction and the increase in leakage current. To make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following is a special The preferred embodiment, in conjunction with the attached drawings, will be described in detail as follows: Brief description of the drawings: Figures 1A ~ 1C are conventional cross-sectional manufacturing flowcharts of a self-aligned silicide of a semiconductor. Figures 2A ~ 2D is based on The present invention uses a flow chart for the automatic alignment of silicides for manufacturing semiconductors. Embodiments First, please refer to FIG. 2A to provide a semiconductor device as shown in FIG. 1A, wherein components with the same function are marked with the same reference numerals; Its package II---_! I ^ n — ^ ϋ--I = I (please read the precautions on the back before filling this page) The standard size of the printed and printed copy of the Falcon Bureau employee consumer cooperative in the Ministry of Economic Affairs is appropriate Beijing Valve, 1M C: NS) A4tiL grid (210 O'r gong) S082S1 Γ doc / 002 A7 B7 Central Ministry of Economic Affairs staff of the Central Falcon Bureau, cooperation. Co. 2-¾ V. Description of invention (bi ) Includes a P-type silicon substrate 10 on which a field oxide region 12 and a transistor are formed, including a gate dielectric layer 14 and a gate conductive layer 16, and a sidewall spacer layer 18 is formed on both sidewalls of the gate, wherein The material of the gate conductive layer is, for example, polycrystalline silicon, and the material of the gate dielectric layer and the sidewall spacer is, for example, silicon dioxide. Secondly, please refer to Figure 2B, using the gas composed of HC1 / SiC12H2 / H2 / PH3 to selectively deposit one epitaxy on the surface of the silicon substrate and the surface of the polycrystalline silicon electrode of the gate electrode by chemical vapor deposition (CVD) The epitaxial Si layers 19 and 21 are in-situ doping with N-type ions such as dish or arsenic during the deposition process. Next, referring to FIG. 2C, a heat-resistant metal layer is formed on the silicon substrate by DC sputtering. The heat-resistant metals are: titanium, platinum, cobalt, nickel, and palladium; in this embodiment, a metal titanium is formed Layer 22. Then, referring to FIG. 2D, after the titanium metal layer is formed, the first rapid thermal tempering is performed to cause a silicidation reaction between the titanium metal layer and the epitaxial silicon layer, on both sides of the gate polysilicon electrode Each substrate surface is formed with an auto-aligned titanium silicide layer 24 and 26; wherein, the condition of rapid thermal tempering is under nitrogen atmosphere, and the tempering is about 20 ~ 120 seconds when the temperature is about 600 ~ 900 ° C. In addition, during the rapid thermal tempering process, impurities doped in the epitaxial silicon layer will diffuse into the polycrystalline electrode and the silicon substrate surface on both sides to increase the conductivity of the gate polycrystalline silicon electrode and form The source / drain diffusion region 20 of the transistor does not require another step of ion implantation to form the source / drain diffusion region. Titanium that is in contact with the sidewall spacer and the field oxidation region does not produce silicidation reaction, and can be reactive chemical lithography (reactivec hem 1 ca 1 etch) ------ τ --.-- F ^ .--- --- Order (please read the notes on the back and then fill in this page) Table 4 Zhang's degree of moderate state threshold threshold (C.NS) Λ4 specifications (： Μ〇κ2 < ί7 公 筇) 0 $ 85twf .doc / 002 Λ 7 B7 5. Description of the invention (t;) Etched away. In this way, this embodiment completes the manufacture of the NMOS device according to the present invention, which has low sheet resistance and does not reduce the junction depth after silicidation, and increases the leakage current. The process is more convenient than the conventional method, and the effect is also Preferably, the manufacturing process of the PMOS device is almost the same as that of the _OS, except that it provides an N-type silicon substrate, and the doped ion source is P-type ions. The detailed manufacturing process will not be repeated here. Although the present invention has been disclosed as above in a preferred embodiment, it is not intended to limit the present invention. Anyone who is familiar with this skill can make some changes and modifications within the spirit and scope of the present invention. The scope of protection of an invention shall be deemed as defined by the scope of the attached patent application. I---111 I----ΊΙ— 11 ^^ 1 I---.. n (please read the precautions on the back before filling out this page) Employee Cooperative Printing and Printing Duo Pack of 7 copies Chinese Standard Falcon (CNS) Λ4 Peg (2 丨 Ox, 2 percussion)