JP2000133802A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which can form a high heat-resistant silicide film having satisfactory and stable electrical characteristics on a fine pattern. SOLUTION: An element isolation region 102 is formed in a specified region on the surface of one conductivity-type Si substrate 101. A gate oxide film 103 is formed in an element formation region on the substrate surface. On the oxide film 103, a poly Si film 104 and a first silicide film 105a of high- melting point metal are formed, and thereon a mask insulating film 106 is formed. The insulating film is used as a mask, unwanted parts of the first silicide film, the poly Si film and the gate oxide film are etched and removed. A two-layered gate electrode of poly Si and first silicide is formed. Without eliminating the mask insulating film on the electrode, a sidewall spacer 107 of an insulating film is formed on the electrode side surface part, and the peripheral part of the electrode is covered with the insulating film. After a diffused layer 108 of opposite conductivity-type to the substrate is formed in the element formation region, and a metal film is formed only on the layer 108, the metal film is made to react with the diffused layer surface by heat treatment, and a second silicide film is formed only on the diffused layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an electrode forming method using a salicide technique for selectively forming a silicide film on a diffusion layer of a semiconductor device.

[0002]

2. Description of the Related Art Self-alignment is performed on an active area of a semiconductor device.
A silicide for selectively forming a silicide film (self-aligned silicide, Self Align Silicid)
e, salicide) In the technology, it is important to form a silicide film having a uniform thickness, a low and stable electric resistance, and a high heat resistance.

For this reason, the silicide has a low specific resistance,
A salicide technique using cobalt (Co) having an appropriate Schottky barrier height for both the N-type and the N-type and having little dependence on the impurity concentration and pattern size of the silicidation reaction is employed. For example, K. Goto
et al, Technical Digest o
f IEEE International Elec
tron DeviceMeeting 1995, p.
p449-452. (1995) includes cobalt (C
A method of forming a silicide film in a self-alignment manner on a gate electrode and a diffusion layer using o) is disclosed. This prior art will be described below.

FIG. 5 is a longitudinal sectional view showing the prior art in the order of manufacturing steps. First, as shown in FIG. 5A, an element isolation region 102 formed by a LOCOS method, a gate oxide film 103,
MOSFET (M) composed of a polycrystalline silicon film 104 serving as a gate electrode, a sidewall spacer 107, and a diffusion layer 108 having an n ⁺ / p junction depth of 100 nm.
etal Oxide Semiconductor
A cobalt film 109a is formed to a thickness of 10 nm on a Field Effect Transistor (metal-oxide film-semiconductor field-effect transistor) by a sputtering method.

Further, a titanium nitride (TiN) film 109b is formed thereon to a thickness of 30 nm by sputtering. Subsequently, as shown in FIG. 5B, the silicon substrate 101 is heated at 550 ° C. in a nitrogen atmosphere by a lamp rapid heating method.
A heat treatment is performed for 30 seconds, so that the surface of the polycrystalline silicon film 104 and the diffusion layer 108 serving as the gate electrode is
9a to form a cobalt silicide film 110 having a composition of CoxSiy (x ≧ y) in a self-aligned manner.

The titanium nitride film 109b is formed for the purpose of preventing the oxidation of cobalt during the heat treatment for silicidation. Subsequently, as shown in FIG.
After the titanium nitride film 109b is removed by a wet etching method and the unreacted cobalt film 109a is selectively removed, 750 to 750 in a nitrogen atmosphere by a lamp rapid heating method.
A heat treatment at 900 ° C. for 30 seconds is performed to convert the cobalt silicide film 110 having a composition of CoxSiy (x ≧ y) on the surface of the gate electrode 104 and the diffusion layer 106 into a thermally stable and low-resistance cobalt disilicide (CoSi).
₂ ) Phase transition.

However, in this method, a silicide film is formed on a different base from polycrystalline silicon on the gate electrode and monocrystalline silicon on the diffusion layer. In general, when comparing silicide films formed under the same heat treatment conditions, a silicide film formed on polycrystalline silicon has lower heat resistance than a silicide film formed on a single crystal diffusion layer. Therefore, if a high temperature is applied in the heat treatment during the manufacturing process after the formation of the silicide film, the resistance of the silicide film may increase due to aggregation of the silicide film. Will be determined by
In the case of a logic device, after silicidation is basically performed on the gate electrode and the diffusion layer, there is no step that requires a high-temperature heat treatment, so that a very high heat resistance is required for the silicide film. Never.

However, for example, in a mixed memory device in which a memory circuit and a logic circuit coexist on the same chip, unlike the above-described logic device, after the silicidation on the diffusion layer and the gate electrode, the memory cell There is a process that requires high heat treatment in the capacitor manufacturing process of some parts. Therefore, when the heat treatment temperature is restricted by the upper limit temperature due to the heat resistance of the silicide film, there is a possibility that a problem such as a failure to obtain sufficient capacitance characteristics may occur.

Further, a technique of depositing a metal film on the entire surface of a silicon substrate and silicidizing only the region where silicon is exposed to reduce the resistance is performed at the end of the element isolation region near the element isolation end. Since the metal layer on the existing insulating film is subjected to the reaction, the diffusion layer and the gate electrode are miniaturized, and when the pn junction depth of the diffusion layer is reduced, the junction leakage due to the "penetration" of silicide is caused. There is a concern about deterioration of characteristics.

[0010] Therefore, the conventional salicide technique described above forms a silicide film on a gate and a diffusion layer,
There is a drawback that the technique for reducing the resistance does not have a sufficient degree of perfection.

[0011]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks of the prior art, and in particular, to form a highly heat-resistant silicide film having good and stable electric characteristics on a fine pattern. And a method of manufacturing the same.

[0012]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object. That is, in a first aspect of the method of manufacturing a semiconductor device according to the present invention, an element isolation region is formed in a predetermined region on the surface of a silicon substrate of one conductivity type, and a gate oxide film is formed in an element formation region on the surface of the silicon substrate. Forming a polycrystalline silicon film on the gate oxide film, forming a first silicide film on the polycrystalline silicon film, and forming a mask insulating film on the first silicide film. An unnecessary portion of the first silicide film, the polycrystalline silicon film and the gate oxide film is removed by an etching method using the mask insulating film as a mask to form two layers of the polycrystalline silicon film and the first silicide film. Forming a gate electrode made of a film, and removing a side wall of an insulating film on a side surface of the gate electrode without removing the mask insulating film on the gate electrode. Forming a capacitor and covering the periphery of the gate electrode with an insulating film; forming a diffusion layer of a conductivity type opposite to that of the silicon substrate in a predetermined region of the element formation region; Selectively forming a metal film only on the upper surface, and performing a heat treatment to react the metal film with the surface of the diffusion layer to selectively form a second silicide film only on the diffusion layer. In a second aspect, the first silicide film is any one of titanium silicide, tungsten silicide, and tantalum silicide. In a fourth aspect, the metal film is made of one of cobalt (Co) and nickel (Ni). In a fourth aspect, a metal film is selectively formed only on the diffusion layer. Form In the fifth aspect, the step of selectively forming a metal film only on the diffusion layer is performed by an electroless plating method. In a sixth mode, the mask insulating film is any one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. .

[0013] Further, an aspect of the semiconductor device according to the present invention is as follows.
In a semiconductor device in which a silicide film is formed on a diffusion layer and a gate polysilicon, the silicide film on the diffusion layer and the gate polysilicon is a silicide film having a different composition, and the heat resistance of the silicide film on the polysilicon is high. In this case, the heat resistance is higher than the heat resistance of the silicide film formed on the diffusion layer.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a method of manufacturing a semiconductor device according to the present invention, an element isolation region is formed in a predetermined region on the surface of a silicon substrate of one conductivity type, and a gate oxide film is formed in an element formation region on the surface of the silicon substrate. Forming, forming a polycrystalline silicon film on the gate oxide film, forming a first silicide film on the polycrystalline silicon film, and forming a mask insulating film on the first silicide film Then, unnecessary portions of the first silicide film, the polycrystalline silicon film, and the gate oxide film are removed by an etching method using the mask insulating film as a mask to remove the polycrystalline silicon film and the first silicide film. Forming a gate electrode made of a layer film; and forming a sidewall made of an insulating film on a side surface of the gate electrode without removing the mask insulating film on the gate electrode. Forming a spacer and covering the periphery of the gate electrode with an insulating film; forming a diffusion layer of a conductivity type opposite to that of the silicon substrate in a predetermined region of the element formation region; A step of selectively forming a metal film only on the diffusion layer and a step of performing a heat treatment so that the metal film and the surface of the diffusion layer react with each other to selectively form a second silicide film only on the diffusion layer. Therefore, according to the manufacturing method of the present invention, since the silicide film formed on the polycrystalline silicon film that is difficult to obtain high heat resistance becomes a titanium silicide film having higher heat resistance than the cobalt silicide film, the entire gate electrode can be formed. The heat resistance is higher compared to that obtained by conventional cobalt salicide technology.

Further, in the step of forming a silicide on the diffusion layer, the metal film is selectively deposited only in the region where silicidation is required, so that the metal film is not deposited on the insulating film existing near the element isolation end. No reaction occurs. For this reason, even when the element isolation region is miniaturized or the junction depth of the diffusion layer becomes shallow, an excellent effect such as no junction leakage due to "bite" of silicide is obtained.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a semiconductor device and a method of manufacturing the same according to the present invention will be described below in detail with reference to the drawings. (First Specific Example) FIGS. 1 and 2 show the structure of a specific example of a semiconductor device and a method of manufacturing the same according to the present invention. Forming a device isolation region 102 in a predetermined region, forming a gate oxide film 103 in a device formation region on the surface of the silicon substrate 101, and forming a polycrystalline silicon film 104 on the gate oxide film 103; Forming a first silicide film 105a on the polycrystalline silicon film 104; and forming a mask insulating film 1 on the first silicide film 105a.
06, and the first silicide film 105a is formed by an etching method using the mask insulating film 106 as a mask.
The polycrystalline silicon film 104 and the gate oxide film 10
Forming a gate electrode composed of a two-layer film of the polycrystalline silicon film 104 and the first silicide film 105a by removing unnecessary portions 3; and without removing the mask insulating film 106 on the gate electrode. Sidewall spacers 107 made of an insulating film are formed on side surfaces of the gate electrode, and the periphery of the gate electrode is formed on insulating films 106 and 10.
7, a step of forming a diffusion layer 108 of a conductivity type opposite to that of the silicon substrate in a predetermined region of the element formation region, and a step of selectively forming a metal film 109a only on the diffusion layer 108. And a heat treatment are performed to cause the metal film 109a to react with the surface of the diffusion layer 108 so that the second silicide film 11 is selectively formed only on the diffusion layer 108.
1 shows a method for manufacturing a semiconductor device including a step of forming a zero.

Hereinafter, the present invention will be described in more detail. First, as shown in FIG. 1A, a predetermined region on a silicon substrate 101 has a depth of 300 formed of a silicon oxide film.
The element isolation region 102 having a trench filling structure of about 400 nm and a width of 200 to 500 nm is formed by using a known method such as a dry etching method, an oxide film CVD method, and an oxide film CMP method.

Subsequently, a gate oxide film 103 having a thickness of 3 to 8 nm is formed in an element formation region on the silicon substrate by a thermal oxidation method, and further, a 100 to 150 nm thickness is formed on the silicon substrate 101 by a CVD method. Polycrystalline silicon film 104
Is deposited, and arsenic (As) or boron (B) is ion-implanted to perform a heat treatment for activation. Then, titanium silicide (TiSix, x ≧ 2) is formed by sputtering.
The film 105a is formed on the polycrystalline silicon film 104 by 50 to 100
It is formed with a thickness of nm.

In the first specific example, the polycrystalline silicon film 10
Although a titanium silicide film is used as the low-resistance silicide film on 4, the present invention is not limited to this, and a high-melting-point silicide film such as a tungsten silicide film or a tantalum silicide film may be used. Subsequently, a mask insulating film 106 composed of a silicon oxide film is formed on the titanium silicide film 105a to a thickness of 200 to 400 nm by a CVD method, and the mask insulating film 106 is patterned by a dry etching method using a photoresist as a mask. I do.

Then, the titanium silicide film 10 is formed by dry etching using the mask insulating film 106 as a mask.
5a, polycrystalline silicon film 104 and gate oxide film 103
Is removed to form a gate electrode composed of the titanium silicide film 105a and the polycrystalline silicon film 104. In this etching step, the mask insulating film 106, the titanium silicide film 105a, and the polycrystalline silicon are formed such that the thickness of the mask insulating film 106 remaining on the titanium silicide film 105a serving as the gate electrode after the gate etching is about 10 to 30 nm. It is necessary to adjust the etching selectivity of the film 104.

Further, in order to obtain an optimum etching selectivity, a material such as a silicon nitride film or a silicon oxynitride film other than the silicon oxide film may be used as the mask insulating film. Then, as shown in FIG. 1B, a silicon oxide film having a thickness of 50 to 100 nm is formed on the silicon substrate 101 by using the CVD method, and is anisotropically etched back.
A sidewall spacer 107 is formed leaving only the silicon oxide film formed on the side surface of the gate electrode. Although not shown, ion implantation is performed before this step.
An impurity implantation region is formed on the side of the gate electrode, and the transistor is formed as an LDD (Lightly Doped Drain).
n).

Subsequently, the sidewall spacer 107
Arsenic (As) or boron (B) is ion-implanted into the silicon substrate region exposed on the side by ion implantation.
Heat treatment for activation is performed to form a diffusion layer 108. Further, as shown in FIG. 2A, a region where the silicon on the surface of the silicon substrate 101 is exposed, that is, the diffusion layer 108 is formed.
The cobalt film 109a is selectively formed on the upper surface by selective CVD using an organic source (Chemical Vapor Deposition, Chemical
Vapor Deposition)
It is formed with a thickness of 15 nm.

The selective CVD of the cobalt film 109a is performed as follows.
For example, as an organic source, bis (hexafluoroacetylacetonato) cobalt (II) (Co (C ₅ HF)
_{Using 6} O ₂ ) ₂ ), a substrate temperature of 200 to 400 ° C., a carrier hydrogen gas flow rate of 100 to 400 sccm, a vaporized bis (hexafluoroacetylacetonato) cobalt (II) gas flow rate of 10 to 40 sccm, and a pressure of 10 to 5
It is performed under the condition of 0 Pa.

Under these conditions, the deposition rate of the cobalt film is approximately 5 to 15 nm / min. And relatively slow, a thin cobalt film can be formed with high uniformity and reproducibility. Therefore, a thin silicide film is required.
It has an advantage that it can be easily applied to a semiconductor device having a shallow diffusion layer junction depth.

Subsequently, the silicon substrate 101 is applied to the silicon substrate 101 in a nitrogen or argon gas atmosphere by a lamp rapid heating method.
A heat treatment is performed at 50 to 550 ° C. for 30 seconds to form a diffusion layer 108.
React with the cobalt film 109a to form CoxSi
Cobalt silicide film 11 having a composition of y (x ≧ y)
0 is formed in a self-aligned manner. If Cobalt Selective CVD
In the case, even if the deposition of the cobalt film is non-selective growth, since the layers other than the diffusion layer 108 are insulating films,
After the heat treatment, if wet etching is performed using, for example, a mixed aqueous solution of ammonia and hydrogen peroxide, or a mixed aqueous solution of hydrochloric acid and hydrogen peroxide, the element isolation region 102 that has not reacted with silicon, the mask insulating film 106, and the sidewalls Since the cobalt film 109a on the spacer 107 can be easily removed, a defect such as an electrical short between the gate electrode and the diffusion layer does not occur, so that there is no problem.

Further, a second heat treatment at 700 to 800 ° C. for 10 to 30 seconds is performed in a nitrogen atmosphere by a lamp rapid heating method to form CoxS formed on the surface of the diffusion layer 108.
Cobalt silicide film 1 having a composition of iy (x ≧ y)
10 undergoes a phase transition to thermally and electrically stable cobalt disilicide (CoSi ₂ ). According to this technique,
Since the silicide film formed on the polycrystalline silicon film, which is difficult to obtain high heat resistance, is a titanium silicide film with higher heat resistance than the cobalt silicide film, the heat resistance of the entire gate electrode can be obtained by the conventional cobalt salicide technology It is higher than that.

Further, since the resistance of the gate electrode and the diffusion layer can be reduced, the problem of heat resistance which has been a problem can be overcome. Further, in the step of forming silicide on the diffusion layer, the metal film can be selectively deposited only in the region where silicidation is required, so that the metal film can be deposited on the insulating film near the element isolation end. Since no reaction occurs, even when the element isolation region is miniaturized or the junction depth of the diffusion layer becomes shallow, excellent effects such as no junction leakage characteristics due to silicide "biting" are obtained. Can be

(Second Embodiment) As another embodiment of the present invention, a tantalum silicide film is used as a silicide film of a gate electrode, and a cobalt film which is a metal film for silicidizing a diffusion layer is formed by an electroless plating method. can do. The manufacturing method is shown as a second specific example in FIGS.

First, as shown in FIG. 3A, using the same material and method as in the first embodiment, the silicon substrate 1
01 and a depth of 30 formed of a silicon oxide film in a predetermined region.
An element isolation region 102 having a groove filling structure having a width of 0 to 400 nm and a width of 200 to 500 nm, a gate oxide film 103 having a thickness of 3 to 8 nm in an element formation region on a silicon substrate, and a 100 to 150 nm thickness having impurities introduced therein. A polycrystalline silicon film 104 is formed.

Then, a tantalum silicide (TaSix, x ≧ 2) film 105b is formed with a thickness of 50 to 100 nm on the polycrystalline silicon film 104 by a sputtering method or a CVD method by a sputtering method. In this specific example, a tantalum silicide film is used as a low-resistance silicide film on the polycrystalline silicon film 104 serving as a gate electrode. However, the present invention is not limited to this, and a high melting point silicide such as a tungsten silicide film is used. A film may be used.

Subsequently, a mask insulating film 106 composed of a silicon oxide film is formed on the tantalum silicide film 105b to a thickness of 200 to 400 nm by using the CVD method, and thereafter, a dry etching method using a photoresist as a mask. Patterning. Then, FIG.
As shown in FIG. 3, the tantalum silicide film 105 is formed by dry etching using the mask insulating film 106 as a mask.
b, polycrystalline silicon film 104 and gate oxide film 10
The unnecessary portion 3 is etched and removed to form a gate electrode composed of the tantalum silicide film 105b and the polycrystalline silicon film 104.

In this etching step, the mask insulating film 106 and the tantalum silicide film 105 are formed such that the thickness of the mask insulating film 106 remaining on the tantalum silicide film 105b after the gate etching is about 10 to 30 nm.
It is necessary to adjust the etching selectivity of b and the polycrystalline silicon film 104. Further, it is possible to optimize the etching selectivity by using a silicon nitride film or a silicon oxynitride film other than the silicon oxide film as the mask insulating film.

Next, as shown in FIG. 4A, a silicon oxide film having a thickness of 50 to 100 nm is formed on the silicon substrate 101 by using the CVD method, and the gate electrode is formed by anisotropic etch back. Only the silicon oxide film formed on the side surface is left as a sidewall spacer 107. Although not shown, ion implantation is performed before this step.
An impurity implantation region is formed on the side of the gate electrode, and the transistor is formed as an LDD (Lightly Doped Drain).
n).

Subsequently, the sidewall spacer 107
Arsenic (As) or boron (B) is ion-implanted into the silicon substrate region exposed on the side by ion implantation.
Heat treatment for activation is performed to form a diffusion layer 108. Then, a cobalt film 109a is selectively formed on the surface of the silicon substrate 101 where silicon is exposed, that is, on the diffusion layer 108, by electroless plating to a thickness of 10 to 15 nm.
Formed with a thickness of

The plating solution used for the electroless plating of the cobalt film contains cobalt chloride as a main component, hydrazine hydrochloride as a reducing agent, sodium tartrate as a complexing agent and a buffer, and aqueous ammonia as a pH adjusting agent. Use the one that is used. The wafers are brought to a concentration of 0.
30 to 50-0.1 g / L palladium chloride solution
After immersion for 1 second to 1 minute to selectively deposit a thin palladium film (not shown) of about 5 nm only on the exposed silicon surface, the wafer is washed with pure water, and the cobalt chloride is removed. 05 mol / l, hydrazine hydrochloride 1.0 mol / l, and sodium tartrate 0.
4 mol / liter, adjusted to pH 9 with ammonia water, caustic soda, etc., liquid temperature 70 to 90
The wafer is immersed in a plating solution at a temperature of ° C. to selectively form a cobalt film 109 a with a thickness of 10 to 15 nm on the region where silicon is exposed, that is, on the diffusion layer 108.

Under these conditions, the cobalt film has a thickness of 30 nm /
min. A film forming speed of the order can be obtained. However, when it is desired to lower the film formation rate due to the problem of the controllability of the film thickness of cobalt, it is effective to lower the pH of the plating solution or lower the plating temperature. In the second specific example, an electroless plating solution using hydrazine hydrochloride as a reducing agent is used. However, the present invention is not limited to this. In addition, sodium hypophosphite and sodium borohydride may be used. A plating solution as a reducing agent may be used.

Further, the metal film for silicidizing the diffusion layer is not limited to cobalt, but may be nickel. Also in this case, a cobalt plating solution using sodium hypophosphite, sodium borohydride, dimethylamine borane, or the like can be used as a reducing agent for the metal film. Then, as shown in FIG. 4B, the silicon substrate 101 is subjected to heat treatment at 450 to 550 ° C. for 30 seconds in a nitrogen or argon atmosphere by a lamp rapid heating method, so that the surface of the diffusion layer 108 and the cobalt film 109 a
To form a cobalt silicide film 110 having a composition of CoxSiy (x ≧ y) in a self-aligned manner.

Even if the formation of the cobalt film is not selected in the electroless plating step of the cobalt film, the portions other than the diffusion layer 108 are covered with the insulating film. If wet etching is performed using a mixed aqueous solution of hydrogen peroxide, the element isolation region 102 that has not reacted with silicon, the mask insulating film 1
06 and the cobalt film 109a on the sidewall spacer 107 can be easily removed, so that a defect such as an electrical short between the gate electrode and the diffusion layer does not occur, and does not cause a problem.

Further, by a rapid heating method using a lamp, in a nitrogen or argon gas atmosphere at 700 to 800.degree.
By performing a second heat treatment for 30 seconds, the cobalt silicide film 110 having the composition of CoxSiy (x ≧ y) formed on the surface of the diffusion layer 108 is thermally and electrically stable cobalt disilicide (CoSi _2). ).

According to this method, the silicide film formed on the polycrystalline silicon film, which is difficult to obtain high heat resistance, becomes a tantalum silicide film having higher heat resistance than the cobalt silicide film. It is higher than that obtained by conventional cobalt salicide technology, and in the process of forming silicide on the diffusion layer,
Since the metal film can be selectively deposited only in the region where silicidation is necessary, there is no reaction with the metal film on the insulating film existing near the element isolation end, and therefore, the fineness of the element isolation region is reduced. Even if the formation of the diffusion layer progresses or the junction depth of the diffusion layer becomes shallow, effects such as the occurrence of junction leakage characteristics due to "bite-in" of silicide are obtained.

[0041]

As described above, according to the present invention,
Since the silicide film formed on the polycrystalline silicon film, which is difficult to obtain high heat resistance, has higher heat resistance than the silicide film formed on the diffusion layer, the heat resistance of the entire gate electrode is reduced by the conventional salicide technology. And the resistance of the gate electrode and the diffusion layer can be reduced, so that the conventional problem of heat resistance can be overcome.

In the step of forming silicide on the diffusion layer, the metal film can be selectively deposited only on the region where silicidation is required, so that the metal film on the insulating film existing near the element isolation end can be formed. No reaction with the membrane occurs,
Even when the element isolation end is miniaturized or the junction depth of the diffusion layer becomes shallow, an excellent effect is obtained such that junction leakage due to "bite" of silicide does not occur.

It should be noted that the present invention is not limited to the above specific examples, and it is clear that each specific example can be appropriately modified within the scope of the technical idea of the present invention.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a first specific example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing step continued from FIG. 1;

FIG. 3 is a cross-sectional view showing a manufacturing process of a second specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing step continued from FIG. 3;

FIG. 5 is a cross-sectional view showing a manufacturing step in a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 101 silicon substrate 102 element isolation region 103 gate oxide film 104 polycrystalline silicon film 105a titanium silicide film (first silicide film) 105b tantalum silicide film (first silicide film) 106 mask oxide film 107 sidewall spacer 108 diffusion layer 109a cobalt Film 109b Titanium nitride film 110 Cobalt silicide film (second silicide film)

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA01 BB01 BB20 BB21 CC01 CC05 DD04 DD37 DD43 DD46 DD53 DD65 DD80 DD84 EE06 EE14 EE17 FF14 GG09 HH16 5F040 DA00 DA10 DC01 EC01 EC04 EC07 EC13 EH02 FA03 FA05 FA15 FA19 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FA17 FC09 FC19

Claims (7)

[Claims] 1. A step of forming an element isolation region in a predetermined region on a surface of a silicon substrate of one conductivity type and forming a gate oxide film in an element formation region on the surface of the silicon substrate; Forming a silicon film; forming a first silicide film on the polycrystalline silicon film; forming a mask insulating film on the first silicide film;
By the etching method using the mask insulating film as a mask,
Removing unnecessary portions of the first silicide film, the polycrystalline silicon film, and the gate oxide film to form a gate electrode including a two-layer film of the polycrystalline silicon film and the first silicide film; Forming a sidewall spacer made of an insulating film on a side surface of the gate electrode without removing the mask insulating film on the electrode, and covering the periphery of the gate electrode with an insulating film; Forming a diffusion layer of a conductivity type opposite to that of the silicon substrate in a predetermined region, a step of selectively forming a metal film only on the diffusion layer, and performing a heat treatment on the metal film and the diffusion layer. A method for manufacturing a semiconductor device, comprising a step of selectively forming a second silicide film only on the diffusion layer by reacting with a surface. 2. The method according to claim 1, wherein the first silicide film is any one of titanium silicide, tungsten silicide, and tantalum silicide. 3. The method according to claim 1, wherein the metal film is made of one of cobalt (Co) and nickel (Ni). 4. The semiconductor device according to claim 1, wherein the step of selectively forming a metal film only on the diffusion layer is performed by a chemical vapor deposition method. Production method. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the step of selectively forming a metal film only on the diffusion layer is performed by an electroless plating method. . 6. The mask insulating film is a silicon oxide film,
2. The method for manufacturing a semiconductor device according to claim 1, wherein the method is either a silicon nitride film or a silicon oxynitride film. 7. A semiconductor device in which a silicide film is formed on a diffusion layer and a gate polysilicon, wherein the silicide films on the diffusion layer and the gate polysilicon have different compositions, and the silicide films have different compositions. Wherein the heat resistance of the silicide film is higher than the heat resistance of the silicide film formed on the diffusion layer.