經濟部中央標準局員工消費合作杜印製 A7 B7 五、發明説明（1 ) 本發明是有關於互補式金氧半（CMOS)電晶體積體電 路之保護電路設計，特別是有關於一種用於CMOS電晶體 積體電路中，防止内部元件之閘極氧化層受損的靜電放電 (ESD)保護電路。 由於CMOS電晶體已廣泛爲各類功能之積體電路所採 用，随著半導體製造技術之發展，積體電路内部的元件尺 寸愈縮小’尤其閘極氧化層厚變薄，致使積體電路内之 金氧半（MOS)元件對於外部靜電力作用敏感。於是，爲保 持積體電路正常運作，在電路之輪入或輸出端，特別是金 屬垫附近，便以設置靜電放電保護電路的方式，防止靜電 力進入電路内部，以避免傷害的發生。 然而根據實際半導體積體電路製造所見，不僅積體電 路，部靜電會傷害元件，在電路内部產生之靜電力亦會對 薄氧化層儿件之閘極造成損害，而影響電路的正常運作。 例如第1圖所示積體電路係由兩個獨立電路方塊1〇和2〇 所構成，一電路藉一長金屬導線】5連接，而得將訊號互相 傳遞j由於電路10和2〇受到不同電源供給，或彼此間之 運作方式頗有差異（如電路1〇是數位 電路電路H)傳輪至電路20之訊號，經由長金 可此在進入電路2〇時產生一相當大的靜電力，使電 路2〇内部的疋件受損害。此靜電力可能是相當大的正向突 皮（over shoot)或疋負向笑波⑽如卜如的），均足以侵 電路内部之薄閘氧化層元件。 另方面’根據第1圖所示之積體電路架構，由於長Du Printed A7 B7 by Employee Consumer Cooperation of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (1) The present invention relates to the design of protection circuits for complementary metal oxide semi-conductor (CMOS) bulk transistor circuits, in particular to An electrostatic discharge (ESD) protection circuit that prevents damage to the gate oxide layer of internal components in a CMOS transistor volume circuit. Since CMOS transistors have been widely used in integrated circuits of various functions, with the development of semiconductor manufacturing technology, the size of components inside the integrated circuit has become smaller and smaller, especially the thickness of the gate oxide layer has become thinner, resulting in the integrated circuit Metal oxide semi-oxide (MOS) components are sensitive to external electrostatic forces. Therefore, in order to maintain the normal operation of the integrated circuit, an electrostatic discharge protection circuit is provided at the in-circuit or output end of the circuit, especially near the metal pad, to prevent static electricity from entering the circuit to avoid injury. However, according to the actual semiconductor integrated circuit manufacturing, not only the integrated circuit, but also the static electricity will damage the components. The electrostatic force generated inside the circuit will also damage the gate of the thin oxide layer and affect the normal operation of the circuit. For example, the integrated circuit shown in Figure 1 is composed of two independent circuit blocks 10 and 20. A circuit is connected by a long metal wire [5], and the signals must be transmitted to each other. Since circuits 10 and 20 are different The power supply, or the operation mode of each other is quite different (such as the circuit 10 is a digital circuit circuit H) The signal transmitted to the circuit 20, through the long gold can generate a considerable electrostatic force when entering the circuit 20, Damage to the internal circuit 20 is damaged. This electrostatic force may be quite a positive over shoot or a negative smile wave (such as Bru), both of which are sufficient to invade the thin gate oxide components inside the circuit. On the other hand, according to the integrated circuit architecture shown in Figure 1, due to the long
2 303512 A7 B7 五、發明説明（2 ) 金屬導線15之存在，其形態類似一天線架構，可能會對其 提供訊號輪入之元件造成所謂|，電衆充電損害（plasma charging damage)"，而導致元件毀損，影響電氣特性。 由於發生在CMOS積體電路内部之靜電破壞，多爲元 件薄氧化層元件或寄生場氧化層（parasitic fieid_oxide)元件 之汲極接面崩潰(junction breakdown)而造成，即以進入元 件之過高電壓而產生。爲此，有必要在積體電路内部，採 取適當手段限制超過限度的輸入電壓値，以防止靜電力作 用在内部元件上。 本發明即針對防止CMOS電晶體積體電路内部靜電破 壞而提出’利用一靜電放電保護電路，將内部電壓控制在 合理範圍内，避免元件接面崩潰發生，而得保持元件及電 路正常運作。 經濟部中央標準局員工消費合作社印製 依照本發明一較佳實施例之靜電放電保護電路係適用 於經由一長金屬導線連通之一第一電路和一第二電路所構 成之CMOS積體電路中。此靜電保護電路含有一上突波限 制元件和一下突波限制元件。若訊號係由第一電路傳送至 第二電路，上突波限制元件即設置於第二電路前級，連接 長金屬導線和一第一電源，而下突波限制元件則在同一位 置連接長金屬導線和一第二電源。藉由上、下突波限制元 件的作用，超過限制値的訊號電壓即被限制，僅得以合理 的電壓値輸入第二電路，使其間的元件充份獲得保障。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細説明如 本紙張尺度適用中國國家標準（CNS ) 丨0X297公嫠） 經濟部中央標準局員工消費合作社印製 A7 ____B7_ 五、發明説明（3) 下： 圖式之簡單説明： 第1圖爲電路方塊圖，繪示習知CMOS積體電路中， 藉長金屬導線連接二電路方塊之架構； 第2圖爲本發明靜電放電保護電路一實施例之電路方 塊示意圖； 第3圖爲本發明靜電放電保護電路之組成與受其保護 電路示意圖； 第4圖爲第3圖電路採用MOS電晶體組成之實際電路 圖；以及 第5圖爲第3圖電路採用二極體組成之實際電路圖。 實施例 請參照第2圖所示依照本發明一較佳實施例之方塊示 意圖。本發明係適用於藉由一長金屬導線15連接之CM〇s 電路内部二獨立電路部份，包括：第一電路1〇和第二電路 20。設若訊號是自第一電路1〇送至第二電路2〇 ,則在第 二電路20前級裝設一保護電路3〇，以防止經由金屬導線 傳送之減含有正、負歧，對第二電路2Q產 影響。 保護電路30包含-上突波限制元件32和—下突波限 制元件34，如第3圖所示。上突波限制元件32連接於一 第一電源、和金屬導線15之間’遇有過高的電壓訊號(over_ =二第即予限制於合理位準。下突波限 制件3^在第二電路2G之前連接於-第二電源和全屬2 303512 A7 B7 5. Description of the invention (2) The existence of the metal wire 15 has a form similar to an antenna structure, which may cause the so-called plasma charging damage to the components that provide signal rotation. And cause damage to components and affect electrical characteristics. Due to the electrostatic damage that occurs inside the CMOS integrated circuit, it is mostly caused by the breakdown of the junction of the thin oxide layer of the device or the parasitic field oxide (parasitic fieid_oxide) device, that is, the excessive voltage entering the device And produced. For this reason, it is necessary to adopt appropriate means within the integrated circuit to limit the input voltage value that exceeds the limit to prevent electrostatic forces from acting on internal components. The present invention proposes to prevent the internal static electricity of the CMOS transistor volume circuit from being damaged. An electrostatic discharge protection circuit is used to control the internal voltage within a reasonable range to avoid the breakdown of the device interface, and the normal operation of the device and the circuit must be maintained. An ESD protection circuit printed by an employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs according to a preferred embodiment of the present invention is suitable for a CMOS integrated circuit composed of a first circuit and a second circuit connected by a long metal wire . This electrostatic protection circuit contains an upper surge limiting element and a lower surge limiting element. If the signal is transmitted from the first circuit to the second circuit, the upper surge limiting element is placed before the second circuit, connecting the long metal wire and a first power source, and the lower surge limiting element is connected to the long metal at the same position Wire and a second power supply. By the function of the upper and lower surge limiting components, the signal voltage exceeding the limit value is limited, and only a reasonable voltage value can be input into the second circuit, so that the components between them are fully protected. In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and understandable, a preferred embodiment is described below in conjunction with the attached drawings, which will be described in detail if the paper size is applicable to the Chinese National Standard (CNS) 丨 0X297 Public daughter) A7 ____B7_ printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention (3) Below: A brief description of the diagram: Figure 1 is a block diagram of the circuit, showing the conventional CMOS integrated circuit, borrowing the long The structure of connecting two circuit blocks with metal wires; FIG. 2 is a schematic diagram of a circuit block of an embodiment of the ESD protection circuit of the present invention; FIG. 3 is a schematic diagram of the composition and protection circuit of the ESD protection circuit of the present invention; FIG. 4 is The circuit in Figure 3 is an actual circuit diagram composed of MOS transistors; and Figure 5 is the actual circuit diagram in which the circuit of Figure 3 is composed of diodes. Embodiment Please refer to the block diagram shown in FIG. 2 according to a preferred embodiment of the present invention. The present invention is applicable to two independent circuit parts inside a CM〇s circuit connected by a long metal wire 15, including: a first circuit 10 and a second circuit 20. If the signal is sent from the first circuit 10 to the second circuit 20, a protection circuit 30 is installed in front of the second circuit 20 to prevent the transmission through the metal wire from containing positive and negative divergence. Circuit 2Q production impact. The protection circuit 30 includes an upper surge limiting element 32 and a lower surge limiting element 34, as shown in FIG. The upper surge limiting element 32 is connected between a first power source and the metal wire 15 'in case of an excessively high voltage signal (over_ = second, it is limited to a reasonable level. The lower surge limiting element 3 Circuit 2G was previously connected to-the second power supply and all
0 (請先閱讀背面之注意事項再填寫本頁) 裝.0 (Please read the precautions on the back before filling out this page).
、1T 經濟部中央橾準局員工消費合作社印製, Printed by 1T Employee Consumer Cooperative of the Central Department of Economic Affairs of the Ministry of Economic Affairs
五、發明説明（4 m，用以限制過大之負向突波進入第二電路2〇。 ==與第二電路20<高電㈣同等，而第二電V. Description of the invention (4 m, to limit the excessive negative surge to enter the second circuit 20. == equal to the second circuit 20 < high electricity (iv), while the second electricity
低㈣源同等，以達到眞正限制㈣ 位卓疋效果。即以一般CMOSt路爲例 而第二電源便是地端。 電原爲VDDThe low source is the same, so as to achieve the effect of restricting the position. Take the general CMOSt circuit as an example and the second power supply is the ground. Electricity is VDD
㈣：前迷裝設突波限制元件之精神，依照本發明-較 2實施例m電路㈣朴“輯示者U 做爲上突波限制元件，而以一卿s電晶體34a 做爲下犬波限制元件。PMOS電晶體32a的源接接至第一 電源y及極接至金屬導線15，其閘極則以適當之偏屢，如 以一第二電綠控制，使此電晶體沒極電壓高至一特定位準 時’才能將通道區導通。第三電源可採同等於第一電源， 以万便設計其侔局結構及電路安排。NMOS電晶雜W之 汲極接至金屬導線15，源極接至第二電源，間極亦同接至 二《，以於導線上具有過大的負向突波時，將電晶體34a 導通，使其發揮限制電壓的效果。 第4圖所;^保護電路3〇中，各電晶體的通道區寬長 比(W/L)當可依照實際需要調整，並且，其饰局型態得以配 合第一電路20 一併設計，以求發揮最大的保護效果。例 如，倘若第-電路㈣―數位電路，其供應之電源爲〜； 第一電路20是一類比電路，藉電I提供偏屢，並且，訊 號係由第-電路丨〇送至第：電路2()，則根據本發明之精 神，保護電路30係於第二電路20附近設置，並以Vdd偏 壓。再者’保護電路3G内部各電晶體寬長比可依金屬導線 本紙張尺歧财關家標準(CNS ) A7 B7 五、發明説明（5) 15之長度設計。以在區城網控制晶片中之實際運用爲例， 電晶體寬長比値對應各種不同的導線長度之關係如下表所 列： 金屬導線長度 NMOS寬長比 PMOS寬長比 500微米~1000微米 1000微米〜1500微来 1500微米〜2000微米 20/0.7(微米/微米）20/0.7(微米/微米） 40/0.7(微米/微来）40/0.7(微米/微米） 60/0.7(微米/微米）60/0.7(微米/微米） 經濟部中央標準局員工消費合作衽印製 + i U i J ’又啊汉’丨|况卜，各電晶 體需加大通道寬度，以提供更大的電流導通能力，防止更 大的突波進入第二電路20。 在另一方面，因保護電路30主要是將突波藉上下突波 限制元件吸收，使其電壓降低，則以第4圖的電路中，電 *1曰體32a和34a的沒極區是備爲極大電流通過之區域，在 電路佈局設計時，此等汲極區需與第二電路2〇内部，特別 是第一級的元件保持一定距離。如第4圖所示之緩衝器22 係第二電路20提供接受來自金屬導線15之訊號之第一級 元件，緩衝器22之閘極即需與電晶體32a和3乜的汲極區 保持-定値以上之距離(例如5微米），錢電晶體32a和 34a汲極電流侵入緩衝器22之閉極，造成損害。而爲保持 輕大的保護效果，前㈣晶體彡歧區料-級元件間之距 離亦不得太大，應在100微米之内。 則述保護電路3 〇除了可以電晶體構成，亦得採用二極 5如第5圖所不。第5圖之電路30以二極體32b和34b 别做爲上大波和下笑波限制元件。二極體32b的陽極連 (請先閲讀背面之注意事項再填寫本頁} Λ -訂 - I · I I I · 五、發明説明（6 ) 接金屬導線15，陰極同第二電路2〇接至第-電源。二接 體34b之陽極連接第二電綠，陰極則金屬導線^祕。於 疋，每有正向笑波發生，二極體32b即導通，使突波受限 制，當負笑波形成時，二杨體34b會導通，限制此突波進 入第二電路。 若訊號以另一金屬導線自第二電路20傳至第一電路 10時’在接近第-電路1G之金屬導線上亦得設置本發明 之保護電路，防止靜電力之作用，避免第—電路1Q之内部 元件受損。 本發明雖以若干較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此項技藝者，在不脱離本發明之精 神和範圍内，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 本紙張尺度i4财國國家橾準（CNS > A4聽 ( 210X297公嫠(Iv) The spirit of the front fan equipped with the surge limiting element, according to the present invention-Compared with the second embodiment, the m circuit ("Pu" editor U is used as the upper surge limiting element, and Yiqing s transistor 34a is used as the lower dog) Wave limiting element. The source of the PMOS transistor 32a is connected to the first power supply y and the electrode is connected to the metal wire 15, and the gate of the PMOS transistor 32a is appropriately biased, such as controlled by a second electric green, so that the transistor has no electrode Only when the voltage is as high as a certain level can the channel area be turned on. The third power supply can be used as the first power supply to design its local structure and circuit arrangement. The drain of the NMOS transistor W is connected to the metal wire 15 , The source is connected to the second power source, and the intermediate electrode is also connected to two ", so that when there is an excessive negative surge on the wire, the transistor 34a is turned on, so that it exerts the effect of limiting the voltage. Figure 4; ^ In the protection circuit 30, the channel area width-to-length ratio (W / L) of each transistor can be adjusted according to actual needs, and its decoration pattern can be designed together with the first circuit 20 in order to maximize the Protection effect. For example, if the first circuit-digital circuit, the power supply is ~; A circuit 20 is an analog circuit, which is supplied by I, and the signal is sent from the first circuit to the second circuit 2 (). According to the spirit of the present invention, the protection circuit 30 is connected to the second circuit 20 Set nearby and biased by Vdd. Furthermore, the width-to-length ratio of each transistor in the protection circuit 3G can be based on the metal wire, paper, and paper standard (CNS) A7 B7 5. Invention description (5) 15 length design Taking the actual application in the control chip of the district and city network as an example, the relationship between the width-to-length ratio of transistors corresponding to various wire lengths is listed in the following table: Metal wire length NMOS width-to-length ratio PMOS width-to-length ratio 500 microns to 1000 microns 1000 to 1500 micron 1500 to 2000 micron 20 / 0.7 (micron / micron) 20 / 0.7 (micron / micron) 40 / 0.7 (micron / micron) 40 / 0.7 (micron / micron) 60 / 0.7 (micron / Micron) 60 / 0.7 (micron / micron) Printed by the consumer consumption cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs + i U i J '又 啊 汉' 丨 | Condition, each transistor needs to increase the channel width to provide a larger The current conducting capability prevents larger surges from entering the second circuit 20. On the other hand, Since the protection circuit 30 mainly absorbs the surge wave by the upper and lower surge limiting elements to reduce its voltage, in the circuit of FIG. 4, the electrodeless regions of the body 32a and 34a are prepared for the passage of a maximum current In the circuit layout design, these drain regions need to keep a certain distance from the inside of the second circuit 20, especially the first-stage components. The buffer 22 shown in Figure 4 is provided by the second circuit 20 For the first-level component of the signal from the metal wire 15, the gate of the buffer 22 needs to be kept at a distance above a certain value (for example, 5 microns) from the transistors 32a and 3 to the transistors 32a and 34a. A polar current invades the closed pole of the buffer 22, causing damage. In order to maintain the great protection effect, the distance between the material and the grade components in the front and back of the crystal should not be too large, and should be within 100 microns. In addition, the protection circuit 3 can be composed of transistors, and the diode 5 has to be used as shown in FIG. 5. The circuit 30 in FIG. 5 uses diodes 32b and 34b as upper and lower wave limiting elements. Diode 32b anode connection (please read the precautions on the back before filling in this page) Λ -Subscribe- I · III · V. Description of invention (6) Connect the metal wire 15 and connect the cathode to the second circuit 20 -Power supply. The anode of the second body 34b is connected to the second electro-green, and the cathode is the metal wire. Yu Yu, whenever there is a positive laugh wave, the diode 32b is turned on, which limits the surge and acts as a negative laugh wave. When formed, the second poppet 34b will turn on, limiting this surge into the second circuit. If the signal is transmitted from the second circuit 20 to the first circuit 10 by another metal wire, it will also be on the metal wire close to the first-circuit 1G The protection circuit of the present invention may be provided to prevent the effect of electrostatic force and avoid damage to the internal components of the first circuit 1Q. Although the present invention has been disclosed above in a number of preferred embodiments, it is not intended to limit the present invention, any familiar with this The skilled person can make some changes and modifications within the spirit and scope of the present invention, so the scope of protection of the present invention shall be subject to the scope defined in the attached patent application. This paper standard i4 National Standard (CNS > A4 Listening (210 X297 Gongmai