JP3204118B2 - Internal protection circuit for CMOS integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection circuit for a complementary metal oxide semiconductor (CMOS) integrated circuit, and more particularly, to a protection circuit for a CMOS integrated circuit which prevents gate oxide damage due to electrostatic stress. It relates to an internal protection circuit.

[0002]

BACKGROUND OF THE INVENTION Traditionally, CMOS devices have become a major component of many digital and analog integrated circuits as a result of each evolving manufacturing process and its functional flexibility. As semiconductor technology continues to advance, smaller components require a reduction in the total area of CMOS integrated circuits. This reduced area of the device creates several problems that affect the performance of the CMOS circuit. For example, as the size of MOS transistors decreases, the gate oxide film is too thin to withstand high input voltages, which can cause oxide film damage. Therefore, CMOS integrated circuits are often provided with an input / output protection circuit for protecting internal elements constituting the CMOS circuit from high input voltages. This input / output protection circuit, that is, the electrostatic discharge (ESD) circuit, bypasses the high current of external signals, that is, heat flow,
The internal elements that make up the CMOS circuit are protected.

[0003]

However, the CMO
Internal signals transferred between different elements in an S integrated circuit can also be dangerous to thin oxide transistors and can damage the internal elements. For example, as shown in FIG. 5, in a CMOS integrated circuit, a first internal circuit 3 and a second internal circuit 7 are connected by a conductive line 5. The conductive line 5 has a function of transferring a signal from the first circuit 3 to the second circuit 7. The two internal circuits 3 and 7 of this CMOS integrated circuit may have different functions or may be biased by different voltage sources. If the conductive line 5 is long enough, an overshoot signal or an undershoot signal, that is, a relatively high voltage signal is present on the conductive line 5 at the input node of the second circuit 7, and The internal elements constituting the circuit 7 may be damaged.

[0004] Further, since the long conductive wire 5 can serve as an antenna, electric charges may be induced and transmitted to the second circuit 7. Due to the length of the conductive line 5, plasma charging damage may occur in the second circuit 7. Therefore, the internal elements of the second circuit 7 may be damaged,
It may affect the performance of the CMOS integrated circuit.

The majority of such internal device damage is electrostatic damage caused by drain junction breakdown of thin oxide devices or parasitic field oxide.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problem, in which an input signal level to an internal element of a second circuit on the input side between first and second circuits constituting a CMOS integrated circuit is provided. It is an object of the present invention to provide an internal protection circuit of a CMOS integrated circuit that can protect the internal element from electrostatic damage by restricting the above.

[0007]

An internal protection circuit for a CMOS integrated circuit according to the present invention is a CMOS integrated circuit having a first circuit, a second circuit, and a conductive line connecting between the two circuits, wherein the circuit is provided on the conductive line. In a CMOS integrated circuit internal protection circuit for protecting the second circuit from a transferred signal, a first voltage source is connected between the first voltage source and a conductive line, and transmitted on the conductive line. A first clamp element for clamping an overshoot signal to be applied, a second voltage source, and a clamp between the second voltage source and the conductive line for clamping an undershoot signal transmitted on the conductive line. A first clamp element and a second clamp element.
Are connected in close proximity to the second circuit side.

Although the voltage level of an input signal to an internal element in the second circuit may be higher than the breakdown voltage of the internal element, in the present invention, an overshoot signal transmitted on a conductive line is generated. Since the first clamp element clamps and the undershoot signal transmitted on the conductive line is clamped by the second clamp element, the second element is protected so as to protect the internal elements from possible electrostatic damage at this time.
The input signal level to the internal element of the circuit is limited, and the internal element can be protected from electrostatic damage.
Further, since the internal protection circuit is connected close to the second circuit side, better protection of the second circuit is obtained.

More preferably, the length of the conductive line between the first and second clamp elements and the second circuit is in the range of 5 μm to 100 μm.

According to this configuration, a preferable distance between the internal protection circuit and the second circuit is within 100 μm, and
Since the drain regions bypass high electrostatic currents when the clamp elements are transistors, these regions should be maintained at a certain distance of at least 5 μm from the input gate of the internal device in the second circuit. .

Still preferably, in a CMOS integrated circuit according to the present invention, the first clamp element includes an anode connected to the conductive line, and a first clamp element.
A diode having a cathode connected to the second voltage source, and a diode having a second clamp element having an anode connected to the second voltage source, and a cathode connected to the conductive line. Is characterized by being at least one of the following. That is, preferably, the first clamp element in the internal protection circuit of the CMOS integrated circuit of the present invention is a diode having an anode connected to the conductive line and a cathode connected to the first voltage source. is there. Preferably, the second clamp element in the internal protection circuit of the CMOS integrated circuit of the present invention is a diode having an anode connected to the second voltage source and a cathode connected to the conductive line. is there. Further, preferably,
The first embodiment of the internal protection circuit of the CMOS integrated circuit according to the present invention
An anode connected to the conductive line,
And a diode having a cathode connected to the first voltage source, wherein the second clamp element has an anode connected to the second voltage source, and a cathode connected to the conductive line. It is.

Preferably, in the internal protection circuit for a CMOS integrated circuit according to the present invention, the first clamp element comprises:
A P electrode having a source electrode connected to the first voltage source, a gate electrode connected to the first or third voltage source, and a drain electrode connected to the conductive line;
A MOS transistor, and the second clamp element is an NMOS transistor having a drain electrode connected to the conductive line and a gate electrode and a source electrode connected to the second voltage source. And at least one of them. That is, preferably, in the internal protection circuit of the CMOS integrated circuit of the present invention, the first clamp element is connected to a source electrode connected to the first voltage source and to the first voltage source or the third voltage source. And a drain electrode connected to the conductive line. Preferably, in the internal protection circuit of the CMOS integrated circuit according to the present invention, the second clamp element includes a drain electrode connected to the conductive line, a gate electrode and a source electrode connected to the second voltage source. NMOS with
It is a transistor. Further, preferably, the C of the present invention
In an internal protection circuit of a MOS integrated circuit, a first clamp element includes a source electrode connected to a first voltage source, a gate electrode connected to a first voltage source or a third voltage source, A PMOS transistor having a drain electrode connected to the conductive line, wherein the second clamp element includes a drain electrode connected to the conductive line;
An NMOS transistor having a gate electrode and a source electrode connected to the second voltage source.

According to the above configuration, a transistor and a clamp diode can be used as the first clamp element and the second clamp element, and can be easily configured.

Further, in the internal protection circuit of the CMOS integrated circuit according to the present invention, the second circuit includes the first voltage source and the second voltage source.
Is preferably connected between the power supply and the voltage source. Preferably, the second voltage source is grounded.

[0015]

Embodiments of the present invention will be described with reference to the drawings. In this embodiment, an internal protection circuit between two internal circuits will be described for the sake of simplicity. However, the internal protection circuit of the present invention is not limited to this embodiment, It can be applied to any CMOS integrated circuit composed of internal circuit modules.

FIG. 1 is a block diagram showing a main configuration of a CMOS integrated circuit including an internal protection circuit according to one embodiment of the present invention.

Referring to FIG. 1, a CMOS integrated circuit according to the present embodiment has a first circuit 10 and a second circuit 10 which are internal circuits thereof.
, A conductive line 15 connecting the first circuit 10 and the second circuit 20 and transferring a signal from the first circuit 10 to the second circuit 20, and a conductive line 15 transferred on the conductive line 15 An internal protection circuit 30 that protects the second circuit 20 from electrostatic damage by limiting the signal level of the second circuit 20. These first circuit 10 and second circuit 20 may be any of a digital circuit and an analog circuit. Also, the first circuit 10 and the second circuit 2
0 is supplied with a different voltage or the same voltage.
Further, when a signal is transferred from the first circuit 10 to the second circuit 20 through the conductive line 15, the internal protection circuit 30
What is necessary is just to connect and arrange | position to the conductive line 15 in front of the 2nd circuit 20 so that internal electrostatic stress may be prevented. Conversely, as shown by the dotted line in FIG. 1, when a signal is transferred from the second circuit 20 to the first circuit 10 through the conductive line 15 ', the signal is separately transferred to the conductive line 15' in front of the first circuit 10. May be connected and disposed.

FIG. 2 is a block diagram showing a circuit configuration of the internal protection circuit 30 of FIG.

As shown in FIG. 2, in the internal protection circuit 30, a first clamp element 32 is connected to a first voltage source 35 connected to the second circuit 20 and applying a predetermined voltage to a conductive line. 15 to limit the predetermined positive voltage level of the input signal to the second circuit 20. A second clamp element 34 is connected between a second voltage source (shown here as ground) 36 and the conductive line 15 to provide a negative voltage for the input signal to the second circuit 20. Limit levels. Therefore, the first clamp element 32 protects the second circuit 20 from an overshoot signal, and the second clamp circuit 34 protects the second circuit 20 from an undershoot signal. In the case of the CMOS integrated circuit of the present embodiment, the first voltage source 35 is at V _DD and the second voltage source 36 is at ground. The first clamp element 32 and the second clamp element 34 may be any electronic components capable of limiting an input signal to a predetermined voltage level, and a transistor or a clamp diode may be used as a clamp element. Can be. FIG. 3 shows a case where transistors are used as the clamp elements 32 and 34.

FIG. 3 shows that the clamp elements 32 and 34 of FIG.
FIG. 3 is a circuit diagram showing an example of a circuit configuration in the case of a MOS transistor.

In FIG. 3, the first clamp element 32
Is a PMOS transistor 32a, and the second clamp element 34 is an NMOS transistor 34a. PMOS transistor 32a as first clamp element 32
Is connected between the first voltage source (V _DD ) 35a and the conductive line 15. That is, the PMOS transistor 32
The source of a is connected to a first voltage source (V _DD ) 35a, its gate is connected to a third voltage source, and its drain is connected to the conductive line 15. In a simplified arrangement and circuit design, its gate could be directly connected to the first voltage source 35a. Also, the second clamp element 3
4 is connected to the conductive line 15.
And the ground as the second voltage source 36a. That is, the drain of the NMOS transistor 34a is connected to the conductive line 15, and its gate and source are grounded.

When the input signal to the second circuit 20 has a voltage level lower than a predetermined value, the PMOS transistor 32a and the NMOS transistor 34a of the internal protection circuit 30 are off. However, if the voltage level of the input signal on the conductive line 15 becomes higher than a predetermined value,
The PMOS transistor 32a conducts and limits the input signal voltage to a predetermined voltage. This predetermined voltage is the sum of the voltage from the first voltage source 35a and the threshold voltage of the PMOS transistor 32a. On the other hand, the voltage on the conductive line 15 is equal to the ground voltage as the voltage of the second voltage source 36a and N.
If the difference is smaller than the threshold voltage of the MOS transistor 34a, the NMOS transistor 34a conducts and limits the input signal voltage to a predetermined voltage.

The above protection occurs when the integrated circuit is operating normally, that is, when the power supply is applying an appropriate voltage to the integrated circuit. However, electrostatic discharge
It often occurs during the manufacture and transportation of unpowered integrated circuits. In this case, the transistor 32a or 3
A current is emitted by the connection breakdown of 4a. That is,
Even if no power supply voltage is applied to the integrated circuit and the transistor is not forward biased, the internal circuit is not subject to electrostatic damage, since the electrostatic current is still emitted by the junction breakdown of the transistor.

The internal protection circuit 30 includes a second circuit 20
Should be taken into account when designing the layout. The channel width / length ratio of PMOS transistor 32a and NMOS transistor 34a can be optimized according to the length of conductive line 15 and the arrangement of second circuit 20. Table 1 below shows the preferred width (W) / length (L) ratio of the transistor for different lengths of the conductive line 15.

[0025]

[Table 1]

The internal protection circuit 30 provides better protection of the second circuit 20 when close to the second circuit 20. The preferred distance between the protection circuit 30 and the second circuit 20 is within 100 μm. However, since the drain regions of PMOS transistor 32a and NMOS transistor 34a bypass high electrostatic currents, these regions should be maintained at some predetermined distance from the input gates of internal elements in second circuit 20. is there. For example, referring to FIG. 3, preferably, the input gate of the first stage input buffer 22, which is an internal element in the second circuit 20, is 5 μm away from the drain regions of the PMOS transistor 32a and the NMOS transistor 34a.

Next, FIG. 4 shows a case where diodes are used as the clamp elements 32 and 34 in FIG.

FIG. 4 is a circuit diagram showing an example of a circuit configuration when the clamp elements 32 and 34 in FIG. 2 are diodes.

In FIG. 4, the first clamp element 32 is a diode 32b. The anode of the diode 32b is connected to the conductive line 15, and the cathode of the diode 32b is connected to the first voltage source 35b. Similarly, the second clamp element 34 is connected to another diode 34.
b. The anode of this other diode 34b is the second
And another diode 34b
Are connected to the conductive line 15. Conductive wire 15
When the upper signal voltage is higher than the voltage of the first voltage source 35b, the diode 32b serving as the first clamp element 32 conducts so as to limit the voltage on the conductive line 15 to a predetermined voltage, and Of the circuit 20 is prevented from being damaged by the overshoot signal voltage. On the other hand, the conductive wire 15
When the upper signal voltage is lower than the voltage of the second voltage source 36b, the diode 34b serving as the second clamp element 34 conducts so as to limit the voltage on the conductive line 15 to a predetermined voltage, and The internal elements of the circuit 20 are prevented from being damaged by the undershoot signal voltage.

If no power supply is present, the diode 3
2b and 34b emit electrostatic current due to junction breakdown. This operation is different from the operation of the conventional clamp circuit.

As described above, the CMOS integrated circuit of the present invention includes the first circuit 10, the second circuit 20, and the conductive line 15 for transferring a signal from the first circuit 10 to the second circuit 20.
And an internal protection circuit 30 for protecting the second circuit 20 from a signal voltage connected to the conductive line 15 and transferred on the conductive line 15. The internal protection circuit 30 has a first clamp element 32 and a second clamp element 34 and can be attached to any long conductive line 15 between internal circuit modules of a CMOS integrated circuit. Also,
The internal protection circuit 30 is provided at a stage before a circuit module to be protected, and is preferably disposed close to the circuit module. That is, the first clamp element 32 is close to the second circuit 20 and is connected between the first voltage source 35 and the conductive line 15 to clamp an overshoot signal. Further, the second clamp element 34 is close to the second circuit 20 and is connected between the second voltage source 36 and the conductive line 15 to clamp an undershoot signal. In these internal protection circuits 30, the clamp elements 32, 34
, The input signal voltage to the internal element is limited to a predetermined voltage corresponding to the first and second voltage sources 35 and 36, and the second circuit 2
0 protects internal elements from electrostatic damage.

Therefore, the clamp elements 32 and 34 of the internal protection circuit 30 reduce the amplitude of the input signal voltage to the first and second levels.
Of the present invention can be limited to a voltage range corresponding to the voltages of the voltage sources 35 and 36, thereby protecting the internal elements of the second circuit 20 from electrostatic damage. It can be operated without being affected by stress.

In the above embodiment, the second circuit 20
Although the voltage source 35 connected to and applying a predetermined voltage is used as the first voltage source, a separate and independent voltage source may be used as the first voltage source. Also, as for the second voltage source, similarly to the first voltage source, a separate and independent voltage source may be used as the second voltage source. As described above, when the first and second voltage sources are separately and independently provided, the voltages of these voltage sources can be arbitrarily set regardless of the voltage applied to the second circuit 20. .

[0034]

As described above, according to the present invention, the CMOS
An overshoot signal transmitted on a conductive line between the first and second circuits in an integrated circuit is clamped by a first clamp element, and an undershoot signal transmitted on a conductive line is transmitted to a second clamp circuit. To clamp with the clamp element,
The input signal level to the internal element of the second circuit can be limited so as to protect the internal element from electrostatic damage that may occur at this time, and the internal element can be protected from electrostatic damage. Moreover, since the internal protection circuit is connected close to the second circuit side, better protection of the second circuit can be obtained.

At this time, better protection can be obtained by setting the more preferable distance between the internal protection circuit and the second circuit to within 5 μm to 100 μm.

Further, a transistor, a clamp diode, or the like can be used as the first and second clamp elements. In this case, a simple configuration can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main configuration of a CMOS integrated circuit including an internal protection circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a circuit configuration example of an internal protection circuit of FIG. 1;

FIG. 3 is a circuit diagram showing an example of a circuit configuration when the clamp element in FIG. 2 is a MOS transistor.

FIG. 4 is a circuit diagram showing an example of a circuit configuration when the clamp element of FIG. 2 is a diode.

FIG. 5 is a block diagram showing a configuration of an internal circuit of a conventional CMOS integrated circuit.

[Explanation of symbols]

 Reference Signs List 10 first circuit 15 conductive line 20 second circuit 30 protection circuit 32 first clamp element 32a PMOS transistor 34a NMOS transistor 32b, 34b diode 34 second clamp element 35, 35a, 35b first voltage source 36, 36a, 36b Second voltage source

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/822 H01L 21/8234-21/8238 H01L 27/04 H01L 27/08-27/092

Claims (6)

(57) [Claims] 1. A first circuit , a second circuit, and a circuit between both circuits.
Within the protection circuit of the CMOS integrated circuit for protecting the second circuit from a signal transferred over the conductive wire a CMOS integrated circuit having a conductive wire for connecting a first voltage source, said first voltage A first clamp element that is connected between the power supply and the conductive line and clamps an overshoot signal transmitted on the conductive line; a second voltage source; and between the second voltage source and the conductive line. And a second clamp element for clamping an undershoot signal transmitted on the conductive line .
The first clamp element and the second clamp element are connected to the second clamp element.
Characterized by being connected close to the circuit side of
Internal protection circuit for MOS integrated circuits. 2. The conductive line between the first and second clamp elements and the second circuit has a length of 5 μm to 100 μm.
CM of claim 1 Symbol mounting, characterized in that m is in the range of
Internal protection circuit of OS integrated circuit. 3. The first clamp element is a diode having an anode connected to the conductive line and a cathode connected to the first voltage source, and the second clamp element. but the second anode is connected to a voltage source, and according to claim 1 or 2, wherein the said at least one of that a diode having a cathode connected to the conductor line Internal protection circuit for CMOS integrated circuit. A first electrode connected to the first voltage source; a gate electrode connected to the first voltage source or a third voltage source; PM having a drain electrode connected to a conductive line
An OS transistor, and the second clamp element is an NMOS transistor having a drain electrode connected to the conductive line, and a gate electrode and a source electrode connected to the second voltage source. 3. The internal protection circuit of a CMOS integrated circuit according to claim 1, wherein the internal protection circuit is at least one of the following. 5. The internal protection of a CMOS integrated circuit of claim 1, wherein said second circuit is connected between said second voltage source and the first voltage source circuit. 6. The CMOS according to claim 1 , wherein said second voltage source is grounded.
Internal protection circuit for integrated circuits.