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Insulated Gate Type Field-Effect Transistor
(AREA)
Abstract
A process of forming split polysi-gate MOS structure comprises the steps of: forming one photoresist layer on silicon usbstrate with one gate oxide and one poly-1; definning one isolation trench pattern by lithography, and according to the isolation trench pattern ethcing until partial region of the silicon substrate to form one isolation trench; removing the photoresist layer left by etching step, to expose the poly-1 as one split polysi-gate; forming one oxide-1 on the split polysi-gate and in the isolation trench; forming one insulator on the oxide-1, and filling up the isolation trench; forming one oxide-2 on the insulator; ethcing back the oxide-2, and removing the insulator above the split polysi-gate and the oxide-1; and forming one poly-2 on split polysi-gate with planarization effect and the isolatin trench.
TW84104683A1995-05-111995-05-11Process for forming split polysi-gate MOS structure
TW265469B
(en)
A method for isolating an active region of an MOS semiconductor device using a planarized refill layer which is not substantially overpolished and an MOS device fabricated thereby