TW368736B - Manufacturing method for multiple surface short insulated gate bipolar transistor - Google Patents

Manufacturing method for multiple surface short insulated gate bipolar transistor

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Publication number
TW368736B
TW368736B TW085111613A TW85111613A TW368736B TW 368736 B TW368736 B TW 368736B TW 085111613 A TW085111613 A TW 085111613A TW 85111613 A TW85111613 A TW 85111613A TW 368736 B TW368736 B TW 368736B
Authority
TW
Taiwan
Prior art keywords
etching
photolithography
oxide
chip
forming
Prior art date
Application number
TW085111613A
Other languages
Chinese (zh)
Inventor
Ruei-Ling Lin
Ching-Hsiang Hsu
Yu-Ping Ju
Chia-Jung Chang
Original Assignee
Nat Science Council
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nat Science Council filed Critical Nat Science Council
Priority to TW085111613A priority Critical patent/TW368736B/en
Application granted granted Critical
Publication of TW368736B publication Critical patent/TW368736B/en

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A kind of manufacturing method for multiple surface short insulated gate bipolar transistor which is to form an epitaxy silicon layer on the surface of substrate; then, forming a first oxide on the epitaxy silicon layer and employing photolithography and etching to define a plurality of P-well predetermined region; then, proceeding ion implantation and forming a plurality of P-well in a plurality of P-well predetermined region; then, forming a second oxide on the chip and defining the active region by photolithography and etching; sequentially depositing a gate oxide and a polycide on the surface of active region and defining polycide layer by the photolithography and etching and forming the gate of transistor component; proceeding ion implantation to form a channel region; proceeding ion implantation to form a plurality of buried emitter lines in the channel region; coating a photoresistant on the chip and employing photolithography for defining a plurality of spaced implantation contact; employing the photoresistant as the mask for ion implantation to form the N+/P+ crossed diffusion region, and removing the photoresistant; then, depositing a third oxide on the chip and employing photolithography and etching to define the third oxide and form a plurality of contacts; lastly, depositing a metal aluminum layer on the front and back face of the chip and employing photolithography and etching to define the front metal aluminum layer and form the metal interconnect.
TW085111613A 1996-09-23 1996-09-23 Manufacturing method for multiple surface short insulated gate bipolar transistor TW368736B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW085111613A TW368736B (en) 1996-09-23 1996-09-23 Manufacturing method for multiple surface short insulated gate bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW085111613A TW368736B (en) 1996-09-23 1996-09-23 Manufacturing method for multiple surface short insulated gate bipolar transistor

Publications (1)

Publication Number Publication Date
TW368736B true TW368736B (en) 1999-09-01

Family

ID=57941364

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085111613A TW368736B (en) 1996-09-23 1996-09-23 Manufacturing method for multiple surface short insulated gate bipolar transistor

Country Status (1)

Country Link
TW (1) TW368736B (en)

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees