JPH10229174A
(ja)
*
|
1997-02-18 |
1998-08-25 |
Mitsubishi Electric Corp |
半導体記憶装置の製造方法
|
US6297644B1
(en)
|
1999-03-04 |
2001-10-02 |
Advanced Micro Devices, Inc. |
Multipurpose defect test structure with switchable voltage contrast capability and method of use
|
US6294397B1
(en)
*
|
1999-03-04 |
2001-09-25 |
Advanced Micro Devices, Inc. |
Drop-in test structure and abbreviated integrated circuit process flow for characterizing production integrated circuit process flow, topography, and equipment
|
US6452412B1
(en)
|
1999-03-04 |
2002-09-17 |
Advanced Micro Devices, Inc. |
Drop-in test structure and methodology for characterizing an integrated circuit process flow and topography
|
US6268717B1
(en)
|
1999-03-04 |
2001-07-31 |
Advanced Micro Devices, Inc. |
Semiconductor test structure with intentional partial defects and method of use
|
US6258437B1
(en)
|
1999-03-31 |
2001-07-10 |
Advanced Micro Devices, Inc. |
Test structure and methodology for characterizing etching in an integrated circuit fabrication process
|
US6429452B1
(en)
|
1999-08-17 |
2002-08-06 |
Advanced Micro Devices, Inc. |
Test structure and methodology for characterizing ion implantation in an integrated circuit fabrication process
|
US6740555B1
(en)
|
1999-09-29 |
2004-05-25 |
Infineon Technologies Ag |
Semiconductor structures and manufacturing methods
|
US6434503B1
(en)
|
1999-12-30 |
2002-08-13 |
Infineon Technologies Richmond, Lp |
Automated creation of specific test programs from complex test programs
|
DE10010821A1
(de)
*
|
2000-02-29 |
2001-09-13 |
Infineon Technologies Ag |
Verfahren zur Erhöhung der Kapazität in einem Speichergraben und Grabenkondensator mit erhöhter Kapazität
|
US6617180B1
(en)
|
2001-04-16 |
2003-09-09 |
Taiwan Semiconductor Manufacturing Company |
Test structure for detecting bridging of DRAM capacitors
|
JP3875047B2
(ja)
*
|
2001-06-22 |
2007-01-31 |
シャープ株式会社 |
半導体基板の面方位依存性評価方法及びそれを用いた半導体装置
|
US6576487B1
(en)
|
2002-04-19 |
2003-06-10 |
Advanced Micro Devices, Inc. |
Method to distinguish an STI outer edge current component with an STI normal current component
|
TW556303B
(en)
*
|
2002-10-25 |
2003-10-01 |
Nanya Technology Corp |
Test key of detecting whether the overlay of active area and memory cell structure of DRAM with vertical transistors is normal and test method of the same
|
US20060009011A1
(en)
*
|
2004-07-06 |
2006-01-12 |
Gary Barrett |
Method for recycling/reclaiming a monitor wafer
|
JP2008508716A
(ja)
*
|
2004-07-30 |
2008-03-21 |
アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド |
半導体デバイスの技術分野において局所的電気的特徴を評価するための技術
|
DE102004036971B4
(de)
*
|
2004-07-30 |
2009-07-30 |
Advanced Micro Devices, Inc., Sunnyvale |
Technik zur Bewertung lokaler elektrischer Eigenschaften in Halbleiterbauelementen
|
US8061224B2
(en)
*
|
2008-05-06 |
2011-11-22 |
Globalfoundries Singapore Pte. Ltd. |
Method for performing a shelf lifetime acceleration test
|
DE102010026351B4
(de)
*
|
2010-07-07 |
2012-04-26 |
Siltronic Ag |
Verfahren und Vorrichtung zur Untersuchung einer Halbleiterscheibe
|
US8716037B2
(en)
|
2010-12-14 |
2014-05-06 |
International Business Machines Corporation |
Measurement of CMOS device channel strain by X-ray diffraction
|
KR102046761B1
(ko)
|
2013-01-14 |
2019-12-02 |
삼성전자 주식회사 |
비휘발성 메모리 장치
|
US9799575B2
(en)
|
2015-12-16 |
2017-10-24 |
Pdf Solutions, Inc. |
Integrated circuit containing DOEs of NCEM-enabled fill cells
|
US9805994B1
(en)
|
2015-02-03 |
2017-10-31 |
Pdf Solutions, Inc. |
Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads
|
US10199283B1
(en)
|
2015-02-03 |
2019-02-05 |
Pdf Solutions, Inc. |
Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage
|
US10978438B1
(en)
|
2015-12-16 |
2021-04-13 |
Pdf Solutions, Inc. |
IC with test structures and E-beam pads embedded within a contiguous standard cell area
|
US10593604B1
(en)
|
2015-12-16 |
2020-03-17 |
Pdf Solutions, Inc. |
Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells
|
US9929063B1
(en)
|
2016-04-04 |
2018-03-27 |
Pdf Solutions, Inc. |
Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
|
US9653446B1
(en)
|
2016-04-04 |
2017-05-16 |
Pdf Solutions, Inc. |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and AA-short-configured, NCEM-enabled fill cells
|
US9905553B1
(en)
|
2016-04-04 |
2018-02-27 |
Pdf Solutions, Inc. |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells
|
US9748153B1
(en)
|
2017-03-29 |
2017-08-29 |
Pdf Solutions, Inc. |
Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configure
|
US9773774B1
(en)
|
2017-03-30 |
2017-09-26 |
Pdf Solutions, Inc. |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells
|
US9786649B1
(en)
|
2017-06-27 |
2017-10-10 |
Pdf Solutions, Inc. |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells
|
US9768083B1
(en)
|
2017-06-27 |
2017-09-19 |
Pdf Solutions, Inc. |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells
|
US10096530B1
(en)
|
2017-06-28 |
2018-10-09 |
Pdf Solutions, Inc. |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells
|
US9865583B1
(en)
|
2017-06-28 |
2018-01-09 |
Pdf Solutions, Inc. |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including stitch open configured fill cells
|
CN113311309B
(zh)
*
|
2021-07-30 |
2021-10-12 |
度亘激光技术(苏州)有限公司 |
半导体结构的覆盖层剥除方法及半导体结构失效分析方法
|