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Application filed by United Microelectronics CorpfiledCriticalUnited Microelectronics Corp
Priority to TW82109082ApriorityCriticalpatent/TW248606B/en
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Publication of TW248606BpublicationCriticalpatent/TW248606B/en
Insulated Gate Type Field-Effect Transistor
(AREA)
Abstract
A local anti-punchthrough implanting device structure which could lower junction capacitance of source/drain and raise device effective mobility includes the steps: - depositing a Si3N4 layer with proper thickness on gate oxide of Si substrate; - implementing Si3N4 mask/etching to form one indentation; - depositing on indentation position/etching-back to form spacer so that implanting opening with narrow width is formed between spacers; - implanting ion with opposed polarity into the opening to form punchthrough stop with width close to that of the opening(the width L2 of this area less than L1+L2 in Fig. 2F); - depositing poly silicon and implanting or doping dopant with high density, and with planar etching-back process forming gate area with low resistance feature; - removing Si3N4 layer, then implanting source/drain with low density, depositing/etching-back gate to form oxide spacer and implanting source/drain with high density.