TW247370B - - Google Patents

Info

Publication number
TW247370B
TW247370B TW082109364A TW82109364A TW247370B TW 247370 B TW247370 B TW 247370B TW 082109364 A TW082109364 A TW 082109364A TW 82109364 A TW82109364 A TW 82109364A TW 247370 B TW247370 B TW 247370B
Authority
TW
Taiwan
Application number
TW082109364A
Other languages
Chinese (zh)
Original Assignee
At & T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by At & T Corp filed Critical At & T Corp
Application granted granted Critical
Publication of TW247370B publication Critical patent/TW247370B/zh

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/081Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/081Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/092Manufacture or treatment of dielectric parts thereof by smoothing the dielectric parts
TW082109364A 1992-11-12 1993-11-06 TW247370B (https=)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/975,235 US5268332A (en) 1992-11-12 1992-11-12 Method of integrated circuit fabrication having planarized dielectrics

Publications (1)

Publication Number Publication Date
TW247370B true TW247370B (https=) 1995-05-11

Family

ID=25522812

Family Applications (1)

Application Number Title Priority Date Filing Date
TW082109364A TW247370B (https=) 1992-11-12 1993-11-06

Country Status (5)

Country Link
US (1) US5268332A (https=)
EP (1) EP0597634A3 (https=)
JP (1) JPH06224188A (https=)
KR (1) KR100276146B1 (https=)
TW (1) TW247370B (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2926864B2 (ja) * 1990-04-12 1999-07-28 ソニー株式会社 銅系金属膜のエッチング方法
US6297110B1 (en) 1994-07-29 2001-10-02 Stmicroelectronics, Inc. Method of forming a contact in an integrated circuit
IL122484A0 (en) 1995-06-07 1998-06-15 Noven Pharma Transdermal compositions containing low molecular weight drugs which are liquid at room temperatures
CN102157437B (zh) * 2010-02-11 2013-12-25 中国科学院微电子研究所 半导体结构的形成方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4708770A (en) * 1986-06-19 1987-11-24 Lsi Logic Corporation Planarized process for forming vias in silicon wafers
DE3686721D1 (de) * 1986-10-08 1992-10-15 Ibm Verfahren zur herstellung einer kontaktoeffnung mit gewuenschter schraege in einer zusammengesetzten schicht, die mit photoresist maskiert ist.
US5022958A (en) * 1990-06-27 1991-06-11 At&T Bell Laboratories Method of etching for integrated circuits with planarized dielectric

Also Published As

Publication number Publication date
EP0597634A2 (en) 1994-05-18
JPH06224188A (ja) 1994-08-12
EP0597634A3 (en) 1994-08-24
US5268332A (en) 1993-12-07
KR100276146B1 (ko) 2001-01-15
KR940012505A (ko) 1994-06-23

Similar Documents

Publication Publication Date Title
TW266147B (https=)
DK0551248T3 (https=)
KR100300681B1 (https=)
BR9304651A (https=)
TW224108B (https=)
TW276250B (https=)
BR9207065A (https=)
DK0553681T3 (https=)
TW223081B (https=)
TW247370B (https=)
DK0571172T3 (https=)
FR2691541B1 (https=)
DE9209779U1 (https=)
IN181027B (https=)
IN179272B (https=)
BRPI9204323A2 (https=)
IN180830B (https=)
IN180801B (https=)
IN180790B (https=)
IN180768B (https=)
IN180676B (https=)
IN178317B (https=)
CN3012425S (https=)
AU2065592A (https=)
AU2061492A (https=)

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent