03149 Λ 6 Β6 經濟部中央標準局员工消費合作社印製 五、發明説明（I ) (一） 發明背景 製作一個投射式液晶顯示器時，由於光學条統的要求，顯示畫面的尺 寸通常被限制在對角線3吋上，其中畫素的數目也許是640X480，其至到 1000 X 1000;畫素的尺寸亦小至95X95 wm，甚至是70X40 Wm。如此一 來，自畫素平行拉出的訊號端，其間距就會急劇的縮小，因此以目前的組 裝技術，如捲帶式自動接合技術（Tape Automatic Bonding ; TAB)，無法 將驅動IC與畫素訊號端相接。 為了解決這個問題，有一種方法是直接將驅動1C以薄膜電晶髏技術來 設計，直接製作在奎素所在的同一基體上。目前一般常用的有複晶矽薄膜 電晶體製程，這是因為複晶矽的電荷移動率較高，元件的尺寸因此可以縮 小，足以滿足投射式薄膜電晶髏液晶顯示器上，開口率（aperture ratio) 要高的要求。 在驅動1C中最重要的組件為移位暫存器，其中需包括數個反相器。在 已知的複晶矽薄膜電晶體製程中，反相器大多採用如圖1所示互補式金氣 半薄膜電晶體（CM0SFET)的結構。它包括了兩個汲極、兩個源極，缺點即 所佔面積很大。 (二） 發明的簡要說明 本發明提出一種複晶矽反相器的積體電路，是由一個薄膜電晶體和一 値具控制閘的PIN薄膜二極髏所組成。具有製程簡易、面積小、消耗電流 低的優點。其製作方法為：在絕緣基髏上沈積未經摻雜的第一層複晶矽， 在其上並形成一絕緣層，然後沈積第二層複晶矽，植入適當的導性離子使 具有導電性；製定此第二層複晶矽的圖形，提供薄膜電晶髏的閘極和PIN 薄膜二極體的控制閘極。分別在薄膜電晶體閘極兩旁植入N形（或P型）離子 ，作為源/汲極區域，然後在PIN控制閘極的另一側植入P型（或N型）離 子，隨即沈積絕緣層，挖開接觸窗，並沈積金屬形成電性連接後’即完成 本發明之複晶矽薄膜反相器。 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度返用中國B家標準(CNS) T4規格(210x297公龙) k,03149 Λ 6 B6 經濟部中央標準局员工消費合作社印製 五、發明説明（2) (三） 圖示的簡要說明 圖1為習知技蓊之佈局圖。 圖2為本發明之第一個實施例及其等效電路，包括一値Ν型TFT及PIN 薄膜二極體。 圖3為本發明之第二値實施例。 圖4為本發明之第三個實施例。 圖5為本發明之第四個實施例。 圖6到圖8為本發明之薄膜反相器製作過程的剖面圖。 圖9為本發明之薄膜反相器之佈局圖。 (四） 工作原理 首先請參考圖2到，以第一値實施例來說明本發明之反相器的工作原 理。画2為本發明的第一値實施例，由一個N型TFT(Dl)及一値具控制閘的 PIN薄膜二極髖（D2)所構成，其等效電路則為一個N型TFT(El)，一値PIN薄 膜二極體（E2)及一値P型寄生TFT(E3)所構成。當V ϊ n =0V，E1為ON狀態 ，E3為OFF狀態，因此V。u τ =VD D =-15\/。當V ϊ N =-15V，E1 為OFF 狀態，E3為ON狀態，E2為順向偏壓，所以Vo υ τ = ν i> = 0V。 圖3為本發明之第二値實施例，與圖2本發明之第一値實施例相同， 均由一値N型薄膜電晶髏及PIN薄膜二極髏，但是其N型TFT和PIN薄膜二極 體的閘極分開，分別接至V X N和\/D D。 接著參考圖4，本發明的第三値實施例由一値P型TFT(Dl)及一個具控 制閘的PIN薄膜二極髏（D2)所構成，其等效電路則為一値P型TFT(El)，一 値PIN薄膜二極體（E2)及一個N型寄生TFT(E3)所構成。當V r μ =15V，E1 為OFF狀態，E3為ON狀態，因此Vo υ τ =\/G N D = 0\/。當V z N =0V， El為ON狀態，E2為順向偏壓，E3則為OFF狀態，所以l/〇 u τ =15\/。 圖5為本發明之第四個實施例，與圖5本發明之第二値實施例相同， (請先閱讀背面之注意事項再塡寫本頁) 裝< 訂_ 線- 本紙張尺度遑用中B β家標準(CNS)甲4規格(210X297公;¢) 03149 Λ 6 Β6 經濟部中央搮準局员工消費合作社印製 五、發明説明（3) 均由一個Ρ型薄膜電晶髁及PIN薄膜二極醱，但是其Ρ型TFT和PIN薄膜二極 體的閘極分開，分別接至V ϊ N和VD D。 (五）製作方法 第一個實施例是由一個N型薄膜電晶體和一個具控制閘的PIN薄膜二極 體所構成的複晶矽薄膜反相器，其製作方法如下。如圖6所示，先在N型 的矽晶H(l)上利用熱氣化長出約700-900nm的氣化物層（2)，然後在其上 利用低壓化學汽相沈積法（LPCVD)沈積第一層複晶矽（3)，溫度約在550〜 650t：之間，厚度約在100到300nm。在製定其圖形後，利用熱氧化再長成 一絕緣層（4)，約50到150 nm厚。接著沈積第二層複晶矽，厚約300到 500nm，並且用P0C13離子擴散技術予以摻雜，溫度在900到1000Ϊ：之間， 濃度是1015〜1017atoms/cm3，並製定其圖形，産生作為薄膜電晶體的閘 極（52)及作為PIN二極體之控制閘（51)。 隨之如圖6所示進行離子植入的步驟。此時即利用製定後之第二層複 晶矽（51)，（52)作為自動對準用的光軍，同時也利用光軍（6)將欲作為P型 區域的部分遮蓋往後，植入P離子，濃度約在1X1015到1016之間，來完 成N+區域（7)，作為薄膜電晶體的源/汲極區域，如圖6所示。 參考圖7,隨即去除此光軍（6),另以光罩（8)遮蓋住N+區域，而進行 P+區域（9)的植入步驟。所用離子為BF2，濃度約在1X1015到1016之間。 接著如圖8所示，在圖7完成之結構之上沈積一介電層（10)，可以 是低溫氣化物或硼磷矽酸玻璃，厚約0.5卿到1.5um之間，並挖出接觸窗 (11)，分別通往N型源/汲極區域及P型區域。如此即完成了本發明的第一 個實施例反相器結構，其中第二層複晶矽（52)及兩旁之N型區域即為一値N 型薄膜電晶髏，而第二層複晶矽（51)及兩旁的N型及P型區域，卽為一値具 控制閘的PIN二極髏。 圖9所示為本發明之佈局圖，由圖可以看出其結構非常簡單，所佔面 積比起互補式薄膜電晶體要小很多。 本紙張尺度遑用中國國家標準(CNS)甲4規格(210x297公*) '—" ~ (請先閱讀背面之注意事項再填寫本頁) 裝. 訂- 線·03149 Λ 6 Β6 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of Invention (I) (1) Background of the Invention When making a projection LCD, the size of the display screen is usually limited to On a 3-inch corner, the number of pixels may be 640X480, which can reach 1000X1000; the size of the pixels is also as small as 95X95 wm, or even 70X40 Wm. As a result, the distance between the signal ends pulled out in parallel from the pixels will be sharply reduced. Therefore, the current assembly technology, such as tape automatic bonding technology (Tape Automatic Bonding; TAB), cannot drive the IC and the picture. The signal terminals are connected. In order to solve this problem, there is a method to directly design the drive 1C with thin-film electro-crystal technology, and directly manufacture it on the same substrate as the quinoline. At present, the commonly used polycrystalline silicon thin film transistor manufacturing process is because the charge mobility of polycrystalline silicon is high, and the size of the device can be reduced, which is sufficient to meet the aperture ratio (aperture ratio) on the projected thin film transistor LCD. ) Be demanding. The most important component in driving 1C is the shift register, which includes several inverters. In the known polycrystalline silicon thin film transistor manufacturing process, most of the inverters adopt the structure of complementary gold gas semi-thin film transistor (CM0SFET) as shown in FIG. 1. It includes two drains and two sources. The disadvantage is that it occupies a large area. (2) Brief description of the invention The present invention proposes an integrated circuit of a polycrystalline silicon inverter, which is composed of a thin film transistor and a PIN thin film diode with a control gate. It has the advantages of simple process, small area and low current consumption. The manufacturing method is as follows: depositing an undoped first layer of polycrystalline silicon on the insulating base, forming an insulating layer thereon, and then depositing a second layer of polycrystalline silicon, implanting appropriate conductive ions to have Conductivity; formulate this second layer of polycrystalline silicon graphics to provide the gate electrode of the thin film electric crystal and the control gate electrode of the PIN thin film diode. N-type (or P-type) ions are implanted on both sides of the thin film transistor gate as source / drain regions, and then P-type (or N-type) ions are implanted on the other side of the PIN control gate, and insulation is deposited immediately Layer, dig the contact window, and deposit metal to form an electrical connection ', the polycrystalline silicon thin film inverter of the present invention is completed. (Please read the precautions on the back before filling out this page) This paper standard is returned to the Chinese B standard (CNS) T4 specification (210x297 male dragon) k, 03149 Λ 6 B6 Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Description of the invention (2) (3) Brief description of the drawings Figure 1 is a layout diagram of a conventional technique. FIG. 2 is the first embodiment of the present invention and its equivalent circuit, including an N-type TFT and a PIN thin film diode. Fig. 3 is a second embodiment of the present invention. Figure 4 is a third embodiment of the invention. Fig. 5 is a fourth embodiment of the present invention. 6 to 8 are cross-sectional views of the manufacturing process of the thin film inverter of the present invention. 9 is a layout diagram of the thin film inverter of the present invention. (4) Working principle First, please refer to FIG. 2 to the first embodiment to explain the working principle of the inverter of the present invention. Picture 2 is the first embodiment of the present invention, which is composed of an N-type TFT (Dl) and a PIN film dipole hip (D2) with a control gate, and its equivalent circuit is an N-type TFT (El ), Consisting of a PIN thin film diode (E2) and a P-type parasitic TFT (E3). When V ϊ n = 0V, E1 is in the ON state and E3 is in the OFF state, so V. u τ = VD D = -15 \ /. When V ϊ N = -15V, E1 is OFF, E3 is ON, and E2 is forward biased, so Vo υ τ = ν i> = 0V. FIG. 3 is a second embodiment of the present invention, which is the same as the first embodiment of the present invention of FIG. 2, and is composed of a N-type thin film transistor and a PIN thin film diode, but its N-type TFT and PIN film The gate of the diode is separated and connected to VXN and \ / DD respectively. 4, the third embodiment of the present invention is composed of a P-type TFT (Dl) and a PIN film diode (D2) with a control gate, and its equivalent circuit is a P-type TFT (El), consisting of a PIN thin film diode (E2) and an N-type parasitic TFT (E3). When V r μ = 15V, E1 is OFF and E3 is ON, so Vo υ τ = \ / G N D = 0 \ /. When V z N = 0V, El is in the ON state, E2 is in forward bias, and E3 is in the OFF state, so l / 〇 u τ = 15 \ /. Fig. 5 is the fourth embodiment of the present invention, which is the same as the second embodiment of the present invention of Fig. 5, (please read the precautions on the back before writing this page) Install < Order_ Line-this paper size Printed in China B β Home Standard (CNS) A4 specifications (210X297 g; ¢) 03149 Λ 6 Β6 Printed by the Employee Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economy V. Description of invention (3) All are made of a P-type thin film crystal condyle and The PIN film diode is flat, but its P-type TFT and the gate electrode of the PIN film diode are separated and connected to V ϊ N and VD D, respectively. (5) Manufacturing method The first embodiment is a polycrystalline silicon thin film inverter composed of an N-type thin film transistor and a PIN thin film diode with a control gate. The manufacturing method is as follows. As shown in Fig. 6, a vaporized layer (2) of about 700-900 nm is grown on N-type silicon crystal H (l) by thermal vaporization, and then deposited on it by low pressure chemical vapor deposition (LPCVD) The first layer of polycrystalline silicon (3), the temperature is about 550 ~ 650t: between, the thickness is about 100 to 300nm. After making its pattern, it is thermally oxidized to grow into an insulating layer (4), about 50 to 150 nm thick. Then deposit a second layer of polycrystalline silicon, about 300 to 500nm thick, and doped with P0C13 ion diffusion technology, the temperature is between 900 and 1000Ϊ :, the concentration is 1015 ~ 1017atoms / cm3, and formulate its pattern, produced as a thin film The gate (52) of the transistor and the control gate (51) as a PIN diode. Following this, the steps of ion implantation are performed as shown in FIG. 6. At this time, the second layer of polycrystalline silicon (51), (52) after the formulation is used as the optical army for automatic alignment, and at the same time, the optical army (6) is used to cover the part to be the P-type region backward and implanted. P ion, the concentration is about 1X1015 to 1016, to complete the N + region (7), as the source / drain region of the thin film transistor, as shown in Figure 6. Referring to FIG. 7, the light army (6) is removed immediately, and the N + area is covered with a photomask (8), and the implantation step of the P + area (9) is performed. The ion used is BF2, the concentration is about 1X1015 to 1016. Next, as shown in FIG. 8, a dielectric layer (10) is deposited on the structure completed in FIG. 7, which may be low-temperature vapor or borophosphosilicate glass, with a thickness of about 0.5% to 1.5um, and contacts are dug out The window (11) leads to the N-type source / drain region and the P-type region, respectively. In this way, the inverter structure of the first embodiment of the present invention is completed, in which the second layer of polycrystalline silicon (52) and the N-type regions on both sides are an N-type thin film transistor, and the second layer of polycrystalline silicon Silicon (51) and the N-type and P-type areas on both sides are a PIN diode with a control gate. Figure 9 shows the layout of the present invention. It can be seen from the figure that the structure is very simple, and the occupied area is much smaller than that of the complementary thin film transistor. The size of this paper is not in accordance with Chinese National Standard (CNS) A4 specifications (210x297 g *) '— " ~ (please read the precautions on the back before filling in this page). Order-Thread ·