TW202431945A - Method of forming semiconductor structure - Google Patents

Abstract

A method of forming a semiconductor structure includes forming a dielectric stack over a substrate, wherein the dielectric structure includes a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer and a third support formed in sequence. A bottom electrode layer is formed in and over the dielectric stack. A planarization process is performed to remove a portion of the bottom electrode layer such that a top surface of the bottom electrode layer is substantially aligned to a top surface of the dielectric stack. An etching process is performed to at least remove a portion of the third support layer and form a first opening such that the first opening exposes the second sacrificial layer. The dielectric stack is continued to be etched along the first opening to form a second opening.

Description

Method of forming a semiconductor structure

The present disclosure relates to a method of forming a semiconductor structure.

Capacitors can be used in a variety of different semiconductor circuits. For example, capacitors can be used in dynamic random access memory (DRAM) memory circuits or any other type of memory circuit. DRAM memory circuits can be manufactured by replicating millions of identical circuit elements (called DRAM cells) on a single semiconductor wafer. A DRAM cell is an addressable location that can store bits of data (binary bits). In its common form, a DRAM cell can include two circuit components: a storage capacitor and an access field effect transistor.

The development of semiconductor circuits is aimed at achieving larger capacitors, therefore, it is desirable to develop semiconductor structures with higher capacitance.

The present invention discloses a method for forming a semiconductor structure.

According to some embodiments of the present disclosure, a method for forming a semiconductor structure includes forming a dielectric stack on a substrate. Forming a lower electrode layer, the lower electrode layer including a horizontal portion located above the dielectric stack and a vertical portion located in the dielectric stack. Performing a planarization process on the lower electrode layer to remove the horizontal portion of the lower electrode layer and retain the vertical portion of the lower electrode layer. After performing the planarization process, forming a mask layer on the lower electrode layer. Etching the mask layer and the dielectric stack to form a first opening.

In some embodiments of the present disclosure, a planarization process is performed such that the top surface of the dielectric stack is exposed.

In some embodiments of the present disclosure, a planarization process is performed to make the top surface of the bottom electrode layer substantially flush with the top surface of the dielectric stack.

In some embodiments of the present disclosure, the first opening has a first width in the mask layer and a second width in the dielectric stack, and the first width is greater than the second width.

In some embodiments of the present disclosure, the ratio of the first width to the second width is in the range of 1.5 to 2.5.

In some embodiments of the present disclosure, the lower electrode layer has a top surface and a side wall exposed by the first opening, and the top surface of the lower electrode layer is connected to the side wall of the lower electrode layer.

In some embodiments of the present disclosure, the sidewall of the lower electrode layer extends downward from the top surface of the lower electrode layer, and the sidewall of the lower electrode layer is perpendicular to the top surface of the lower electrode layer.

In some embodiments of the present disclosure, the method of forming a semiconductor structure further includes continuing to etch the dielectric stack along the first opening to form a second opening.

In some embodiments of the present disclosure, the width of the second opening in the dielectric stack is equal to the width of the first opening in the dielectric stack.

In some embodiments of the present disclosure, the method of forming a semiconductor structure further includes forming a high-k dielectric layer along a sidewall of the lower electrode layer, and forming an upper electrode layer along the sidewall of the high-k dielectric layer to define a capacitor including the lower electrode layer, the high-k dielectric layer, and the upper electrode layer in the second opening.

According to the above-mentioned implementation method of the present disclosure, since a planarization process is performed to remove a portion of the lower electrode layer and an etching process is performed to form the first opening, the lower electrode layer will not be etched when forming the first opening, so the area of the lower electrode layer will not be reduced, which can avoid reducing the capacitance value of the semiconductor structure.

The following will disclose multiple embodiments of the present disclosure with drawings. For the purpose of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. In other words, in some embodiments of the present disclosure, these practical details are not necessary and therefore should not be used to limit the present disclosure. In addition, in order to simplify the drawings, some commonly used structures and components will be depicted in the drawings in a simple schematic manner. In addition, in order to facilitate the reader's viewing, the size of each component in the drawings is not drawn according to the actual scale.

As used herein, "about", "approximately" or "substantially" shall generally refer to within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The numerical values given herein are approximate, meaning that if not explicitly stated, the meaning of the term "about", "approximately" or "substantially" can be inferred.

FIG. 1 to FIG. 10 are cross-sectional views of various steps of a method for forming a semiconductor structure according to some embodiments of the present disclosure. Referring to FIG. 1 , a dielectric stack DS is formed on a substrate 110. In detail, forming the dielectric stack DS includes forming a first supporting layer 120 on the substrate 110, forming a first sacrificial layer 130 on the first supporting layer 120, forming a second supporting layer 140 on the first sacrificial layer 130, forming a second sacrificial layer 150 on the second supporting layer 140, and forming a third supporting layer 160 on the second sacrificial layer 150. That is, the dielectric stack DS includes a first supporting layer 120, a first sacrificial layer 130, a second supporting layer 140, a second sacrificial layer 150, and a third supporting layer 160 formed in sequence.

The substrate 110 has a device region DR and a peripheral region PR, wherein the device region DR is a region where a semiconductor structure (e.g., a capacitor) is formed. The peripheral region PR is adjacent to the device region DR. For example, the peripheral region PR surrounds the device region DR. The substrate 110 includes a dielectric layer 112, wherein the dielectric layer 112 may be an interlayer dielectric (ILD) layer or an intermetallic dielectric (IMD) layer. The dielectric layer 112 may be a low-k dielectric layer made of a low dielectric constant (k) material, an ultra-low-k material, or a combination thereof. In some embodiments, the dielectric layer 112 includes a nitride (e.g., silicon nitride), or other suitable dielectric materials. The substrate 110 further includes a connection pad 114 and a bit line contact 116 formed in the dielectric layer 112, wherein the connection pad 114 and the bit line contact 116 are located above the device region DR of the substrate 110. The connection pad 114 and/or the bit line contact 116 may include aluminum, aluminum alloy, copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, cobalt, etc., or a combination thereof. In some embodiments, the substrate 110 further includes a transistor or other similar component. In this way, a capacitor (e.g., capacitor Ca in FIG. 10 ) subsequently formed in the dielectric stack DS is connected to other components (e.g., transistors) in the substrate 110 through the connection pad 114.

In some embodiments, the first supporting layer 120, the second supporting layer 140, and the third supporting layer 160 include nitrides (e.g., silicon nitride). In some embodiments, the first sacrificial layer 130 and the second sacrificial layer 150 include oxides. The first sacrificial layer 130 and the second sacrificial layer 150 may be made of different materials. When forming the first sacrificial layer 130, a dopant is added to the first sacrificial layer 130, and the dopant includes boron, phosphorus, or a combination thereof. For example, the first sacrificial layer 130 is made of borophosphosilicate glass (BPSG), which is silicon oxide doped with boron and phosphorus. In some embodiments, the second sacrificial layer 150 is made of tetraethoxysilane (TEOS) or other suitable dielectric materials.

Referring to FIG. 2 , a lower electrode layer 170 is formed in and above the dielectric stack DS. The method for forming the lower electrode layer 170 may first form an opening 165 in the dielectric stack DS above the device region DR of the substrate 110, and the opening 165 penetrates the first supporting layer 120, the first sacrificial layer 130, the second supporting layer 140, the second sacrificial layer 150, and the third supporting layer 160 and exposes the connection pad 114 of the substrate 110, and then fills the opening 165 with a conductive material to form the lower electrode layer 170. In some embodiments, the lower electrode layer 170 includes a horizontal portion 172 located above the dielectric stack DS and a vertical portion 174 located in the dielectric stack DS. The vertical portion 174 of the lower electrode layer 170 is formed above the device region DR of the substrate 110 and contacts the sidewall DS1 of the dielectric stack DS. The vertical portion 174 of the lower electrode layer 170 extends upward from the connection pad 114 of the substrate 110. In other words, the vertical portion 174 of the lower electrode layer 170 is located in the peripheral region PR. In some embodiments, the lower electrode layer 170 includes titanium nitride (TiN) or other suitable conductive materials.

Referring to FIGS. 2 and 3 , a planarization process is performed to remove the horizontal portion 172 of the lower electrode layer 170 so that the top surface 171 of the lower electrode layer 170 is substantially flush with the top surface DST of the dielectric stack DS. The planarization process is performed so that the third support layer 160 of the dielectric stack DS is exposed. In some embodiments, the planarization process is performed to completely remove the horizontal portion 172 of the lower electrode layer 170 so that the vertical portion 174 of the lower electrode layer 170 remains intact (unchanged) above the device region DR of the substrate 110, and there is no lower electrode layer 170 above the peripheral region PR of the substrate 110. In some embodiments, the planarization process may be, for example, a chemical-mechanical polishing (CMP) process.

4 , after performing a planarization process, a fourth supporting layer 180 is formed on the dielectric stack DS. The fourth supporting layer 180 contacts the lower electrode layer 170 and the third supporting layer 160 of the dielectric stack DS. In some embodiments, the fourth supporting layer 180 and the third supporting layer 160 include the same material, such as silicon nitride.

After the fourth supporting layer 180 is formed, a third sacrificial layer 190 is formed on the fourth supporting layer 180. The third sacrificial layer 190 contacts the fourth supporting layer 180. In some embodiments, the third sacrificial layer 190 includes an oxide, such as silicon oxide or other suitable materials. In some other embodiments, the third sacrificial layer 190 includes the same material as the first sacrificial layer 130 or the second sacrificial layer 150.

After forming the third sacrificial layer 190, a first mask layer 200 and a second mask layer 210 are sequentially formed. In detail, the first mask layer 200 is formed on the third sacrificial layer 190, and the second mask layer 210 is formed on the first mask layer 200. In some embodiments, the first mask layer 200 and the second mask layer 210 include materials different from each other. In some embodiments, the first mask layer 200 and the second mask layer 210 include the same material. For example, the first mask layer 200 and/or the second mask layer 210 include an organic material. The first mask layer 200 and/or the second mask layer 210 is a bottom anti-reflective coating (BARC) layer. Alternatively, the first mask layer 200 and/or the second mask layer 210 may include silicon nitride, amorphous carbon (α-C), silicon oxynitride, silicon oxide, or other suitable materials. In some embodiments, the fourth supporting layer 180, the third sacrificial layer 190, the first mask layer 200, and the second mask layer 210 may be collectively considered as a plurality of mask layers on the dielectric stack DS.

After forming the first mask layer 200 and the second mask layer 210, a patterned photoresist 220 is formed on the second mask layer 210. The method of forming the patterned photoresist 220 may include first forming a photoresist layer on the second mask layer 210, and then patterning the photoresist layer using a suitable lithography process to form the patterned photoresist 220, so that a portion of the second mask layer 210 is exposed by the patterned photoresist 220.

Referring to FIG. 5 , an etching process is performed to remove at least a portion of the third support layer 160 of the dielectric stack DS and form a first opening 230, so that the first opening 230 exposes the second sacrificial layer 150. Since a planarization process has been performed to remove the vertical portion 174 of the lower electrode layer 170 (see FIGS. 2 and 3 ) before forming the first opening 230, the lower electrode layer 170 will not be etched when the first opening 230 is formed, so the area of the lower electrode layer 170 will not be reduced, and the capacitance value of the semiconductor structure can be avoided from being reduced. The first opening 230 is formed so that the lower electrode layer 170 has a top surface 171 exposed by the first opening 230 and a side wall 173 connected to the top surface 171. The sidewall 173 of the lower electrode layer 170 extends downward from the top surface 171 , and the sidewall 173 is substantially perpendicular to the top surface 171 .

In some embodiments, performing an etching process to form the first opening 230 includes a plurality of etching steps. For example, a portion of the second mask layer 210 is etched using the patterned photoresist 220 as an etching mask to expose the first mask layer 200. Then, a portion of the first mask layer 200 is sequentially etched to expose the third sacrificial layer 190, a portion of the third sacrificial layer 190 is etched to expose the fourth supporting layer 180, a portion of the fourth supporting layer 180 is etched to expose the third supporting layer 160, and a portion of the third supporting layer 160 is etched to expose the second sacrificial layer 150. Subsequently, the patterned photoresist 220, the second mask layer 210, and the first mask layer 200 are removed in sequence to expose the top surface of the third sacrificial layer 190. In some embodiments, etching a portion of the fourth supporting layer 180 and etching a portion of the third supporting layer 160 are performed by a single etching step. That is, a portion of the fourth supporting layer 180 and a portion of the third supporting layer 160 are etched at the same time.

In some embodiments, the etching process includes a dry etching process, such as a plasma etching process. In some embodiments, the etching process includes an anisotropic etching process, wherein the anisotropic etching process uses an etching gas having etching selectivity between the third supporting layer 160 and the lower electrode layer 170, so that a portion of the third supporting layer 160 is removed and the lower electrode layer 170 is not removed. For example, the etching gas may include trifluoromethane (CHF ₃ ) or other suitable etching gases. In other words, the third supporting layer 160 has a higher etching rate than the lower electrode layer 170 during the etching process, which will result in a portion of the third supporting layer 160 being removed and exposing the second sacrificial layer 150 below, while the lower electrode layer 170 remains substantially intact (unchanged). In this way, the balance of the lower electrode layer 170 can be improved and the problem of abnormal pattern can be reduced. For example, the problem of merging between different lower electrode layers 170 (or between capacitors formed subsequently) and causing a short circuit can be avoided.

In some embodiments, the sidewall 173 of the lower electrode layer 170 exposed by the first opening 230 has a depth D1, wherein the depth D1 is in a range of about 100 nm to about 200 nm (e.g., 110 nm), and the depth D1 is substantially equal to the thickness of the third supporting layer 160. If the depth D1 is greater than about 200 nm, the lower electrode layer 170 may occupy too large an area, making it impossible for an etching machine to accommodate; if the depth D1 is less than about 100 nm, the lower electrode layer 170 or the third supporting layer 160 may be unable to support the capacitor, and a short circuit may occur between capacitors.

In some embodiments, the first opening 230 has a maximum width W1 in the fourth supporting layer 180 (or the third sacrificial layer 190) and a minimum width W2 in the third supporting layer 160 (or between the lower electrode layers 170). The ratio of the maximum width W1 to the minimum width W2 of the first opening 230 may be in a range of about 1.5 to about 2.5 (e.g., 2). For example, the maximum width W1 of the first opening 230 is in a range of about 55 nanometers to about 65 nanometers (e.g., about 60 nanometers), and the minimum width W2 of the first opening 230 is in a range of about 25 nanometers to about 35 nanometers (e.g., about 30 nanometers).

Referring to FIGS. 5 and 6 , an etching process is performed to remove the entire second sacrificial layer 150 of the dielectric stack DS, so that the second supporting layer 140 is exposed. In some embodiments, the second sacrificial layer 150 is removed by using a wet etching process, and the etchant may include hydrogen fluoride (HF) or other suitable etchants. In some embodiments, during the etching process performed to remove the second sacrificial layer 150 of the dielectric stack DS, the third sacrificial layer 190 is removed simultaneously to expose the top surface of the fourth supporting layer 180.

7 , a portion of the second supporting layer 140 is removed to expose the first sacrificial layer 130. In detail, a hole H1 is formed in the second supporting layer 140 above the device region DR of the substrate 110 to expose a portion of the first sacrificial layer 130. In some embodiments, the second supporting layer 140 is etched by a dry etching process to form the hole H1.

Referring to FIGS. 7 and 8 , the entire first sacrificial layer 130 of the dielectric stack DS is removed from the hole H1. In some embodiments, an etching process is performed to remove the first sacrificial layer 130. For example, the first sacrificial layer 130 is removed by using a wet etching process, and the etchant includes hydrogen fluoride (HF) or other suitable etchants. In some embodiments, the second sacrificial layer 150 ( FIG. 6 ), a portion of the second supporting layer 140 ( FIG. 7 ), and the first sacrificial layer 130 are removed to form/define a second opening 240 in the dielectric stack DS. In some embodiments, the etching process of FIGS. 6 to 8 is to continue etching the dielectric stack DS along the first opening 230 (FIG. 5) to form a second opening 240. That is, the second opening 240 is formed continuously downward from the first opening 230 (FIG. 5), so that the width W3 of the second opening 240 is substantially equal to the minimum width W2 of the first opening 230. Forming the second opening 240 in the dielectric stack DS further allows the first supporting layer 120 of the dielectric stack DS and the sidewall 175 of the lower electrode layer 170 to be exposed by the second opening 240. In some embodiments, the first supporting layer 120 , the second supporting layer 140 , and the third supporting layer 160 are connected via the lower electrode layer 170 .

9, a high-k dielectric layer 250 is formed along the sidewall 175 of the lower electrode layer 170. The high-k dielectric layer 250 may be formed along the sidewall 175 of the lower electrode layer 170 facing the second opening 240 of the dielectric stack DS, and may also be formed along the other sidewall of the lower electrode layer 170 facing away from the second opening 240 of the dielectric stack DS. In addition, the high-k dielectric layer 250 may be formed along the sidewalls, top surfaces, and bottom surfaces of the second supporting layer 140 and the third supporting layer 160, and the top surface of the first supporting layer 120. In some embodiments, the high-k dielectric layer 250 includes ferrite (HfO). In various examples, high-k dielectric layer 250 includes metal oxide (eg, HfSiO ₂ , ZnO, ZrO ₂ , Ta ₂ O ₅ , Al ₂ O ₃ , etc.), metal nitride, or a combination thereof.

10 , a first conductive layer 260 is formed along the sidewall 253 of the high-k dielectric layer 250. In some embodiments, the first conductive layer 260 is located above the horizontal surface of the high-k dielectric layer 250. The first conductive layer 260 may include titanium nitride (TiN) or other suitable conductive materials. In some embodiments, the first conductive layer 260 and the lower electrode layer 170 include the same material.

The semiconductor layer 270 is formed on the first conductive layer 260. Specifically, the semiconductor layer 270 is formed between the first supporting layer 120 and the second supporting layer 140 and between the second supporting layer 140 and the third supporting layer 160. The semiconductor layer 270 may completely fill the second opening 240 of the dielectric stack DS. The semiconductor layer 270 may include polysilicon or other suitable semiconductor materials. The material of the semiconductor layer 270 is different from the material of the first conductive layer 260 and the material of the lower electrode layer 170.

After forming the semiconductor layer 270, a second conductive layer 280 is formed on the semiconductor layer 270. The second conductive layer 280 is formed along the top surface and sidewalls of the semiconductor layer 270. The second conductive layer 280 may include a metal (e.g., tungsten) or other suitable conductive materials. The material of the second conductive layer 280 is different from the material of the first conductive layer 260 and is also different from the material of the lower electrode layer 170. The first conductive layer 260, the semiconductor layer 270, and the second conductive layer 280 have the same potential. In some embodiments, the first conductive layer 260 is regarded as the upper electrode layer of the capacitor Ca. In some other embodiments, the first conductive layer 260 and the semiconductor layer 270 are regarded as the upper electrode layer of the capacitor Ca. Alternatively, the first conductive layer 260, the semiconductor layer 270 and the second conductive layer 280 are considered as the upper electrode layer of the capacitor Ca. After the upper electrode layer (i.e., the first conductive layer 260, the semiconductor layer 270 and/or the second conductive layer 280) is formed, the capacitor Ca including the lower electrode layer 170, the high-k dielectric layer 250 and the upper electrode layer is defined in the second opening 240 of the dielectric stack DS.

In some embodiments of the present disclosure, a method for forming a semiconductor structure is to first perform a planarization process in FIG. 3 to remove a portion of the lower electrode layer 170, and then perform subsequent processes, such as forming a fourth support layer 180, a third sacrificial layer 190, a first mask layer 200, a second mask layer 210 and a patterned photoresist 220 (FIG. 4), forming a first opening 230 (FIG. 5) and forming a second opening 240, etc. Therefore, the lower electrode layer 170 will not be additionally etched in the etching process (for example, the etching process performed in FIG. 5), thereby avoiding unnecessary reduction in the area of the lower electrode layer 170, thereby avoiding reducing the capacitance value of the semiconductor structure (capacitor Ca).

In some embodiments, the semiconductor structure includes a substrate 110, a plurality of supporting layers (i.e., a first supporting layer 120, a second supporting layer 140, and a third supporting layer 160), and a capacitor Ca. The first supporting layer 120, the second supporting layer 140, and the third supporting layer 160 are arranged from bottom to top, and the first supporting layer 120, the second supporting layer 140, and the third supporting layer 160 are spaced apart from each other. In other words, the third supporting layer 160 is located above the second supporting layer 140, and the second supporting layer 140 is located above the first supporting layer 120. Each of the capacitors Ca includes a lower electrode layer 170, a high-k dielectric layer 250, and an upper electrode layer (i.e., a first conductive layer 260, a semiconductor layer 270, and/or a second conductive layer 280). The lower electrode layer 170 has a top surface 171 and a side wall 175 connected to the top surface 171 and extending continuously downward. The top surface 171 of the lower electrode layer 170 is substantially flush with the top surface of the third supporting layer 160 and is covered by the high-k dielectric layer 250. The side wall 175 of the lower electrode layer 170 is substantially perpendicular to the top surface 171. It is worth noting that the capacitor Ca in FIG. 10 is illustrative, and the capacitor Ca is not limited to the structure shown in FIG. 10. For example, the capacitor Ca may include other additional layers.

Although the present disclosure has been disclosed in the above implementation form, it is not intended to limit the present disclosure. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the scope of the attached patent application.

110: substrate 112: dielectric layer 114: connection pad 116: bit line contact 120: first support layer 130: first sacrificial layer 140: second support layer 150: second sacrificial layer 160: third support layer 165: opening 170: lower electrode layer 171: top surface 172: horizontal portion 173: side wall 174: vertical portion 175: side wall 180: fourth support layer 190: third sacrificial layer 200: first mask layer 210: second mask layer 220: patterned photoresist 230: First opening 240: Second opening 250: High-k dielectric layer 253: Sidewall 260: First conductive layer 270: Semiconductor layer 280: Second conductive layer Ca: Capacitor D1: Depth DS: Dielectric stack DS1: Sidewall DST: Top surface DR: Component region H1: Hole PR: Peripheral region W1: Maximum width W2: Minimum width W3: Width

In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more clearly understandable, the attached drawings are described as follows: Figures 1 to 10 show cross-sectional views of various steps of the method for forming a semiconductor structure according to some embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

110: Substrate

112: Dielectric layer

114:Connection pad

116: Bit line contact

120: The first support layer

140: The second support layer

160: The third support layer

170: Lower electrode layer

171: Top

175: Side wall

240: Second opening

250: High dielectric constant dielectric layer (high-k dielectric layer)

253: Side wall

260: First conductive layer

270:Semiconductor layer

280: Second conductive layer

Ca:Capacitor

DS: Dielectric Stack

DR: Component area

PR: Peripheral area

Claims (10)

A method for forming a semiconductor structure, comprising: forming a dielectric stack on a substrate; forming a lower electrode layer, the lower electrode layer comprising a horizontal portion located above the dielectric stack and a vertical portion located in the dielectric stack; performing a planarization process on the lower electrode layer to remove the horizontal portion of the lower electrode layer and retain the vertical portion of the lower electrode layer; after performing the planarization process, forming a mask layer on the lower electrode layer; and etching the mask layer and the dielectric stack to form a first opening. The method of claim 1, wherein the planarization process is performed so that a top surface of the dielectric stack is exposed. The method as described in claim 1, wherein the planarization process is performed so that a top surface of the lower electrode layer is substantially flush with a top surface of the dielectric stack. The method of claim 1, wherein the first opening has a first width in the mask layer and a second width in the dielectric stack, and the first width is greater than the second width. A method as described in claim 4, wherein the ratio of the first width to the second width is in the range of 1.5 to 2.5. The method as described in claim 1, wherein the lower electrode layer has a top surface and a side wall exposed by the first opening, and the top surface of the lower electrode layer is connected to the side wall of the lower electrode layer. The method as described in claim 6, wherein the side wall of the lower electrode layer extends downward from the top surface of the lower electrode layer, and the side wall of the lower electrode layer is perpendicular to the top surface of the lower electrode layer. The method as described in claim 1 further comprises: Continuing to etch the dielectric stack along the first opening to form a second opening. The method of claim 8, wherein a width of the second opening in the dielectric stack is equal to a width of the first opening in the dielectric stack. The method as described in claim 8 further comprises: forming a high-k dielectric layer along a side wall of the lower electrode layer; and forming an upper electrode layer along a side wall of the high-k dielectric layer to define a capacitor including the lower electrode layer, the high-k dielectric layer and the upper electrode layer in the second opening.