KR20040005075A - Method for manufacturing capacitor and bit line in semiconductor device using the same - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor and bit line of semiconductor device using the same are provided to improve capacitance by enhancing effective surface area of a capacitor. CONSTITUTION: The first interlayer dielectric(112) including the first contact hole is formed on a semiconductor substrate(102) having MOS transistors(110). A storage node(114) is formed to have a plurality of pores by filling the first contact hole with a conductive layer and CMP(Chemical Mechanical Polishing) using polysilicon grains as a slurry. A dielectric film is formed between the pores. Then, an upper electrode is formed on the dielectric film.

Description

Method for manufacturing capacitor and bit line in semiconductor device using the same

The present invention relates to a method of manufacturing a capacitor and a method of manufacturing a bit line of a semiconductor device using the same, and more particularly, to a method of manufacturing a capacitor and a method of manufacturing a bit line of a dynamic random access memory (DRAM) device. It is about.

In general, as a semiconductor memory device, a DRAM device having a high capacity while freely inputting and outputting information has been widely used. A DRAM device generally includes a memory cell region for storing information data in the form of charge and a peripheral circuit region for inputting and outputting data. DRAM devices generally include one access transistor and one storage capacitor.

In recent years, as the size of a memory cell decreases due to high integration, the size of a capacitor is gradually decreasing. Therefore, manufacturing a capacitor having a reduced size and a high accumulation capacity has become a more important problem. In fact, it is a problem to improve the storage capacity of the capacitor without increasing the horizontal area occupied by the capacitor on the substrate. In terms of process order, the technology change of the capacitor was changed from the CUB (Capacitor Under Bit-line) structure in which the capacitor is formed before the formation of the bit line, to the COB (CapacitorOver Bit-line) structure in which the capacitor is formed after the bit line is formed. Since the COB structure forms the capacitor after the bit line is formed in comparison with the CUB structure, it is possible to form the capacitor irrespective of the bit line process margin, thereby having an excellent advantage in increasing the storage capacity of the capacitor in a limited area.

In general, the storage capacitor 'C' of the capacitor is obtained by the following equation. here, ' 'And' Are the dielectric constants of the capacitor and the dielectric constant of the capacitor dielectric film, respectively, 'A' represents the effective area of the capacitor, and 'd' represents the thickness of the dielectric film.

Equation

As can be seen from the above equation, in order to improve the storage capacity, a method of forming a dielectric film having a high dielectric constant, a method of increasing the effective area of a capacitor, a method of reducing the thickness of the dielectric film, and the like can be considered.

However, the method of reducing the thickness of the dielectric film has its limitations in application to the highly integrated memory device in view of the current technology trend. Although dielectric materials having a high dielectric constant and processes for forming dielectric films using these materials are widely known, it is difficult to adopt dielectrics other than nitride in current processes in selecting a dielectric material suitable for a semiconductor device. In other words, high dielectric materials are difficult to apply to current semiconductor manufacturing processes due to the burden of new investment and process stability.

Therefore, considering the current situation of the manufacturing process of the semiconductor device, it can be evaluated that the method of improving the storage capacity through the increase of the effective area of the capacitor is most suitable. According to this method, an early planar capacitor structure is converted into a stack type or a trench type capacitor structure, and in a stacked type capacitor structure, a storage electrode such as a cylinder type capacitor or a fin type capacitor is used. As a structure for increasing the area of a storage electrode, technology changes are being made.

However, in the method of raising the height of the capacitor as in the stacked capacitor structure as described above, various problems arise. First, in the DLM process, it is very difficult to form a metal contact, and an excessively high capacitor may collapse. In addition, when the height of the capacitor is increased, deposition materials do not reach from below, and thus the capacity of the capacitor is not substantially increased.

Accordingly, the present invention has been made to solve the problems of the prior art described above, and provides a method of manufacturing a capacitor of a semiconductor device capable of increasing the effective surface area of the capacitor of the semiconductor device to improve the storage capacity of the high capacitor. There is a purpose.

1 to 8 are cross-sectional views illustrating a method of manufacturing a capacitor and a bit line of a semiconductor device according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

102 semiconductor substrate 104 word line

106: nitride film 108, 122: spacer

110: MOS transistor 112: first interlayer insulating film

114: storage node 116: dielectric film

118: upper electrode 120: first contact hole

124: contact plug 126: second interlayer insulating film

128: second contact hole 130: bit line

In the present invention, forming a first interlayer insulating film including a first contact hole on the semiconductor substrate on which the substructure is formed, and filling the first contact hole and forming a plurality of voids, polysilicon particles or polysilicon Forming a storage node using a chemical mechanical polishing method using an oxide grain as a slurry, penetrating a dielectric material to form a dielectric film between a plurality of pores in the storage node, and forming an upper electrode to cover the dielectric film. It provides a capacitor manufacturing method comprising the step of forming.

In addition, in the present invention, the step of forming a capacitor, and the upper electrode and the first interlayer insulating film which are not corresponding to the storage node, and the first interlayer insulating film are sequentially etched so that the drain region included in the lower structure is exposed. Forming a second contact hole, forming a spacer on an inner wall of the second contact hole, forming a bit line contact plug to fill the second contact hole, and forming a second upper portion of the entire structure. Forming an interlayer insulating film, etching the second interlayer insulating film to expose the contact plug, forming a third contact hole, and forming a bit line to fill the third contact hole; It provides a bit line manufacturing method.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information. In the drawings, the same reference numerals refer to the same elements, and descriptions of overlapping elements will be omitted.

1 to 8 are cross-sectional views illustrating a method of manufacturing a bit line of a semiconductor device in accordance with a preferred embodiment of the present invention. As an example, cross-sectional views of a DRAM device including a capacitor having a CUB structure are illustrated.

Referring to FIG. 1, a transistor such as a metal oxide semiconductor (MOS) transistor 110 is formed on a semiconductor substrate 102 having a device region defined by a field oxide film (not shown). The MOS transistor 110 is formed on the semiconductor substrate 102, and is a source region or a drain region (not shown) and a word line 104 which are in contact with a storage node for a lower electrode of the capacitor (see 114 in FIG. 3). (Eg, a gate electrode), a nitride film 106 and a spacer 108.

Subsequently, spin on glass (SOG), un-doped silicate glass (USG), boron-phosphorus silicate glass (BPSG), phosphorus silicalicate glass (PSG) plasma enhanced tetra ethyl ortho silicate glass (PEPEOS), or IPO After the deposition of Inter Poly Oxide, an interlayer insulating film 112 (hereinafter, referred to as “Blanket” or “etch back”) may be subjected to planarization to expose the nitride film 106. A first interlayer insulating film) is formed.

Referring to FIG. 2, after the photoresist (not shown) is coated on the entire structure, an exposure process and a developing process using a photo mask are sequentially performed, and the storage node of the capacitor is subsequently processed. 114) (eg, conventionally, a landing plug is formed in this region) to form a photoresist pattern PR that opens the area where it will be formed.

Referring to FIG. 3, an etching process using the photoresist pattern PR formed in FIG. 2 as an etching mask is performed to form a first interlayer insulating layer formed between the word lines 104 to expose a source region between the word lines 104. Etch (112) to remove it. Thereafter, the photoresist pattern PR used to etch the first interlayer insulating film 112 is removed by performing a strip process.

Subsequently, a storage node 114 in the form of a pore is formed in a region where the first interlayer insulating layer 112 between the word lines 104 is removed through the etching process. At this time, the manufacturing process of the storage node 114 is as follows.

First, by using chemical mechanical polishing (CMP) equipment, and using polysilicon grains (or polysilicon oxide grains) as a slurry, the interlayer dielectric layer 112 in the etching process. The removed site is filled with polysilicon grains. In this case, the polysilicon grains or the polysilicon grains may be formed using a grinding method, and the size thereof is preferably formed to a thickness of 50 to 150 mm 3. Then, in order to interrupt the electrical connection between adjacent storage nodes 114, a chemical mechanical polishing method or an etch back method is performed to isolate the storage node 114. Then, heat treatment processes such as annealing in the air using nitrogen (N ₂ ) gas or argon (Ar) gas, which is an inert gas, in order to interconnect the polysilicon grains in the storage node 104. To form the final storage node 114.

Referring to FIG. 4, a dielectric material is deposited on the entire structure to form a dielectric film 116. In this case, as the dielectric material of the dielectric layer 116, it is preferable to use a material having a very good step coverage so as to fill the small voids in the storage node 114. Chemical Vapor Deposition (CVD) It is preferable to use a material that can be deposited in a process such as ONO (Oxide / Nitreide / Oxide) or TaON. As such, since the dielectric film 116 is formed by penetrating into the voids in the storage node 114, the effective surface area may be increased accordingly.

Subsequently, a polysilicon layer 118a and a titanium nitride layer (TiN; 118b) may be laminated as shown above, or a monolayer structure of the polysilicon layer 118a or a monolayer of the titanium nitride layer 118b may be used. An upper electrode 118 having a structure is formed. In this case, when the upper electrode 118 is formed in a stacked structure of the polysilicon layer 118a and the titanium nitride layer 118b, the titanium nitride layer 118b functions as a barrier layer during a subsequent chemical mechanical polishing planarization process. do.

Referring to FIG. 5, after a photoresist (not shown) is coated on the entire structure, an exposure process and a development process using a photo mask are sequentially performed to produce a subsequent bit line contact plug (see '124' in FIG. 6). A photoresist pattern (not shown) that opens the region to be formed is formed.

Subsequently, an etching process using the photoresist pattern as an etching mask is performed to expose the drain region between the word line 104 and the first interlayer insulating layer 112 formed between the upper electrode 118 and the word line 104. By etching, a contact hole 120 (hereinafter, referred to as a “first contact hole”) is formed. This photoresist pattern is then removed by stripping.

Subsequently, an oxide layer (not shown) is deposited on the entire structure, and then a spacer 122 is formed on the inner surface of the first contact hole 120 by performing an entire surface etching process such as a blanket or an etch back. As a result, the bit line contact plug 124 formed through the subsequent process is electrically isolated from the upper electrode 118 of the capacitor.

Referring to FIG. 6, after the polysilicon 124 is deposited by a gap fill method on the entire structure so that voids do not occur in the first contact hole 120, the upper electrode 118 is formed. The planarization process is performed by a chemical mechanical polishing method using the titanium nitride film 118b as a barrier to form a bit line contact plug 124 to fill the first contact hole 120.

Referring to FIG. 7, an interlayer insulating film 126 (hereinafter referred to as a “second interlayer insulating film”) is formed on the entire structure by using an SOG, USG, BPSG, PSG, PETEOS, IPO, or oxide film.

Subsequently, after the photoresist (not shown) is coated on the entire structure, an exposure process and a developing process using a photo mask are sequentially performed to form a photoresist pattern (not shown).

Subsequently, an etching process using the photoresist pattern as an etching mask is performed to expose the bit line contact plug 124 between the second interlayer insulating layer 126 (hereinafter referred to as a “second contact hole”). ). This photoresist pattern is then removed by stripping.

Referring to FIG. 8, an electroplating process (EP), a physical vapor deposition (PVD), or a chemical vapor deposition (CVD) is formed on the entire structure to fill the second contact hole 128. After the deposition of a conductive material such as copper (Cu), aluminum (Al) or tungsten (W) to form a bit line 130 through a patterning process.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, in the present invention, the lower electrode storage node of the capacitor is formed by using polysilicon grains or polysilicon oxide grains so that a plurality of pores are formed, and a dielectric film is formed in these pores through a subsequent process, By increasing the effective surface area of the capacitor, it is possible to improve the accumulation capacity of the high capacitor.

In addition, in the present invention, by forming a lower electrode storage node of the capacitor using a chemical mechanical polishing method, and forming a dielectric film in the pores of the storage node through a deposition process using a chemical vapor deposition method, the addition of additional process equipment The process can be carried out to reduce the development cost and simplify the process of the capacitor.

Further, in the present invention, the dielectric film of the capacitor is formed in the storage node for the lower electrode, which is very advantageous for securing the critical dimension of the capacitor.

In addition, in the present invention, by forming the dielectric film of the capacitor in the lower electrode storage node, the height of the capacitor can be lowered, so that subsequent bit line processes can be facilitated and high integration can be improved.

Claims (4)

(a) forming a first interlayer insulating film including a first contact hole on a semiconductor substrate on which a substructure is formed; (b) forming a storage node using a chemical mechanical polishing method using a polysilicon grain or a polysilicon oxide grain as a slurry to fill the first contact hole and form a plurality of pores; (c) penetrating a dielectric material between the plurality of pores in the storage node to form a dielectric film; And (d) forming an upper electrode to cover the dielectric film. The method of claim 1, The dielectric film is a capacitor manufacturing method, characterized in that the ONO or TaON. The method of claim 1, The upper electrode is a capacitor manufacturing method, characterized in that formed of a polysilicon layer and a titanium nitride layer laminated structure, or a polysilicon layer or a titanium nitride layer single layer structure. (a) forming a capacitor in the step of claim 1; (b) forming a second contact hole by sequentially etching the upper electrode and the first interlayer insulating layer not corresponding to the storage node so that the drain region included in the lower structure is exposed; (c) forming a spacer on an inner wall of the second contact hole; (d) forming a bit line contact plug to fill the second contact hole; (e) forming a second interlayer insulating film over the entire structure; (f) forming a third contact hole by etching the second interlayer insulating layer so that the contact plug is exposed; And (g) forming a bit line to fill the third contact hole.