JP2002026291A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a cylindrical storage node electrode through an already existing process using no CMP device. SOLUTION: A contact hole having a larger upper opening diameter is formed through an interlayer dielectric 8A on a diffusion layer and a first film 9A having such a film thickness that the film 9A does not fill up completely the contact hole is formed in the hole. Then an insulating film 21A is formed only on the side wall of the contact hole through the first film 9A. After a second film 9B is formed on the first film 9A until the contact hole is completely filled up with the film 9B, the film 9B is left only in the contact hole by etching back the film 9B. Finally, the storage node electrode 9 composed of the first and second films 9A and 9B is formed by etching off the insulating film 21A in the contact hole.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique for increasing the capacity of a DRAM cell capacitor.

[0002]

2. Description of the Related Art FIG. 9 is a sectional view for explaining a basic structure of a conventional semiconductor device.

[0005] Reference numeral 51 denotes a semiconductor substrate of one conductivity type, for example, a P type, on which an element isolation film 52 and a gate oxide film 5 are formed.
3, a gate electrode 54 formed through the gate oxide film 53, an N-type source / drain region 55 formed in the surface layer of the substrate adjacent to the gate electrode 54, A bit line 57 contacting on the region 55 and a cell capacitor (storage node electrode (ST) 5) contacting on the source region 55
9, a capacitor insulating film 60, and a cell plate electrode (SP) 61. ) Constitute a memory cell transistor of a dynamic random access memory (hereinafter, referred to as DRAM). Reference numerals 56, 58 and 62 denote interlayer insulating films, respectively, and reference numeral 63 denotes a metal wiring formed on the interlayer insulating film 62.

[0004]

In the above-mentioned DRAM having a so-called stacked capacitor structure, the area occupied by the memory cells is reduced as the elements are further miniaturized. It is required to increase the effective height of the object.

[0005] In this case, the burden on post-processes, such as the burden of contact etching, the burden of sputter formation of a barrier film in the contact hole, and the burden of lithography of a metal film, etc., are increased in promoting flattening. There was a problem of becoming.

Therefore, a technology has been developed which enables the planarization while increasing the capacitor area by forming a cylindrical storage node electrode.

An example of a method of forming such a cylindrical storage node electrode will be described below with reference to FIG. FIG. 10 is a simplified diagram used for explaining the process of forming the storage node electrode, and a part of the structure shown in FIG. 9 described above is extracted and described.

That is, after the interlayer insulating film 58 is formed, a contact hole 68 for contacting the source region 55 is formed in the interlayer insulating film 58. The contact hole 68 is formed such that the upper opening diameter is wider by etching the interlayer insulating film 58 in two steps using two resist masks having different opening diameters.

Then, as shown in FIG. 10A, a conductive film 69A made of a polysilicon film or the like is formed on the interlayer insulating film 58 including the inside of the contact hole 68.

The conductive film 69A is polished to a predetermined position (refer to the polished surface AA) by using the CMP technique.
As shown in FIG. 10B, adjacent storage node electrodes 69 are separated from each other.

As described above, when a cylindrical storage node electrode is formed by such a method, it is necessary to invest in equipment for a CMP apparatus for pattern separation of a polysilicon film using the CMP technique. there were.

That is, in the existing process of embedding the conductive film 69A and the etch-back process of the conductive film 69A, the conductive film 69A at the bottom of the contact hole is simultaneously etched as shown in FIG. 10C. ,
It was necessary to introduce CMP technology.

However, if such a CMP equipment is newly introduced, the manufacturing cost jumps and the product unit price increases.

Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device in which a storage node electrode capable of increasing the capacitance of a capacitor can be manufactured by conventional equipment.

[0015]

SUMMARY OF THE INVENTION Accordingly, a method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming a gate electrode formed on a semiconductor substrate via a gate oxide film on a surface of the substrate so as to be adjacent to the gate electrode; In a device having a formed diffusion layer and a cell capacitor in contact with one of the diffusion layers, after forming a contact hole on the diffusion layer through an interlayer insulating film and forming a contact hole having a large opening diameter on the upper portion thereof, The first contact hole having a thickness that does not completely fill the contact hole.
Is formed. Next, after forming an insulating film on the first film so as not to completely fill the inside of the contact hole, the insulating film is etched back to leave a film only on the side wall of the contact hole. Subsequently, after a second film is formed on the first film with a thickness that completely fills the inside of the contact hole, the second film is etched back to leave a film only in the contact hole. Then, the insulating film in the contact hole is removed by etching to form a storage node electrode composed of the first and second films.

By forming the interlayer insulating film in the contact hole, the first film formed on the bottom of the contact hole in the subsequent etch back process of the first and second films. Is not etched, so that a cylindrical storage node electrode can be formed without using the CMP technique.

Further, in the method of manufacturing a semiconductor device according to the present invention, after the contact is made on the diffusion layer via an interlayer insulating film and a contact hole having a large opening diameter is formed thereon, the inside of the contact hole is completely removed. First with a film thickness that will not fill
Is formed. Next, after forming an insulating film on the first film so as not to completely fill the inside of the contact hole, the insulating film is etched back to leave a film only on the side wall of the contact hole. Subsequently, after forming an insulating film on the first film so as not to completely fill the inside of the contact hole, the insulating film is etched back to leave a film only on the side wall of the contact hole. Subsequently, after forming a second film on the first film with a thickness that does not completely fill the inside of the contact hole, the second film is etched back and the insulating film remaining in the contact hole is formed. A film is left only on the side wall of the film. And etching the insulating film in the contact hole to form a storage node electrode composed of the first and second films.

By forming the interlayer insulating film in the contact hole, the first film formed on the bottom of the contact hole in the subsequent etch-back process of the first and second films. Is not etched, so that a cylindrical storage node electrode can be formed without using the CMP technique. Furthermore, since the second film is formed so as not to completely fill the contact hole, the surface area of the second film erected in the cylinder is increased, and the capacitor capacity is further increased. Can be achieved.

It is characterized in that the insulating film is an NSG film or a TEOS film formed by a normal pressure CVD method.

In the cleaning step, the interlayer insulating film is formed of a first insulating film having a low etching rate and a second insulating film having a high etching rate, and a contact hole is formed in the interlayer insulating film. The opening diameter of the contact hole formed in the second insulating film is formed to be wider, and the capacitance of the capacitor can be further increased.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate of one conductivity type, for example, a P-type, on which an element isolation film 2 and a gate oxide film 3 are formed. Gate electrode 4 and an N-type source electrode formed on the surface of the substrate so as to be adjacent to the gate electrode 4.
A drain region 5, a bit line 7 contacting on the drain region 5, and a cell capacitor (storage node electrode 9, capacitance insulating film 1
0, the cell plate electrode 11. ) Constitute a memory cell transistor of a dynamic random access memory (hereinafter, referred to as DRAM).
Here, 6, 8 and 12 are interlayer insulating films, respectively, and 13 is a metal wiring formed on the interlayer insulating film 12. Note that the storage node electrode 9 is a so-called cylindrical storage node electrode, and this structure increases the capacitance of the capacitor.

Hereinafter, a method of forming the cylindrical storage node electrode 9 which is a feature of the present invention will be described with reference to FIGS. FIGS. 2 to 4 are simplified drawings used to explain the process of forming the storage node electrode 9. A part of the structure shown in FIG. 1 described above (after the interlayer insulating film 8 is formed, (Until the storage node electrode 9 is formed on the source region 5 via the insulating film 8).

First, as shown in FIG. 2A, a contact hole 20 is formed in the interlayer insulating film 8A. The contact hole 20 is formed such that the upper opening diameter is wider by etching the interlayer insulating film 8A twice using two resist masks having different opening diameters.
The dimensions of the contact hole 20 are, for example, height 40
The width is 0 to 800 nm, the lower width is 100 to 400 nm, and the upper width is 500 to 1000 nm.

Next, as shown in FIG. 2B, a first film 9A for forming a storage node electrode made of a polysilicon film or the like is formed on the source region 5 (see FIG. 1) through the contact hole 20. It is formed with a thickness of about 50 to 200 nm.

Further, as shown in FIG. 3A, an insulating film 21 is formed on the first film 9A with a thickness of about 100 to 150 nm so that the contact hole 20 is not completely filled. Then, the insulating film 21 is etched back,
As shown in FIG. 3B, the insulating film 21A is formed only on the side wall of the first film 9A formed in the contact hole 20.
Is left behind. The insulating film 21 is an NSG film or a TEOS film formed by a normal pressure CVD method.

Subsequently, as shown in FIG.
The second film 9B made of a polysilicon film is formed on the film 9A of a thickness of about 50 so as to completely fill the inside of the contact hole 20.
It is formed with a thickness of about 100 nm.

Then, the second and first films 9B, 9A
Is etched back to a predetermined position, and furthermore, the portions of the insulating films 8A and 21A indicated by the dotted lines in FIG. 4B are removed by etching, so that the first and second films 9A as shown in FIG. , 9B are formed. Incidentally, the storage node electrode 9 is shown in FIG.
As shown in (a), the second film 9B remains at the center thereof, so that the capacitor capacity can be further increased.

The first and second films 9A and 9B constituting the storage node electrode 9 are made conductive by ion-implanting N-type impurities (for example, phosphorus ions). Furthermore, for example, a conductive film made of a so-called doped polysilicon film in which PH ₃ is doped during film formation may be used.

As described above, in the manufacturing method of the present invention, by forming the insulating film 21 in the contact hole 20, the subsequent second and first films 9B,
In the etch-back process of 9A, the insulating film 21 serves as an etching mask and the first film 9A formed at the bottom of the contact hole 20 is not etched, so that the existing process technology can be used without using the CMP technology. Thus, a cylindrical storage node electrode can be formed.

As shown in FIG. 1, a capacitor insulating film 10 (for example, a silicon nitride film or a laminated film of a silicon oxide film and a silicon nitride film, or a silicon oxide film, a silicon nitride film and a silicon oxide film) is formed on the storage node electrode 9. A film with a thickness of about 4 to 5 nm,
A cell plate electrode 11 made of a conductive film (for example, a polysilicon film made conductive with a thickness of about 50 to 150 nm) is formed thereon to form a cell capacitor. Then, an interlayer insulating film 12 made of a CVD oxide film and a BPSG film or the like is formed on the entire surface to a thickness of about 800 to 1200 nm, and a contact hole (not shown) is formed in the interlayer insulating film 12 to contact the source / drain region 5. Is formed, a tungsten plug is buried in the contact hole via a barrier metal film (for example, a laminated film of a titanium film and a titanium nitride (TiN) film), and an Al alloy (for example, Al-Si, Al- Cu, Al-Si-C
u) etc. of the metal wiring (M) 13 of about 300 to 8
The semiconductor device is formed with a thickness of 00 nm and a jacket film is formed, although the description shown below is omitted.

As described above, in the present invention, a conductive film is buried in a contact hole, which is an existing process, without using a CMP technique, and a cylindrical storage node electrode is formed by an etch-back process of the conductive film. be able to. Therefore, an increase in cost due to investment in new equipment can be suppressed.

Hereinafter, a second embodiment of the present invention will be described with reference to FIGS.

Here, the features of the second embodiment (see FIG. 6) will be described in detail later. However, when the same manufacturing steps as in the first embodiment are performed, the first embodiment (see FIG. 6) will be described. This means that the surface area of the conductive film constituting the cylindrical storage node electrode is increased as compared with FIG. 4).

First, as shown in FIG. 5A, a contact hole 30 is formed in the interlayer insulating film 8A. The contact hole 30 is formed such that the upper opening diameter is wider by etching the interlayer insulating film 8A twice using two resist masks having different opening diameters.
The dimensions of the contact holes are assumed to be equivalent to those of the first embodiment.

Next, as shown in FIG. 5B, a first film 19A for forming a storage node electrode made of a polysilicon film or the like is formed on the source region 5 (see FIG. 1) through the contact hole 30. It is formed with a thickness of about 50 to 200 nm.

Further, as shown in FIG. 6A, an insulating film 31 having a thickness of about 100 to 150 nm is formed on the first film 19A so that the contact hole 30 is not completely filled. Then, the insulating film 31 is etched back to leave the insulating film 31A only on the side wall of the first film 19A formed in the contact hole 30, as shown in FIG. 6B. The insulating film 31 is made of a normal pressure CV.
An NSG film or a TEOS film formed by the method D.

Subsequently, as shown in FIG.
A second film 19B made of a polysilicon film is formed to a thickness of about 50 to 100 nm on the film 19A so that the inside of the contact hole 30 is not completely filled.

Then, the second and first films 9B, 9A
Is etched back to a predetermined position, and furthermore, the portions of the insulating films 8A and 31A indicated by dotted lines in FIG. 6B are removed by etching, so that the first and second films 19A and 19A as shown in FIG. , 19B are formed. The storage node electrode 19
As shown in FIG. 7 (b), the second film 19B is paired and left at the center of the film as shown in FIG. 7B, so that the capacitance of the capacitor can be further increased as compared with the first embodiment. ing.

The first and second films 19A and 19B constituting the storage node electrode 19 are ion-implanted with N-type impurities (for example, phosphorus ions) to achieve conductivity. Furthermore, for example, during film formation, PH
A conductive film made of a so-called doped polysilicon film doped with ₃ may be used.

As described above, in the manufacturing method of the present invention, the insulating film 31 is formed in the contact hole 30 so that the subsequent second and first films 19 are formed.
B, 19A in the etch-back process.
1 serves as an etching mask and the first film 19A formed at the bottom of the contact hole 30 is not etched, so that a cylindrical storage node electrode can be formed by an existing process technology without using CMP technology. can do.

Further, according to the present invention, the conductive films 9B and 19B can be formed inside the cylinder when the opening diameter of the contact hole is the critical dimension of the lithography technique.
Fine processing that exceeds the exposure capability of lithography technology becomes possible.

Further, a third embodiment which enables fine processing beyond the pattern processing capability of the lithography technique will be described with reference to FIG.

The feature of this embodiment is that the interlayer insulating films 6 and 6 are used.
8 (8B) is a first insulating film having a low etching rate (for example, an NSG film) and a second insulating film having a high etching rate (for example, a BPSG film, particularly a commonly used BP film).
A BPSG film having a higher impurity concentration (boron ion or phosphorus ion) of about 5% / weight than the SG film is preferable. ), And the interlayer insulating films 6, 8 (8
In the cleaning step after forming the contact hole in B), the opening diameter of the contact hole formed in the second insulating film 8 (8B) is configured to be wider, thereby further increasing the capacitance of the capacitor. It is possible to increase.

FIG. 8 is a drawing of the steps shown in FIG. 2 in the first embodiment.

First, as shown in FIG. 8A, contact holes 20 are formed in the interlayer insulating films 6, 8B. This contact hole 20 is formed by two resist masks (P
By etching the interlayer insulating films 6 and 8B twice using R), the upper opening diameter is formed wider.

Next, after removing the resist mask, a cleaning process is performed as a pre-process for forming a polysilicon film. At this time, as shown in FIG.
Since B has a higher impurity concentration than a normal BPSG film, this cleaning (for example, wet etching with hydrofluoric acid) causes the BPSG film 8B to recede, and the opening diameter of the upper part of the contact hole 20 becomes wider. Contact hole 2
OA is formed.

Then, as shown in FIG. 8C, a first film 29A for forming a storage node electrode made of a polysilicon film or the like is formed on the source region 5 (see FIG. 1) through the contact hole 20A. It is formed with a thickness of 50 to 200 nm.

As described above, in the present embodiment, the interlayer insulating film 8
By forming B with a film having a high wet etching rate, if the contact hole 20 has the exposure limit dimension, pattern processing exceeding the exposure limit becomes possible. By applying this, it is possible to further increase the capacitance of the capacitor.

Although not described below, a cylindrical storage node electrode is formed by performing the steps of FIGS. 3 and 4 in the first embodiment. In the above description, the description has been made in the form applied to the first embodiment. However, it is needless to say that the present invention can be applied to the second embodiment.

In the description of the present embodiment, an example is described in which the present invention is applied to a DRAM having a COB (capacitor over bit line) structure. However, the present invention is not limited to this, and a CUB (capacitor under bit line) structure is employed. May be applied to the DRAM.

[0052]

According to the present invention, by forming an interlayer insulating film in a contact hole, the storage node formed at the bottom of the contact hole can be formed in a subsequent etch-back step of the storage node electrode forming film. Since the electrode forming film is not etched, a cylindrical storage node electrode can be formed by an existing process that does not use the CMP technique. Therefore, an increase in cost due to investment in new equipment can be suppressed.

Further, an interlayer insulating film is formed of a first insulating film having a low etching rate and a second insulating film having a high etching rate, and in a cleaning step after forming a contact hole in the interlayer insulating film, By making the opening diameter of the contact hole formed in the second insulating film wider, pattern processing exceeding the exposure limit can be performed, and the capacitance of the capacitor can be further increased.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a plan view showing a storage node electrode of the present invention.

FIG. 8 is a sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 9 is a sectional view showing a conventional semiconductor device.

FIG. 10 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

Claims (4)

[Claims] 1. A cell in contact with a gate electrode formed on a semiconductor substrate via a gate oxide film, a diffusion layer formed in a surface layer of the substrate adjacent to the gate electrode, and one of the diffusion layers. A method of manufacturing a semiconductor device having a capacitor, wherein the step of contacting the diffusion layer via an interlayer insulating film to form a contact hole having a wide upper portion; Forming a first film on the interlayer insulating film; forming an insulating film on the first film with a thickness that does not completely fill the inside of the contact hole; and etching back the insulating film to form the first film. Leaving a film only on the side wall of the contact hole via the first film; forming a second film on the first film with a thickness that completely fills the inside of the contact hole; Etch back Forming a storage node electrode composed of the first and second films, comprising: a step of forming a film remaining only in the contact hole by etching; and a step of etching and removing the insulating film in the contact hole. A method of manufacturing a semiconductor device. 2. A cell in contact with a gate electrode formed on a semiconductor substrate via a gate oxide film, a diffusion layer formed on the surface of the substrate adjacent to the gate electrode, and one of the diffusion layers. A method of manufacturing a semiconductor device having a capacitor, wherein the step of contacting the diffusion layer via an interlayer insulating film to form a contact hole having a wide upper portion; Forming a first film on the interlayer insulating film; forming an insulating film on the first film with a thickness that does not completely fill the inside of the contact hole; and etching back the insulating film to form the first film. Leaving a film only on the side wall of the contact hole via the first film; forming a second film on the first film with a thickness that does not completely fill the inside of the contact hole; Etchba Forming a storage node electrode composed of the first and second films, comprising: a step of leaving a film only in the contact hole by etching; and a step of etching and removing the insulating film in the contact hole. A method for manufacturing a semiconductor device, comprising: 3. The method according to claim 1, wherein the insulating film is an NSG film or a TEOS film formed by a normal pressure CVD method. 4. A cleaning step, wherein said interlayer insulating film is formed of a first insulating film having a low etching rate and a second insulating film having a high etching rate, and wherein a cleaning step is performed after forming a contact hole in said interlayer insulating film. 3. The method according to claim 1, wherein an opening diameter of the contact hole formed in the second insulating film is wider.