TW202425065A - Wafer edge processing device and operating method capable of accurately controlling the size of wafer edge etching and improving the yield and production efficiency of wafer edge etching - Google Patents

Abstract

The present invention provides a wafer edge processing device, which includes a reaction chamber. A lower electrode assembly in the reaction chamber includes a lower edge ring and a base, and an upper electrode assembly in the reaction chamber includes an upper edge ring and an upper cover plate. A device under test is a calibration wafer or a wafer to be processed. The device under test includes a first device under test. An edge area of the device under test is located between the upper edge ring and the lower edge ring. The wafer edge processing device further includes: a first group of sensors disposed in the upper electrode assembly, in which the first group of sensors includes at least three sensors arranged at intervals along a circumferential direction of the upper electrode assembly for measuring a first distance between the first group of sensors and the first device under test; and a calculation unit configured to determine whether the first device under test is parallel to the upper edge ring based on a measurement result of the first group of sensors. The present invention also provides an operating method of a wafer edge processing device.

Description

Wafer edge processing device and operation method

The present invention relates to the field of semiconductor equipment, and more particularly to a wafer edge processing device and an operating method.

In semiconductor manufacturing, there are many processes involved, and each process is completed by certain equipment and processes. Among them, etching process is an important process in semiconductor manufacturing, such as plasma etching process. Plasma etching process uses reactive gas to generate plasma after obtaining energy, and etches the wafer to be processed through physical bombardment and chemical reaction.

During the plasma etching process, the etching conditions at the edge of the wafer are quite different from those at the center of the wafer (including plasma density distribution, RF electric field, temperature distribution, etc.). In view of this, the industry has introduced the edge etching process. Specifically, the wafer is placed in the edge etching device, and the plasma generated etches the edge of the wafer, while trying to avoid etching the center of the wafer.

The edge etching device includes a vacuum reaction chamber, in which an upper electrode assembly and a lower electrode assembly are arranged. The wafer to be processed is transferred into the reaction chamber and placed on the lower electrode assembly. Usually, the lower electrode assembly is fixed, so the parallelism and concentricity between the wafer and the upper electrode assembly determine the size range and effect of the wafer edge etching. The size deviation of the edge etching can be found by judging the pattern offset after the wafer edge is etched, and then the upper electrode assembly is adjusted. This is repeated many times until the wafer edge etching effect meets the requirements. The wafers used in the adjustment process will be scrapped, which not only increases the production cost of the wafer but also reduces the production efficiency of the wafer.

During edge etching, the spacing between the wafer and the top electrode assembly is usually small. Some wafers will be slightly warped and/or bulged during certain processes (e.g., deposition, etc.). If the wafer is too uneven, it may accidentally hit the top electrode assembly, thus damaging the wafer and/or the top electrode assembly. Therefore, it is necessary to detect the degree of wafer warpage in order to set a reasonable spacing between the top electrode assembly and the wafer before the edge etching process begins.

How to measure the parallelism and concentricity between the wafer to be processed and the upper edge ring, as well as the curvature of the wafer without opening the reaction chamber, so as to improve the yield of wafer edge etching, is a problem that urgently needs to be solved in the industry.

The purpose of the present invention is to provide a wafer edge processing device and operation method, which can ensure at least one of the parallelism and concentricity of the wafer and the upper edge ring, accurately control the size of the wafer edge etching, and improve the yield and production efficiency of the wafer edge etching. At the same time, the present invention can also detect the degree and direction of the warp of the wafer, which is helpful to set a reasonable distance between the upper electrode assembly and the wafer.

In order to achieve the above-mentioned purpose, the present invention provides a wafer edge processing device, the wafer edge processing device includes a reaction chamber, the reaction chamber is provided with a lower electrode assembly and an upper electrode assembly; the lower electrode assembly is used to carry a test piece, the lower electrode assembly includes a lower edge ring and a base, the upper electrode assembly includes an upper edge ring and an upper cover plate arranged opposite to the base; the test piece is a calibration wafer or a wafer to be processed, the test piece includes a first test piece, and the edge area of the test piece is located between the upper edge ring and the lower edge ring; The wafer edge processing device also includes: A first set of sensors is arranged in the upper electrode assembly, the first set of sensors includes at least three sensors arranged at intervals along the circumference of the upper electrode assembly, and is used to measure the first distance between the first set of sensors and the first test piece, and the measured multiple first distance values are used as the first measurement data; A calculation unit determines whether the first test piece and the upper edge ring are parallel based on the first measurement data, and when they are parallel, the difference between the multiple first distance values is less than the first preset threshold.

Optionally, the first set of sensors are located in the upper edge ring.

Optionally, an edge region of at least one surface of the first test piece is a planar structure.

Optionally, the piece to be tested further includes a second piece to be tested, which is parallel to the upper edge ring, and the first group of sensors is further used to measure a second distance between the first group of sensors and a characteristic structure of the second piece to be tested, and the measured multiple second distance values are used as second measurement data, wherein the first piece to be tested and the second piece to be tested are the same piece to be tested or different pieces to be tested, and the characteristic structure is a local structure including a surface inclined relative to the upper edge ring; the calculation unit determines whether the upper edge ring and the second piece to be tested are concentric based on the second measurement data, and when they are concentric, the difference between the multiple second distance values is less than a second preset threshold.

Optionally, an edge region of at least one surface of the second test piece includes the characteristic structure.

Optionally, the first device to be tested and the second device to be tested are both first calibration wafers, an edge region of one surface of the first calibration wafer is a planar structure, and an edge region of another surface includes the characteristic structure.

Optionally, the characteristic structure is a chamfered structure or a V-groove structure.

Optionally, the first group of sensors are located in the upper cover.

Optionally, a central area of at least one surface of the first test piece is a planar structure.

Optionally, the test piece further includes a third test piece, which is parallel to the upper edge ring, and the first group of sensors is further used to measure the distance between the first group of sensors and a characteristic structure of the third test piece, and the measured multiple third distance values are used as third measurement data, wherein the first test piece and the third test piece are the same test piece or different test pieces, and the characteristic structure is a local structure including a surface inclined relative to the upper edge ring; the calculation unit determines whether the upper edge ring and the third test piece are concentric based on the third measurement data, and when they are concentric, the difference between each two of the multiple third distance values is less than a third preset threshold.

Optionally, a central area of at least one surface of the third test piece includes the characteristic structure.

Optionally, the first DUT and the third DUT are both second calibration wafers, a central area of one surface of the second calibration wafer is a planar structure, and a central area of another surface includes the characteristic structure.

Optionally, the characteristic structure is an inverted frustum-shaped through hole, an inverted frustum-shaped blind hole, or an annular groove with a V-shaped cross section.

Optionally, the first piece to be tested is parallel to the upper edge ring, the first piece to be tested includes a characteristic structure, the characteristic structure is a local structure including a surface inclined relative to the upper edge ring, and the wafer edge processing device further includes: A second group of sensors arranged in the upper electrode assembly, the second group of sensors including at least three sensors arranged at intervals along the circumference of the upper electrode assembly, used to measure the fourth distance between the second group of sensors and the characteristic structure of the first piece to be tested, and the measured multiple fourth distance values are used as fourth measurement data; The calculation unit determines whether the first piece to be tested and the upper edge ring are concentric based on the fourth measurement data, and when they are concentric, the difference between the multiple fourth distance values is less than the fourth preset threshold.

Optionally, the first group of sensors is located in the upper edge ring, and the second group of sensors is located in the upper cover plate; or, the first group of sensors is located in the upper cover plate, and the second group of sensors is located in the upper edge ring.

Optionally, the edge region of the first device to be tested is a planar structure, and the central region of the same surface includes the characteristic structure; or, the edge region of the first device to be tested includes the characteristic structure, and the central region of the same surface is a planar structure.

Optionally, the calculation unit determines at least one of the warp direction of the wafer to be processed and calculates the warp of the wafer to be processed based on the distance data from the wafer to be processed measured by the first group of sensors and the second group of sensors.

Optionally, the wafer edge processing device is an edge etching device or an edge deposition device.

Optionally, at least one of the upper cover plate and the base has a concave surface.

The present invention also provides an operating method of the wafer edge processing device as described in the present invention, the operating method comprising: Step S1, the computing unit determines whether the test piece is parallel to the upper edge ring based on the first measurement data, and adjusts at least one of the upper electrode assembly and the lower electrode assembly according to the determination result until the two are parallel.

Optionally, the operation method further includes after step S1: Step S2, the computing unit determines whether the DUT is concentric with the upper edge ring based on the second measurement data, the third measurement data or the fourth measurement data, and adjusts at least one of the upper electrode assembly and the lower electrode assembly according to the determination result until the two are concentric; Wherein, the second measurement data is composed of a plurality of second distance values, and the second distance value is the second distance between the characteristic structure between the first group of sensors and the second DUT measured by the first group of sensors when the first group of sensors is located in the upper edge ring, and the second DUT is parallel to the upper edge ring; The third measurement data is composed of a plurality of third distance values, the third distance value is the third distance between the first group of sensors and the characteristic structure of the third test piece measured by the first group of sensors when the first group of sensors is located in the upper cover plate, and the third test piece is parallel to the upper edge ring; The fourth measurement data is composed of a plurality of fourth distance values, the fourth distance value is the fourth distance between the second group of sensors and the characteristic structure of the first test piece measured by the second group of sensors in the upper electrode assembly, and the first test piece is parallel to the upper edge ring; The characteristic structure is a local structure including a surface inclined relative to the upper edge ring.

Optionally, the operation method further includes after step S1: Step S3, the calculation unit adjusts the distance between the upper electrode assembly and the object to be tested based on the first measurement data measured after parallelization.

Optionally, the operation method further includes after step S2: Step S4, the calculation unit adjusts the distance between the upper electrode assembly and the device to be tested based on at least one of the first measurement data, the second measurement data, the third measurement data and the fourth measurement data.

Compared with the prior art, the wafer edge processing device and operation method of the present invention have the following beneficial effects:

1) The present invention uses the calibration wafer and/or the wafer to be processed as the test piece, fully utilizing the planar structure and characteristic structure of the test piece itself, and automatically measures the parallelism and concentricity between the test piece and the upper edge ring without opening the vacuum reaction chamber, thereby achieving precise control of the size of the wafer edge etching and ensuring the accuracy of the wafer edge etching. The present invention is not limited by the wafer type and has strong applicability. The present invention does not require wafer tape-out testing, nor does it require the pattern offset after the wafer edge is etched to detect the size deviation of the etching. Therefore, the present invention greatly saves the production cost of wafer edge etching and improves the production efficiency of wafer edge etching.

2) The present invention can also instantly determine the degree and direction of the wafer warp without opening the vacuum reaction chamber. Based on the results of the present invention on the degree and direction of the wafer warp, a reasonable distance can be set between the upper electrode assembly and the wafer before the edge etching process begins, which not only effectively prevents the wafer from hitting the upper electrode assembly during the process, but also can avoid etching the central area of the wafer as much as possible.

3) In the present invention, a set of sensors used to measure parallelism can also be used to measure concentricity; multiple sets of sensors for measuring parallelism and concentricity can be used together to measure the degree and direction of warp of a wafer; by reusing sensors, the number of sensors used is reduced, the production cost is reduced, and the complexity of installing sensors is also reduced.

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making progressive labor are within the scope of protection of the present invention.

It should be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and/or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or combinations thereof.

It should also be understood that the terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit the present application. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include plural forms unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" used in this application specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

As used in this specification and the appended claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

In addition, in the description of the present application, the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

Embodiment 1

1 is a schematic diagram of a wafer edge processing device 10 of the present invention. The wafer edge processing device 10 is a plasma edge etching device, which includes: a vacuum reaction chamber 100, a calculation unit (not shown in the figure) and a first set of sensors 110.

As shown in FIG1 , a wafer transfer port 120 is provided on the side wall of the reaction chamber 100 for transferring the wafer W between the inside and outside of the reaction chamber 100. A lower electrode assembly and an upper electrode assembly are provided in the reaction chamber, at least one of which is movable. Next, the present invention is introduced by moving the upper electrode assembly, but it is understandable that the lower electrode assembly can also be moved, or both the upper electrode assembly and the lower electrode assembly can be moved. The lower electrode assembly includes: a base 131 and a lower edge ring 132. The base 131 is provided at the bottom of the reaction chamber, and the transfer structure places the wafer W to be processed or the calibration wafer on the lower electrode assembly through the wafer transfer port 120. The wafer to be processed W or the calibration wafer as the test piece can be placed on the base 131 or the lower edge ring 132 or other parts of the lower electrode assembly, and the present invention is not limited to this. Next, the present invention is introduced by taking the test piece placed on the base 131 as an example.

The lower edge ring 132 surrounds the periphery of the base 131. The upper electrode assembly is located at the top of the reaction chamber 100, and includes: an upper cover plate 141 and an upper edge ring 142. In one embodiment, the upper cover plate 141 is a dielectric plate. The upper cover plate 141 is located above the base 131 and opposite to the base 131, and the upper edge ring 142 surrounds the periphery of the upper cover plate 141 and is concentric with the upper cover plate 141. The upper electrode assembly in this embodiment also includes an upper facility plate 143, and the upper cover plate 141 and the upper edge ring 142 are installed at the bottom of the upper facility plate 143. Optionally, the lower surfaces of the upper cover plate 141 and the upper edge ring 142 are parallel. The wafer W is virtually divided into a central region and an edge region surrounding the central region. The edge region of the wafer W is located between the upper edge ring 142 and the lower edge ring 132 .

The processing gas diffuses to the edge area of the wafer W through the edge of the upper electrode assembly. At least one RF power source (not shown in the figure) is applied to at least one of the upper edge ring 142 and the lower edge ring 132 through a matching network (not shown in the figure), thereby generating a large electric field between the upper edge ring 142 and the lower edge ring 132 to dissociate the processing gas into plasma. The plasma contains a large number of active particles such as electrons, ions, excited atoms, molecules and free radicals. The above active particles can undergo a variety of physical bombardments and/or chemical reactions with the edge area of the wafer W to be processed, so that the morphology of the edge area of the wafer W changes, that is, the edge etching process is completed.

As shown in FIG. 1 , during the wafer edge etching process, the upper cover plate 141 and the wafer W have a small gap (e.g., less than or equal to 20 mm, which is only an example and not a limitation of the present invention) to reduce the plasma entering between the upper cover plate 141 and the wafer W and avoid etching the central area of the wafer W. In this embodiment, a first annular flange 1421 is provided at the bottom of the upper edge ring 142 along the circumferential direction of the upper edge ring 142 . Along the circumferential direction of the lower edge ring 132, a second annular flange 1321 (opposite to the first annular flange 1421) is provided at the top of the lower edge ring 132, and the edge area of the wafer W can be etched outside the first annular flange 1421 and the second annular flange 1321. The first annular flange 1421 and the second annular flange 1321 can also prevent the outer periphery of the bottom of the upper cover plate 141 and the outer periphery of the top of the base from being exposed to plasma. In a preferred embodiment, the bottom surface of the first annular flange 1421 is flush with the bottom surface of the upper cover plate 141 , and the top surface of the second annular flange 1321 is flush with the top surface of the base 131 .

The parallelism and concentricity between the wafer W and the upper electrode assembly determine the range and effect of the wafer edge etching. Therefore, it is necessary to measure the parallelism and concentricity between the upper electrode assembly and the wafer W placed on the base 131 before the edge etching begins, and adjust at least one of the upper electrode assembly and the lower electrode assembly based on the measurement results to achieve precise control of the size of the wafer edge etching and ensure the accuracy of the wafer edge etching.

In the present invention, at least one of the wafer to be processed W and the calibration wafer is used as a test piece, and the test piece is placed on the base 131 through a conveying mechanism (only one test piece is placed on the base 131 at a time), and the distance between the test pieces and the sensors is measured by a sensor. Based on the measurement results, it is determined whether the test piece on the base 131 is parallel/concentric with the upper electrode assembly. It is worth mentioning that the sensor claimed in the present invention measures the distance between the device to be tested and the sensor, and judges whether the device to be tested on the lower electrode assembly is parallel/concentric with the upper electrode assembly based on the measurement result, including measuring the distance between the device to be tested and the sensor by the sensor, converting the distance into the distance between any part of the upper electrode assembly (such as the upper cover plate and the upper edge ring, etc.) and the device to be tested, and then judging whether the device to be tested and the upper electrode assembly are parallel/concentric based on the converted distance.

It should be noted that the difference in quality and size between the calibration wafer and the wafer to be processed W is small enough, and the calibration wafer is placed on the base 131 by the conveying mechanism, and the placement position of the calibration wafer corresponds to the placement position of the wafer to be processed W on the base 131. The placement position correspondence means that the running trajectory of the conveying mechanism when conveying the calibration wafer is the same as the running trajectory when conveying the wafer to be processed W. Therefore, when it is determined based on the measurement result of the calibration wafer that the calibration wafer is parallel/concentric with the upper electrode assembly, it can be known that the wafer to be processed W subsequently conveyed to the base 131 is also parallel/concentric with the upper electrode assembly.

In this embodiment, the first group of sensors 110 is disposed in the upper edge ring 142. The first group of sensors 110 includes at least three sensors that are evenly spaced along the circumference of the upper electrode assembly. Optionally, multiple sensors can also be unevenly spaced along the circumference of the upper electrode assembly. The distances between the first test piece 161 and the second test piece 162 transmitted to the base 131 and each sensor are measured by the first group of sensors 110. The first test piece 161 and the second test piece 162 are different test pieces.

The edge area of at least one surface of the first test piece 161 has a planar structure. In this embodiment, as shown in FIG. 2 , the first test piece 161 has a first surface 1611 and a second surface 1612 relative to each other, and the edge areas of the first surface 1611 and the second surface 1612 both have a planar structure. When the second surface 1612 is in contact with the base 131, the measurement points of each sensor fall on the planar structure of the edge area of the first surface 1611. Alternatively, the first surface 1611 is a plane in contact with the base 131, and the measurement points of each sensor fall on the planar structure of the edge area of the second surface 1612. The first group of sensors 110 obtains a plurality of first distance values by measuring the distance of the planar structure, and the measured plurality of first distance values are used as the first measurement data.

The calculation unit determines whether the first test piece 161 is parallel to the upper edge ring 142 based on the first measurement data, and adjusts the upper electrode assembly according to the determination result until the first test piece 161 is parallel to the upper edge ring 142. When parallel, the difference between any two first distance values in the first measurement data is less than the first preset threshold. In one embodiment, the first preset threshold is 0.5 mm; more preferably, the first preset threshold is 0.1 mm. The above first preset threshold is not a limitation of the present invention, and the technician can set the first preset threshold according to actual needs. In some embodiments, the computing unit further adjusts the distance between the upper edge ring 142 and the first piece to be tested 161 based on the first measurement data obtained after the first piece to be tested 161 is parallel to the upper edge ring 142. The adjusted distance can reduce the plasma entering between the upper cover plate 141 and the wafer W to be processed, and reserve space for possible deformation of the wafer W to be processed.

The second test piece 162 has a first surface 1621 and a second surface 1622 opposite to each other. The edge region of at least one surface of the second test piece 162 has a characteristic structure, and the characteristic structure is a local structure containing a surface that is inclined relative to the upper edge ring when the test piece is parallel to the upper edge ring as a whole. The characteristic structure in this embodiment is a chamfered structure. In this embodiment, as shown in FIG. 3, the edge regions of the first surface 1621 and the second surface 1622 both have a rounded structure. In another embodiment, the edge regions of the first surface 1621 and the second surface 1622 both have a chamfered structure.

After adjusting the upper electrode assembly so that the first DUT 161 is parallel to the upper edge ring 142, it is easy to understand that the second DUT 162 subsequently transferred to the base 131 is also parallel to the upper edge ring 142. The first group of sensors 110 is also used to measure the second distance between each sensor and the characteristic structure of the second DUT 162. When the first surface 1621 of the second DUT 162 contacts the base 131, the measurement points of each sensor in the first group of sensors 110 all fall on the chamfered structure of the second surface 1622. Or when the second surface 1622 of the second DUT 162 contacts the base 131, the measurement points of each sensor in the first group of sensors 110 all fall on the chamfered structure of the first surface 1621. The first set of sensors 110 measures a plurality of second distance values by measuring the distance of the chamfered structure, and the plurality of second distance values measured are used as the second measurement data. The calculation unit determines whether the upper edge ring 142 and the second test piece 162 are concentric based on the second measurement data. When they are concentric, the difference between any two second distance values in the second measurement data is less than the second preset threshold. In one embodiment, the second preset threshold is 0.5 mm; more preferably, the second preset threshold is 0.1 mm. The above second preset threshold is not a limitation of the present invention, and the technical personnel can set the second preset threshold according to actual needs.

In this embodiment, a standard value is stored in the internal memory of the calculation unit. After obtaining the second distance value measured by each sensor on the chamfered structure of the second test piece 162, the calculation unit first calculates the difference between each second distance value and the standard value, thereby obtaining the approximate offset direction and offset of the upper edge ring 142 relative to the second test piece 162. For example, as shown in FIG3, if the second distance value measured by a sensor at point a is greater than the standard value, and the second distance value measured by another sensor at point b is less than the standard value, the upper electrode assembly is translated toward the direction of sensor b.

In some embodiments, after the first DUT 161 is parallel to the upper edge ring 142, the computing unit does not adjust the distance between the upper electrode assembly and the first DUT 161. Instead, after the first DUT 161 is concentric with the upper edge ring 142, the computing unit adjusts the distance between the upper electrode assembly and the first DUT 161 based on the measured second measurement data.

In this embodiment, the first DUT 161 is a wafer to be processed W, and the second DUT 162 is a calibration wafer; or, the first DUT 161 is a calibration wafer, and the second DUT 162 is a wafer to be processed W; or, the first DUT 161 and the second DUT 162 are two calibration wafers with different structures; or, the first DUT 161 and the second DUT 162 are two wafers to be processed W with different structures.

This embodiment utilizes the structural features of the first test piece 161 and the second test piece 162 to automatically measure the parallelism and concentricity of the first test piece 161 and the second test piece 162 and the upper edge ring 142 without opening the vacuum reaction chamber 100, thereby accurately controlling the edge etching size of the wafer W to be processed and ensuring the accuracy of the edge etching. The present invention is not limited by the type of wafer and has strong applicability. The present invention does not require a wafer flow test, nor does it require the size deviation of the wafer edge etching to be discovered based on the pattern offset of the wafer W. Therefore, the present invention greatly saves the production cost of wafer edge etching and improves the production efficiency of wafer edge etching.

In this embodiment, the first set of sensors 110 can be used not only to measure parallelism but also to measure concentricity. By reusing sensors, the number of sensors used is reduced, the production cost is reduced, and the complexity of installing the sensors is also reduced.

Embodiment 2

In this embodiment, a first group of sensors 210 is provided in the upper edge ring of the upper electrode assembly. The first group of sensors 210 includes at least three sensors that are evenly spaced along the circumference of the upper electrode assembly. Optionally, multiple sensors can also be arranged unevenly spaced along the circumference of the upper electrode assembly. As shown in FIG4 , in this embodiment, the first test piece 261 has a first surface 2611 and a second surface 2612 that are opposite to each other, and the first surface 2611 and the second surface 2612 have different structures. The first group of sensors 210 respectively measures the distance values between the first surface 2611, the second surface 2612 and each sensor to determine the parallelism and concentricity between the first test piece and the upper edge ring.

As shown in FIG4 , the edge area of the first surface 2611 of the first test piece 261 is a plane structure, and the edge area of the second surface 2612 includes a characteristic structure. The characteristic structure in FIG4 is a chamfered structure. When measuring the parallelism between the first test piece 261 and the upper edge ring, the first test piece 261 is transferred to the base, and the second surface 2612 of the first test piece 261 is brought into contact with the base. The first set of sensors 210 measures the plane structure of the edge of the first surface to obtain a plurality of first distance values, and the plurality of first distance values are used as the first measurement data. Based on the first measurement data, it is determined whether the first test piece 261 is parallel to the upper edge ring. The upper electrode assembly is adjusted until the first test piece 261 is parallel to the upper edge ring, and the first test piece 261 is transferred out of the reaction chamber. Then the first test piece 261 is transferred into the reaction chamber again, and the first surface 2611 of the first test piece 261 is in contact with the base. The first set of sensors 210 measures the distance of the chamfered structure of the second surface edge to obtain multiple second distance values, and the multiple second distance values are used as second measurement data. The concentricity of the first test piece 261 and the upper edge ring is determined based on the second measurement data.

In some embodiments, the computing unit may further adjust the distance between the upper edge ring and the first device to be tested 261 based on first measurement data obtained after the first device to be tested 261 is parallel to the upper edge ring; or, adjust the distance between the upper electrode assembly and the first device to be tested 261 based on second measurement data obtained after the first device to be tested 261 is concentric with the upper edge ring.

In another embodiment, as shown in FIG. 5 , the characteristic structure of the edge region of the second surface 2612 is a V-groove 270. The plurality of V-grooves 270 are distributed along the circumferential direction of the first test piece 261, and the plurality of V-grooves 270 correspond to the plurality of sensors of the first set of sensors 210, respectively. The V-groove 270 has an inclined inner wall, and when the first surface 2611 contacts the base, the measurement point of the corresponding sensor falls on the inclined inner wall of the corresponding V-groove 270. Based on the second measurement data obtained by the first set of sensors 210 measuring the distance of the V-groove 270, the concentricity of the first test piece 261 and the upper edge ring is determined. In other embodiments, the V-groove 270 can be a continuous annular groove with a V-shaped cross section.

The first test piece 261 in this embodiment is a calibration wafer. In this embodiment, only one calibration wafer is needed to ensure that the wafer W to be processed subsequently transferred into the reaction chamber is parallel and concentric with the upper electrode assembly, thereby further saving production costs.

Embodiment 3

FIG6 is a schematic diagram of the wafer edge processing device 30 in this embodiment. In this embodiment, as shown in FIG6 , the first group of sensors 310 is disposed in the upper cover plate 341, and no sensor is disposed in the upper edge ring 342. The first group of sensors 310 includes at least three sensors that are evenly spaced along the circumference of the upper electrode assembly. Optionally, a plurality of sensors can also be arranged unevenly along the circumference of the upper electrode assembly. The distances between the first test piece 361 and the third test piece 363 transmitted to the base and each sensor are measured respectively by the first group of sensors 310. Among them, the first test piece 361 and the third test piece 363 are different test pieces.

As shown in FIG7 , the central area of at least one surface of the first test piece 361 is a planar structure. The first set of sensors 310 obtains a plurality of first distance values by measuring the distance of the planar structure, and the plurality of first distance values serve as the first measurement data. The calculation unit determines whether the first test piece is parallel to the upper cover plate based on the first measurement data. When they are parallel, the difference between any two first distance values in the first measurement data is less than the first preset threshold. In one embodiment, the first preset threshold is 0.5 mm; more preferably, the first preset threshold is 0.1 mm. The above first preset threshold is not intended to be a limitation of the present invention, and a technician may set the first preset threshold according to actual needs.

As shown in Fig. 8, the central area of at least one surface of the third test piece 363 includes a characteristic structure. The characteristic structure in this embodiment is a frustum-shaped through hole 3633. The characteristic structure in another embodiment is a frustum-shaped blind hole or a V-shaped annular groove.

After adjusting the upper electrode assembly so that the first test piece 361 is parallel to the upper cover plate 341, it is easy to understand that the third test piece 363 subsequently transmitted to the base is also parallel to the upper cover plate 341. The first group of sensors 310 also obtains multiple third distance values by measuring the third distance between each sensor and the characteristic structure of the third test piece 363, and the multiple third distance values are used as third measurement data. The calculation unit determines whether the upper cover plate 341 and the third test piece 363 are concentric based on the third measurement data. When they are concentric, the difference between the multiple third distance values in the third measurement data is less than the third preset threshold. In one embodiment, the third preset threshold is 0.5mm; more preferably, the third preset threshold is 0.1mm. The above third preset threshold is not a limitation of the present invention, and technical personnel can set the third preset threshold according to actual needs.

Since the upper cover plate 341 is concentric with the upper edge ring 342 , when the first DUT 361 is parallel to the upper cover plate 341 , the first DUT 361 is also parallel to the upper edge ring 342 ; when the third DUT 363 is concentric with the upper cover plate 341 , the third DUT 363 is also concentric with the upper edge ring 342 .

In some embodiments, the calculation unit can also adjust the distance between the upper cover plate 341 and the first piece to be tested 361 based on the first measurement data measured after the first piece to be tested 361 is parallel to the upper cover plate 341; or, based on the third measurement data measured after the third piece to be tested 363 is concentric with the upper cover plate 341, adjust the distance between the third piece to be tested 363 and the upper cover plate 341, so that the distance between the wafer to be processed W subsequently transferred into the reaction chamber and the upper electrode assembly meets the requirements. In this embodiment, the first piece to be tested 361 is the wafer to be processed W, and the third piece to be tested 363 is a calibration wafer; or the first piece to be tested 361 and the third piece to be tested 363 are two different calibration wafers.

Embodiment 4

In this embodiment, as shown in FIG9 , the first set of sensors 410 is still disposed in the upper cover. The first test piece 461 has a first surface 4611 and a second surface 4612 opposite to each other, and the first surface 4611 and the second surface 4612 have different structures. The first set of sensors 410 respectively measures the distance values between the first surface 4611, the second surface 4612 and each sensor to determine the parallelism and concentricity between the first test piece 461 and the upper edge ring.

As shown in FIG9 , the central area of the first surface 4611 of the first test piece 461 is a planar structure, and the central area of the second surface 4612 includes a characteristic structure, and the characteristic structure in FIG9 is a frustum-shaped blind hole 4614. When measuring the parallelism between the first test piece 461 and the upper cover plate, the first test piece 461 is transferred to the base, and the second surface 4612 of the first test piece 461 is in contact with the base. The first group of sensors measures the planar structure in the center of the first surface to obtain multiple first distance values, and the multiple first distance values are used as the first measurement data. Based on the first measurement data, it is determined whether the first test piece 461 is parallel to the upper cover plate. The upper electrode assembly is adjusted to achieve that the first test piece 461 is parallel to the upper cover plate, and the first test piece 461 is transferred out of the reaction chamber. Then the first test piece 461 is introduced into the reaction chamber again, and the first surface 4611 of the first test piece 461 is brought into contact with the base, and the first set of sensors 410 measures the distance of the inverted cone-shaped blind hole 4614 in the center of the second surface (the measurement point of each sensor falls on the inclined inner wall of the inverted cone-shaped blind hole 4614) to obtain multiple third distance values, which are used as third measurement data. The concentricity of the first test piece 461 and the upper cover plate is determined based on the third measurement data.

In some embodiments, after the first piece to be tested 461 is parallel to the upper cover plate, or after the first piece to be tested 461 is concentric with the upper cover plate, the distance between the upper cover plate and the first piece to be tested 461 may be adjusted.

In this embodiment, the first DUT 461 is a calibration wafer.

Embodiment 5

FIG10 is a wafer edge processing device 50 in this embodiment. The wafer edge processing device 50 includes two groups of sensors, a first group of sensors 510 is located in the upper edge ring 542, and a second group of sensors 512 is located in the upper cover plate 541. The first group of sensors 510 and the second group of sensors 512 each include at least three sensors that are evenly spaced along the circumference of the upper electrode assembly. Optionally, multiple sensors can also be unevenly spaced along the circumference of the upper electrode assembly. Some wafers may be deformed after processing (such as deposition process, etc.). In this embodiment, at least one of the upper cover plate 541 and the base 531 has a concave surface (Figure 10 shows a concave surface 5411 in the upper cover plate 541) to provide deformation space for the wafer W to be processed.

In this embodiment, as shown in FIG. 11 , the edge area of one surface of the first test piece 561 is a planar structure, and the central area of the same surface includes a characteristic structure 5613 (an inverted cone structure in this embodiment). The first group of sensors 510 is used to measure the first distance between each upper sensor and the planar structure of the first test piece 561 to obtain a plurality of first distance values, which are used as first measurement data. Based on the first measurement data, it is determined whether the first test piece 561 is parallel to the upper edge ring 542. The second group of sensors 512 is used to measure the fourth distance between each sensor and the characteristic structure of the first test piece 561 to obtain a plurality of fourth distance values, which are used as fourth measurement data. The calculation unit determines whether the first test piece 561 and the upper edge ring 542 are concentric based on the fourth measurement data. When they are concentric, the difference between any two fourth distance values in the fourth measurement data is less than the fourth preset threshold. In one embodiment, the fourth preset threshold is 0.5 mm; more preferably, the fourth preset threshold is 0.1 mm. The above fourth preset threshold is not a limitation of the present invention, and the technicians can set the fourth preset threshold according to actual needs.

In some embodiments, the computing unit may further adjust the distance between the upper edge ring 542 and the first device to be tested 561 based on the first measurement data obtained after the first device to be tested 561 is parallel to the upper edge ring 542; or, adjust the distance between the upper electrode assembly and the first device to be tested 561 based on the fourth measurement data obtained after the first device to be tested 561 is concentric with the upper edge ring 542.

In this embodiment, the calculation unit can also determine the warp direction of the wafer W to be processed and calculate at least one of the warp degree of the wafer W to be processed based on the distance data of the wafer to be processed measured by the first group of sensors 510 and the second group of sensors 512. When the multiple fourth distance values measured by the second group of sensors 512 are all greater than the multiple first distance values measured by the first group of sensors 510, it means that the edge of the wafer is warped upward by a large amplitude, and the wafer W is warped into a bowl shape as shown in FIG. 12. When the multiple first distance values measured by the first group of sensors 510 are all greater than the multiple fourth distance values measured by the second group of sensors 512, it means that the center of the wafer is warped upward by a large amplitude, and the wafer W is warped into a dome shape as shown in FIG. 13. When the difference between the first distance values measured by at least two sensors in the first sensor group 510 is greater than the set warp threshold, and the difference between the fourth distance values measured by at least two sensors in the second sensor group 512 is greater than the set warp threshold, it means that the wafer W is warped into a potato chip shape as shown in FIG. 14 .

In one embodiment, the average value of the first distance values measured by the first sensor group 510 is n ₁ , and the average value of the fourth distance values measured by the second sensor group 512 is n ₄ . The difference between n ₁ and n ₄ can be used to represent the curvature of the wafer W to be processed.

In another embodiment, a first distance value (denoted as ), and arbitrarily select a fourth distance value measured by a sensor in the second group of sensors 512 (denoted as ),by and The difference between the curvature of the wafer W to be processed is used to characterize the curvature of the wafer W to be processed. Preferably, the measurement and The sensors with these two distance values are the two sensors with the shortest straight line distance in the horizontal direction. More preferably, the straight line distance is known, and the angle between the wafer W to be processed and the horizontal plane is calculated based on the difference and the straight line distance combined with a trigonometric function, so as to characterize the curvature of the wafer W to be processed.

In another embodiment, taking the case where the first group of sensors 510 and the second group of sensors 512 each include three sensors, the six sensors are divided into three groups, each group including a sensor from the first group of sensors and a sensor from the second group of sensors, and the straight line distance between the two sensors is the shortest; the difference between the distance values measured by each group of sensors is calculated, or the angle between the wafer W to be processed and the horizontal plane is calculated based on the distance values measured by each group of sensors, so as to characterize the curvature of the wafer W to be processed. Based on the judgment result of the warp direction and the calculated warp, a reasonable distance can be set between the upper electrode assembly and the wafer W before the edge etching process begins, which can not only effectively prevent the wafer W from hitting the upper electrode assembly during the process, but also avoid etching the central area of the wafer as much as possible.

The device to be tested in this embodiment is a calibration wafer. In this embodiment, the first set of sensors 510 and the second set of sensors 512 are reused as sensors for measuring the curvature of the wafer. By reusing the sensors, the number of sensors used is reduced, the production cost is reduced, and the complexity of installing the sensors is also reduced. Moreover, only one calibration wafer is needed to achieve that the wafer to be processed W that is subsequently transferred into the reaction chamber is parallel and concentric with the upper electrode assembly, further saving production costs.

Embodiment 6

The wafer edge processing device in this embodiment includes two groups of sensors, a first group of sensors 610 is located in the upper cover plate 641, and a second group of sensors 612 is located in the upper edge ring 642. The first group of sensors 610 and the second group of sensors 612 each include at least three sensors that are evenly spaced along the circumference of the upper electrode assembly. Alternatively, multiple sensors can also be unevenly spaced along the circumference of the upper electrode assembly.

In this embodiment, as shown in FIG. 16 , the edge area of the first test piece 661 includes a characteristic structure (such as a chamfered structure), and the central area of the same surface is a planar structure. The first group of sensors 610 is used to measure the first distance between each sensor and the planar structure of the first test piece 661, and the measured multiple first distance values are used as the first measurement data. Based on the measured first measurement data, it is determined whether the first test piece 661 is parallel to the upper cover plate 641. The second group of sensors 612 is used to measure the fourth distance between each sensor and the characteristic structure of the first test piece 661, and the measured multiple fourth distance values are used as the fourth measurement data. The calculation unit determines whether the first test piece 661 and the upper cover plate 641 are concentric based on the fourth measurement data. When they are concentric, the difference between any two fourth distance values in the fourth measurement data is less than the fourth preset threshold. In one embodiment, the fourth preset threshold is 0.5 mm; more preferably, the fourth preset threshold is 0.1 mm. The above fourth preset threshold is not a limitation of the present invention, and a technician can set the preset threshold according to actual needs.

In some embodiments, the computing unit may further adjust the distance between the upper cover plate 641 and the first piece to be tested 661 based on the first measurement data obtained after the first piece to be tested 661 is parallel to the upper cover plate 641; or, adjust the distance between the upper cover plate 641 and the first piece to be tested 661 based on the fourth measurement data obtained after the first piece to be tested 661 is concentric with the upper cover plate 641.

Similarly, the calculation unit can also determine at least one of the warp direction of the wafer to be processed and calculate the warp degree of the wafer to be processed based on the distance data of the wafer to be processed measured by the first sensor group 610 and the second sensor group 612. This will not be elaborated here.

The present invention also provides an operating method of the wafer edge processing device as described in the present invention, the operating method comprising: Step S1, the calculation unit determines whether the test piece is parallel to the upper edge ring based on the first measurement data, and adjusts at least one of the upper electrode assembly and the lower electrode assembly according to the determination result until the two are parallel. The specific determination method is not described in detail here.

The operation method further includes, after step S1: Step S2, the computing unit determines whether the test piece is concentric with the upper edge ring based on the second measurement data, the third measurement data or the fourth measurement data, and adjusts at least one of the upper electrode assembly and the lower electrode assembly according to the determination result until the two are concentric. The specific determination method is not described in detail here.

Wherein, the second measurement data is composed of a plurality of second distance values, the second distance value is the second distance between the characteristic structure between the first group of sensors and the second test piece measured by the first group of sensors when the first group of sensors is located in the upper edge ring, and the second test piece is parallel to the upper edge ring; The third measurement data is composed of a plurality of third distance values, the third distance value is the third distance between the characteristic structure between the first group of sensors and the third test piece measured by the first group of sensors when the first group of sensors is located in the upper cover plate, and the third test piece is parallel to the upper edge ring; The fourth measurement data is composed of a plurality of fourth distance values, the fourth distance value being the fourth distance between the second set of sensors in the upper electrode assembly and the characteristic structure of the first test piece, the first test piece being parallel to the upper edge ring; The characteristic structure is a local structure including a surface inclined relative to the upper edge ring.

The operation method further includes, after step S1: Step S3, the calculation unit adjusts the distance between the upper electrode assembly and the object to be tested based on the first measurement data;

Or after step S2, it also includes: Step S4, the calculation unit adjusts the distance between the upper electrode assembly and the device to be tested based on at least one of the first measurement data, the second measurement data, the third measurement data and the fourth measurement data.

It should be understood that the order of the sequence numbers of the steps in the above embodiment does not imply the order of execution. The execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

The above is only a specific implementation of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or substitutions within the technical scope disclosed by the present invention, and these modifications or substitutions should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the patent application.

10: Wafer edge processing device 100: Reaction chamber 110: First set of sensors 120: Wafer transfer port 131: Base 132: Lower edge ring 1321: Second annular flange 141: Upper cover plate 142: Upper edge ring 143: Upper facility plate 1421: First annular flange 161: First piece to be tested 1611: First surface 1612: Second surface 162: Second piece to be tested 1621: First surface 1622: Second surface 210: First set of sensors 261: First piece to be tested 2611: First surface 2612: Second surface 270: V-groove 30: Wafer edge processing device 310: First set of sensors 341: Upper cover 342: Upper edge ring 361: First DUT 363: Third DUT 3633: Through hole 410: First set of sensors 461: First DUT 4611: First surface 4612: Second surface 4614: Blind hole 50: Wafer edge processing device 510: First set of sensors 512: Second set of sensors 531: Base 541: Upper cover 5411: Concave surface 542: Upper edge ring 561: First DUT 5613: Feature structure 610: First set of sensors 612: Second set of sensors 641: Upper cover 642: Upper edge ring 661: First DUT S1, S2, S3, S4: Steps W: Wafer

In order to more clearly explain the technical solution of the present invention, the following will briefly introduce the figures required for the description. Obviously, the figures described below are an embodiment of the present invention. For ordinary technical personnel in this field, other figures can be obtained based on these figures without making any progressive work: Figure 1 is a schematic diagram of the wafer edge processing device in the first embodiment of the present invention; Figure 2 is a schematic diagram of the plane structure distance measurement of the first group of sensors for the first piece to be tested in the first embodiment of the present invention; Figure 3 is a schematic diagram of the chamfered structure distance measurement of the first group of sensors for the second piece to be tested in the first embodiment of the present invention; Figure 4 is a schematic diagram of the chamfered structure distance measurement of the first group of sensors for the first piece to be tested in the second embodiment of the present invention; Figure 5 is a schematic diagram of the first group of sensors measuring the distance of the V-groove of the first test piece in another embodiment of the present invention; Figure 6 is a schematic diagram of the wafer edge processing device in the third embodiment of the present invention; Figure 7 is a schematic diagram of the first group of sensors measuring the distance of the planar structure of the first test piece in the third embodiment of the present invention; Figure 8 is a schematic diagram of the first group of sensors measuring the distance of the chamfered cone-shaped through hole of the third test piece in the third embodiment of the present invention; Figure 9 is a schematic diagram of the first group of sensors measuring the distance of the chamfered cone-shaped blind hole of the first test piece in the fourth embodiment of the present invention; Figure 10 is a schematic diagram of the wafer edge processing device in the fifth embodiment of the present invention; Figure 11 is a schematic diagram of the first and second groups of sensors simultaneously measuring the distance of the planar structure and characteristic structure of the first test piece in the fifth embodiment of the present invention; Figure 12 is a schematic diagram of the fifth embodiment of the present invention, in which the wafer warps into a bowl shape; Figure 13 is a schematic diagram of the fifth embodiment of the present invention, in which the wafer warps into a dome shape; Figure 14 is a schematic diagram of the fifth embodiment of the present invention, in which the wafer warps into a potato chip shape; Figure 15 is a schematic diagram of the wafer edge processing device in the sixth embodiment of the present invention; Figure 16 is a schematic diagram of the first and second groups of sensors simultaneously measuring the distance of the plane structure and characteristic structure of the first test piece in the sixth embodiment of the present invention.

10: Wafer edge processing device

100: reaction chamber

110: The first set of sensors

120: Wafer transmission port

131: Base

132: Lower edge ring

1321: Second annular flange

141: Upper cover plate

142: Upper edge ring

143: Upper facility board

1421: First annular flange

W: Wafer

Claims (23)

A wafer edge processing device, comprising a reaction chamber, wherein a lower electrode assembly and an upper electrode assembly are arranged in the reaction chamber; the lower electrode assembly is used to carry a piece to be tested, the lower electrode assembly comprises a lower edge ring and a base, and the upper electrode assembly comprises an upper edge ring and an upper cover plate arranged opposite to the base; the piece to be tested is a calibration wafer or a wafer to be processed, the piece to be tested comprises a first piece to be tested, and the edge area of the piece to be tested is located between the upper edge ring and the lower edge ring; The wafer edge processing device also comprises: A first group of sensors is arranged in the upper electrode assembly, the first group of sensors includes at least three sensors arranged at intervals along the circumference of the upper electrode assembly, and is used to measure the first distance between the first group of sensors and the first test piece, and the measured multiple first distance values are used as the first measurement data; A calculation unit determines whether the first test piece and the upper edge ring are parallel based on the first measurement data, and when they are parallel, the difference between the multiple first distance values is less than the first preset threshold. A wafer edge processing device as described in claim 1, wherein the first set of sensors is located in the upper edge ring. The wafer edge processing device as described in claim 2, wherein the edge area of at least one surface of the first test piece is a planar structure. A wafer edge processing device as described in claim 2, wherein the DUT further includes a second DUT, the second DUT is parallel to the upper edge ring, the first group of sensors is further used to measure a second distance between the first group of sensors and a characteristic structure of the second DUT, and the measured multiple second distance values are used as second measurement data, wherein the first DUT and the second DUT are the same DUT or different DUTs, and the characteristic structure is a local structure including a surface inclined relative to the upper edge ring; the calculation unit determines whether the upper edge ring and the second DUT are concentric based on the second measurement data, and when they are concentric, the pairwise differences of the multiple second distance values are all less than a second preset threshold. The wafer edge processing apparatus as described in claim 4, wherein an edge region of at least one surface of the second test piece includes the feature structure. The wafer edge processing device as described in claim 5, wherein the first device to be tested and the second device to be tested are both first calibration wafers, the edge area of one surface of the first calibration wafer is a planar structure, and the edge area of the other surface includes the characteristic structure. A wafer edge processing device as described in claim 4, wherein the characteristic structure is a chamfer structure or a V-groove structure. A wafer edge processing device as described in claim 1, wherein the first set of sensors is located in the upper cover plate. The wafer edge processing apparatus as described in claim 8, wherein a central area of at least one surface of the first test piece is a planar structure. A wafer edge processing device as described in claim 8, wherein the DUT further includes a third DUT, the third DUT is parallel to the upper edge ring, the first group of sensors is further used to measure a third distance between the first group of sensors and a characteristic structure of the third DUT, and the measured multiple third distance values are used as third measurement data, wherein the first DUT and the third DUT are the same DUT or different DUTs, and the characteristic structure is a local structure including a surface inclined relative to the upper edge ring; the calculation unit determines whether the upper edge ring and the third DUT are concentric based on the third measurement data, and when they are concentric, the pairwise differences of the multiple third distance values are all less than a third preset threshold. A wafer edge processing apparatus as described in claim 10, wherein a central area of at least one surface of the third test piece includes the feature structure. The wafer edge processing device as described in claim 11, wherein the first DUT and the third DUT are both second calibration wafers, the central area of one surface of the second calibration wafer is a planar structure, and the central area of the other surface includes the characteristic structure. A wafer edge processing device as described in claim 12, wherein the characteristic structure is a frustum-shaped through hole, a frustum-shaped blind hole, or an annular groove with a V-shaped cross-section. The wafer edge processing device as described in claim 1, wherein the first test piece is parallel to the upper edge ring, the first test piece includes a characteristic structure, and the characteristic structure is a local structure including a surface inclined relative to the upper edge ring, and the wafer edge processing device further includes: A second group of sensors arranged in the upper electrode assembly, the second group of sensors includes at least three sensors arranged at intervals along the circumference of the upper electrode assembly, and is used to measure the fourth distance between the second group of sensors and the characteristic structure of the first test piece, and the measured multiple fourth distance values are used as fourth measurement data; The calculation unit determines whether the first test piece and the upper edge ring are concentric based on the fourth measurement data. If they are concentric, the difference between the multiple fourth distance values is less than the fourth preset threshold. A wafer edge processing device as described in claim 14, wherein the first group of sensors is located in the upper edge ring and the second group of sensors is located in the upper cover plate; or, the first group of sensors is located in the upper cover plate and the second group of sensors is located in the upper edge ring. The wafer edge processing device as described in claim 15, wherein the edge area of the first DUT is a planar structure, and the central area of the same surface includes the characteristic structure; or, the edge area of the first DUT includes the characteristic structure, and the central area of the same surface is a planar structure. A wafer edge processing device as described in claim 15, wherein the computing unit determines at least one of the warp direction of the wafer to be processed and calculates the warp degree of the wafer to be processed based on the distance data from the wafer to be processed measured by the first group of sensors and the second group of sensors. A wafer edge processing device as described in any one of claims 1 to 17, wherein the wafer edge processing device is an edge etching device or an edge deposition device. A wafer edge processing apparatus as described in any one of claims 1 to 17, wherein at least one of the upper cover plate and the base has a concave surface. An operating method of a wafer edge processing device as described in any one of claims 1 to 19, the operating method comprising: Step S1, the computing unit determines whether the DUT is parallel to the upper edge ring based on the first measurement data, and adjusts at least one of the upper electrode assembly and the lower electrode assembly according to the determination result until the two are parallel. An operating method as described in claim 20, the operating method further comprises after step S1: Step S2, the computing unit determines whether the DUT is concentric with the upper edge ring based on the second measurement data, the third measurement data or the fourth measurement data, and adjusts at least one of the upper electrode assembly and the lower electrode assembly according to the determination result until the two are concentric; Wherein, the second measurement data is composed of a plurality of second distance values, the second distance value is the second distance between the characteristic structures between the first group of sensors and the second DUT measured by the first group of sensors when the first group of sensors is located in the upper edge ring, and the second DUT is parallel to the upper edge ring; The third measurement data is composed of a plurality of third distance values, and the third distance value is the third distance between the first group of sensors and the characteristic structure of the third device to be tested measured by the first group of sensors when the first group of sensors is located in the upper cover plate, and the third device to be tested is parallel to the upper edge ring; The fourth measurement data is composed of a plurality of fourth distance values, and the fourth distance value is the fourth distance between the second group of sensors and the characteristic structure of the first device to be tested measured by the second group of sensors in the upper electrode assembly, and the first device to be tested is parallel to the upper edge ring; The characteristic structure is a local structure including a surface inclined relative to the upper edge ring. An operating method as described in claim 20, the operating method further comprises after step S1: Step S3, the calculation unit adjusts the distance between the upper electrode assembly and the DUT based on the first measurement data measured after parallelization. An operating method as described in claim 21, the operating method further comprises after step S2: Step S4, the calculation unit adjusts the distance between the upper electrode assembly and the DUT based on at least one of the first measurement data, the second measurement data, the third measurement data and the fourth measurement data.

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