TW202418977A - Method for manufacturing micro fluid pump - Google Patents
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- 239000012530 fluid Substances 0.000 title claims abstract description 98
- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 305
- 238000005530 etching Methods 0.000 claims abstract description 50
- 238000000151 deposition Methods 0.000 claims abstract description 28
- 230000002093 peripheral effect Effects 0.000 claims description 37
- 238000000059 patterning Methods 0.000 claims description 35
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 238000005240 physical vapour deposition Methods 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 21
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 238000003486 chemical etching Methods 0.000 description 6
- 238000009413 insulation Methods 0.000 description 6
- 238000013016 damping Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000002131 composite material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
- B81C1/00119—Arrangement of basic structures like cavities or channels, e.g. suitable for microfluidic systems
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
- B81C1/00047—Cavities
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00349—Creating layers of material on a substrate
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00523—Etching material
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C3/00—Assembling of devices or systems from individually processed components
- B81C3/001—Bonding of two components
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
- F04B—POSITIVE-DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS
- F04B17/00—Pumps characterised by combination with, or adaptation to, specific driving engines or motors
- F04B17/03—Pumps characterised by combination with, or adaptation to, specific driving engines or motors driven by electric motors
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
- F04B—POSITIVE-DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS
- F04B19/00—Machines or pumps having pertinent characteristics not provided for in, or of interest apart from, groups F04B1/00 - F04B17/00
- F04B19/006—Micropumps
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- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Mechanical Engineering (AREA)
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- Analytical Chemistry (AREA)
- Dispersion Chemistry (AREA)
- Reciprocating Pumps (AREA)
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Abstract
Description
本案係關於一種微型流體泵浦的製造方法,尤指一種透過半導體製程來製作微型流體泵浦的製造方法。This case is about a method for manufacturing a microfluid pump, and in particular, a method for manufacturing a microfluid pump by a semiconductor process.
隨著科技的日新月異,流體輸送裝置的應用上亦愈來愈多元化,舉凡工業應用、生醫應用、醫療保健、電子散熱等等,甚至近來熱門的穿戴式裝置皆可見它的踨影,可見傳統的泵浦已漸漸有朝向裝置微小化、流量極大化的趨勢,而微機電泵浦能夠將流體輸送裝置的尺寸大幅度地縮小,故微機電泵浦明顯為當下微型化之流體輸送裝置的主要發展方向。With the rapid development of technology, the application of fluid transport devices is becoming more and more diversified, including industrial applications, biomedical applications, healthcare, electronic heat dissipation, etc., and even the popular wearable devices recently can be seen. It can be seen that traditional pumps have gradually tended towards miniaturization of devices and maximization of flow rates, and MEMS pumps can greatly reduce the size of fluid transport devices. Therefore, MEMS pumps are obviously the main development direction of miniaturized fluid transport devices.
請參考第5圖所示,第5圖為先前技術微型流體泵浦90,包含第一基板901、第一接著層902、第二基板903及壓電組件904。第一基板901係為矽基材,具有複數個第一流體通道9011,該些第一流體通道9011呈錐形;第一接著層902係為氧化矽,定義出第二流體通道9021,並疊設於第一基板901上;第二基板903疊設第一接著層902上,包含由下而上依序堆疊之矽結構層9031、第二接著層9035、矽薄化層9037;矽結構層9031具有一個穿孔9032、振動部9033及固定部9034;第二接著層9035係為氧化矽,具有共振腔室9036;矽薄化層9037具有一個致動部9038、外周部9039、連接部903A以及第三流體通道903B,其中致動部9038的外環之外周部9039與連接部903A連接,並具有第三流體通道903B;壓電組件904疊設於矽薄化層9037的致動部9038上,壓電組件904包含依序堆疊於致動部9038上方之下電極層9041、壓電層9042、絕緣層9043及上電極層9044。Please refer to FIG. 5 , which shows a prior art microfluidic pump 90 , including a first substrate 901 , a first bonding layer 902 , a second substrate 903 and a piezoelectric component 904 . The first substrate 901 is a silicon substrate having a plurality of first fluid channels 9011, which are conical in shape. The first connecting layer 902 is a silicon oxide layer, which defines a second fluid channel 9021 and is stacked on the first substrate 901. The second substrate 903 is stacked on the first connecting layer 902, and includes a silicon structure layer 9031, a second connecting layer 9035, and a silicon thinning layer 9037 stacked in order from bottom to top. The silicon structure layer 9031 has a through hole 9032, a vibration portion 9033, and a fixing portion 9034. The second connecting layer 9035 is a silicon oxide layer. Silicon, having a resonance chamber 9036; a silicon thin layer 9037 having an actuating portion 9038, a peripheral portion 9039, a connecting portion 903A and a third fluid channel 903B, wherein the peripheral portion 9039 of the outer ring of the actuating portion 9038 is connected to the connecting portion 903A and has a third fluid channel 903B; a piezoelectric component 904 is stacked on the actuating portion 9038 of the silicon thin layer 9037, and the piezoelectric component 904 includes a lower electrode layer 9041, a piezoelectric layer 9042, an insulating layer 9043 and an upper electrode layer 9044 stacked in sequence above the actuating portion 9038.
先前技術在第一流體通道9011製程上,由於晶圓的晶向造成錐狀的濕蝕刻角度太大,且改用乾蝕刻也有深寬比太高的問題,其製程難度高,且流阻又大;再者,第一接著層902所定義出的第二流體通道9021要夠厚,然而要生成較厚的氧化矽並不容易,且會有明顯的應力問題,造成與第二基板903接合時較易發生剝離(peeling)。In the prior art process of the first fluid channel 9011, the angle of the tapered wet etching is too large due to the crystal orientation of the wafer, and the aspect ratio is too high when dry etching is used instead. The process is difficult and the flow resistance is large. Furthermore, the second fluid channel 9021 defined by the first connection layer 902 must be thick enough, but it is not easy to generate thicker silicon oxide, and there will be obvious stress problems, resulting in easier peeling when bonding with the second substrate 903.
本案之主要目的在於提供一種微機電泵浦的製造方法,以半導體製程用於製造的微米等級的微機電泵浦,俾改善其結構在製程上的良率及流體輸送效率。The main purpose of this case is to provide a method for manufacturing a micro-electromechanical pump, using a semiconductor process to manufacture a micron-scale micro-electromechanical pump, so as to improve the process yield and fluid transport efficiency of its structure.
為達上述目的,本案之較廣義實施態樣為提供一種微型流體泵浦的製造方法,包含:步驟1.準備一第一基板;步驟2.蝕刻該第一基板的一上表面,形成至少一第一凹槽;步驟3.蝕刻該第一基板的該上表面,形成一第二凹槽,其中該至少一第一凹槽位於該第二凹槽的底部;步驟4.沉積一第一接著層於該第一基板之該至少一第一凹槽及該第二凹槽的表面上;步驟5.準備一第三基板;步驟6.沉積一第二接著層於該第三基板的表面上;步驟7.圖案化蝕刻該第二接著層;步驟8.準備一第二基板,將該第二基板與該第三基板之圖案化蝕刻的該第二接著層相互結合;步驟9.移除部分的該第二基板;步驟10.圖案化蝕刻該第二基板;步驟11.將該第一基板具有該至少一第一凹槽及該第二凹槽的表面與該第二基板相互結合;步驟12.移除部分的該第三基板;步驟13.依序沉積一下電極層及一壓電層於該第三基板上;步驟14.圖案化蝕刻該下電極層及該壓電層;步驟15.沉積一絕緣層,並圖案化蝕刻該絕緣層;步驟16.沉積一上電極層,並圖案化蝕刻該上電極層;步驟17.圖案化蝕刻該絕緣層及該第三基板;步驟18.圖案化蝕刻該第一基板的一下表面;步驟19.蝕刻該第一接著層。To achieve the above-mentioned purpose, the more general implementation of the present case is to provide a method for manufacturing a microfluidic pump, comprising: step 1. preparing a first substrate; step 2. etching an upper surface of the first substrate to form at least one first groove; step 3. etching the upper surface of the first substrate to form a second groove, wherein the at least one first groove is located at the bottom of the second groove; step 4. depositing a first bonding layer on the surface of the at least one first groove and the second groove of the first substrate; step 5. preparing a third substrate; step 6. depositing a second bonding layer on the surface of the third substrate; step 7. pattern etching the second bonding layer; step 8. preparing a second substrate, connecting the second substrate and the patterned second bonding layer of the third substrate; Step 9. removing part of the second substrate; Step 10. patterning and etching the second substrate; Step 11. bonding the surface of the first substrate having the at least one first groove and the second groove to the second substrate; Step 12. removing part of the third substrate; Step 13. sequentially depositing a lower electrode layer and a piezoelectric layer on the third substrate; Step Step 14. Pattern-etching the lower electrode layer and the piezoelectric layer; Step 15. Depositing an insulating layer and pattern-etching the insulating layer; Step 16. Depositing an upper electrode layer and pattern-etching the upper electrode layer; Step 17. Pattern-etching the insulating layer and the third substrate; Step 18. Pattern-etching a lower surface of the first substrate; Step 19. Etching the first connecting layer.
體現本案特徵與優點的實施例將在後段的說明中詳細敘述。應理解的是本案能夠在不同的態樣上具有各種的變化,其皆不脫離本案的範圍,且其中的說明及圖示在本質上當作說明之用,而非用以限制本案。The embodiments that embody the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various variations in different aspects without departing from the scope of the present invention, and the descriptions and illustrations therein are essentially for illustrative purposes rather than for limiting the present invention.
請參閱第2S圖,係為本案之微型流體泵浦之第一實施例,微型流體泵浦10包含第一基板101、第一接著層102、第二基板103、第二接著層105、第三基板106及壓電組件107。第一基板101設有流體通槽1011以及至少一第一流體通道1012,其中流體通槽1011為深槽狀;第一基板101、第一接著層102、第二基板103依序由下而上疊設,並定義出第二流體通道104,第二流體通道104頂端設有穿孔1031,穿孔1031係位於第二基板103的中心,穿孔1031的外圍由振動部1032環繞,振動部1032由固定部1033環繞;第二基板103、第二接著層105、第三基板106依序由下而上疊設,並定義出共振腔室1061;第三基板106更包含至少一第三流體通道1062、致動部1063、連接部1064與外周部1065,其中外周部1065環設於致動部1063的外圍,外周部1065並透過連接部1064耦接致動部1063,第三流體通道1062則貫通第三基板106,使第三流體通道1062、共振腔室1061得透過穿孔1031依序連通第二流體通道104、第一流體通道1012、流體通槽1011;壓電組件107疊設於致動部1063之上,包含下電極層1071、壓電層1072、絕緣層1073及上電極層1074。Please refer to FIG. 2S , which is a first embodiment of the microfluid pump of the present invention. The microfluid pump 10 includes a
請參閱第1A圖至第1C圖及第2A圖至第2S圖,如第2A圖所示,步驟1.準備一第一基板101。值得注意的是,第一基板101係為矽基材(Si),厚度為270~430
μm,但不以此為限。
Please refer to FIG. 1A to FIG. 1C and FIG. 2A to FIG. 2S. As shown in FIG. 2A, step 1. prepare a
如第2B圖所示,步驟2.蝕刻第一基板101的一上表面,形成至少一第一凹槽101A。值得注意的是,此蝕刻方式係可以物理或化學方式蝕刻。As shown in FIG. 2B , step 2. etching an upper surface of the
如第2C圖所示,步驟3.蝕刻第一基板101的上表面,形成第二凹槽101B,其中第一凹槽101A位於第二凹槽101B的底部。值得注意的是,此蝕刻方式係可以物理或化學方式蝕刻。As shown in FIG. 2C , step 3. etching the upper surface of the
如第2D圖所示,步驟4.沉積第一接著層102於第一基板101之至少一第一凹槽101A及第二凹槽101B的表面上。值得注意的是,第一接著層102係藉由物理氣相沉積或化學氣相沉積或熱氧化形成於第一基板101的表面,第一接著層102係為氧化矽,厚度範圍為1~5
μm。
As shown in FIG. 2D, step 4. depositing a
如第2E圖所示,步驟5.準備第三基板106。值得注意的是,第三基板106可以是一絕緣層上覆矽(Silicon On Insulator,SOI)晶圓,但不以此為限。As shown in FIG. 2E , step 5. prepare the third substrate 106. It should be noted that the third substrate 106 can be a silicon on insulator (SOI) wafer, but is not limited thereto.
如第2F圖所示,步驟6.沉積第二接著層105於第三基板106的表面上。值得注意的是,第二接著層105係藉由物理氣相沉積或化學氣相沉積或熱氧化形成於第三基板106的表面,第二接著層105的厚度範圍為1-5 μm。 As shown in FIG. 2F, step 6. depositing a second bonding layer 105 on the surface of the third substrate 106. It is worth noting that the second bonding layer 105 is formed on the surface of the third substrate 106 by physical vapor deposition or chemical vapor deposition or thermal oxidation, and the thickness of the second bonding layer 105 ranges from 1 to 5 μm .
如第2G圖所示,步驟7.圖案化蝕刻第二接著層105。值得注意的是,經步驟7.圖案化蝕刻第二接著層105後,產生一共振腔室1061。As shown in FIG. 2G , step 7. patterning the second subsequent layer 105. It is worth noting that after step 7. patterning the second subsequent layer 105, a resonant chamber 1061 is generated.
如第2H圖所示,步驟8.準備第二基板103,將第二基板103與第三基板106之圖案化蝕刻的第二接著層105相互結合。值得注意的是,第二基板103可以是一絕緣層上覆矽(SOI)晶圓,但不以此為限。As shown in FIG. 2H, step 8. prepare the second substrate 103, and bond the second substrate 103 to the patterned second bonding layer 105 of the third substrate 106. It is worth noting that the second substrate 103 can be a silicon-on-insulation (SOI) wafer, but is not limited thereto.
如第2I圖所示,步驟9.移除部分的第二基板103。值得注意的是,經步驟9.移除部分的第二基板103剩餘的厚度範圍為1-5 μm。 As shown in FIG. 2I , step 9. removes part of the second substrate 103. It is worth noting that the remaining thickness of the second substrate 103 after the part of the second substrate 103 is removed in step 9. is in the range of 1-5 μm .
如第2J圖所示,步驟10.圖案化蝕刻第二基板103。值得注意的是,經步驟10.圖案化蝕刻第二基板103後,第二基板103區分為一穿孔1031、一振動部1032及一固定部1033。As shown in FIG. 2J , step 10. patterning the second substrate 103. It is worth noting that after step 10. patterning the second substrate 103, the second substrate 103 is divided into a through hole 1031, a vibration portion 1032 and a fixed portion 1033.
如第2K圖所示,步驟11.將第一基板101具有至少一第一凹槽101A及第二凹槽101B的表面與第二基板103相互結合。值得注意的是,將第二基板103接合第三基板106的順序優先於將第二基板103接合第一基板101。其中,基板接合的順序係考量避免在接合時產生接合不良(Poor Bonding)所造成微型流體泵浦10的良率問題,因此先將第二基板103與第三基板106接合後再與第一基板101接合可以提升接合良率。As shown in FIG. 2K, step 11. The surface of the
如第2L圖所示,步驟12.移除部分的第三基板106。值得注意的是,經步驟12.移除部分的第三基板106剩餘的厚度範圍為5-20 μm。 As shown in FIG. 2L , step 12. removes a portion of the third substrate 106. It is worth noting that the thickness of the remaining portion of the third substrate 106 after the portion is removed in step 12. ranges from 5 to 20 μm .
如第2M圖所示,步驟13.依序沉積下電極層1071及壓電層1072於第三基板106上。As shown in FIG. 2M , step 13. depositing the lower electrode layer 1071 and the piezoelectric layer 1072 on the third substrate 106 in sequence.
如第2N圖所示,步驟14.圖案化蝕刻下電極層1071及壓電層1072。As shown in FIG. 2N , step 14: patterning and etching the lower electrode layer 1071 and the piezoelectric layer 1072.
如第2O圖所示,步驟15.沉積絕緣層1073,並圖案化蝕刻絕緣層1073。As shown in FIG. 20 , step 15 is to deposit an insulating layer 1073 and pattern-etch the insulating layer 1073 .
如第2P圖所示,步驟16.沉積上電極層1074,並圖案化蝕刻上電極層1074。As shown in FIG. 2P , step 16. depositing an upper electrode layer 1074 and pattern-etching the upper electrode layer 1074 .
如第2Q圖所示,步驟17.圖案化蝕刻絕緣層1073及第三基板106。值得注意的是,經步驟17.圖案化蝕刻絕緣層1073及第三基板106後,產生至少一第三流體通道1062,第三基板106區分為致動部1063、至少一外周部1065,其中,至少一連接部1064連接致動部1063與外周部1065,至少一第三流體通道1062亦介於致動部1063與外周部1065之間。此外,值得注意的是,位於第三基板106之致動部1063上的下電極層1071、壓電層1072、絕緣層1073及上電極層1074係為壓電組件107。另外,值得注意的是,壓電層1072為圓形設置於第三基板106之致動部1063上方,使致動部1063亦呈圓形。As shown in FIG. 2Q, step 17. patterning the insulating layer 1073 and the third substrate 106. It is worth noting that after step 17. patterning the insulating layer 1073 and the third substrate 106, at least one third fluid channel 1062 is generated, and the third substrate 106 is divided into an actuating portion 1063 and at least one peripheral portion 1065, wherein at least one connecting portion 1064 connects the actuating portion 1063 and the peripheral portion 1065, and at least one third fluid channel 1062 is also between the actuating portion 1063 and the peripheral portion 1065. In addition, it is worth noting that the lower electrode layer 1071, the piezoelectric layer 1072, the insulating layer 1073 and the upper electrode layer 1074 on the actuating portion 1063 of the third substrate 106 are the piezoelectric component 107. In addition, it is worth noting that the piezoelectric layer 1072 is circularly disposed above the actuating portion 1063 of the third substrate 106, so that the actuating portion 1063 is also circular.
如第2R圖所示,步驟18.圖案化蝕刻第一基板101的一下表面。As shown in FIG. 2R , step 18 is to pattern-etch a lower surface of the
如第2S圖所示,步驟19.蝕刻第一接著層102。即完成微型流體泵浦10的製作。As shown in FIG. 2S, step 19 is to etch the
值得注意的是,如第2S圖所示之流體通槽1011為分段蝕刻,解決了先前技術的蝕刻角度過大或高深寬比蝕刻問題,並且降低了流體流通第一流體通道1012的流阻。此外,第一接著層102係為氧化矽,但厚度調整為1~5
μm,可以避免與第二基板103接合所造成的應力剝離問題。另外,第二流體通道104則以蝕刻第一基板101來定義出。
It is worth noting that the fluid channel 1011 shown in FIG. 2S is etched in sections, which solves the problem of excessive etching angle or high aspect ratio etching in the prior art, and reduces the flow resistance of the fluid flowing through the first fluid channel 1012. In addition, the
再者,值得注意的是,如第2S圖所示之第二基板103係為矽結構層,可以由SOI晶片轉移而來,厚度為1~5 μm,但不以此為限,第二基板103的厚度可視設計需求加以調整。第二基板103區分為穿孔1031、振動部1032及固定部1033三個區域,穿孔1031位於中心位置,振動部1032位於穿孔1031的周邊區域,固定部1033位於第二基板103的周緣區域。 Furthermore, it is worth noting that the second substrate 103 shown in FIG. 2S is a silicon structure layer, which can be transferred from an SOI wafer, and has a thickness of 1 to 5 μm , but is not limited thereto. The thickness of the second substrate 103 can be adjusted according to design requirements. The second substrate 103 is divided into three regions: a through hole 1031, a vibration portion 1032, and a fixed portion 1033. The through hole 1031 is located at the center, the vibration portion 1032 is located at the peripheral region of the through hole 1031, and the fixed portion 1033 is located at the peripheral region of the second substrate 103.
另外,值得注意的是,如第2S圖所示之第二接著層105係為氧化矽,厚度為1~5
μm。第一接著層102的厚度可以等於第二接著層105的厚度,其厚度可以是1.1
μm,但不以此為限,第一接著層102的厚度與第二接著層105的厚度亦可以不相等,可視設計需求加以調整。第二接著層105堆疊於第二基板103上方。
In addition, it is worth noting that the second connecting layer 105 shown in FIG. 2S is silicon oxide with a thickness of 1-5 μm . The thickness of the first connecting
除此,值得注意的是,如第2S圖所示之第三基板106係為矽結構層,可以由SOI晶片轉移而來,厚度為10~20 μm,但不以此為限,第三基板106的厚度可視設計需求加以調整;第三基板106堆疊於第二接著層105上方,形成共振腔室1061;第三基板106具有致動部1063及外周部1065,致動部1063的外環具有第三流體通道1062及連接部1064,連接部1064係用以連接致動部1063與外周部1065。 In addition, it is worth noting that the third substrate 106 shown in FIG. 2S is a silicon structure layer, which can be transferred from an SOI chip, and has a thickness of 10 to 20 μm , but is not limited thereto. The thickness of the third substrate 106 can be adjusted according to design requirements; the third substrate 106 is stacked on top of the second bonding layer 105 to form a resonance chamber 1061; the third substrate 106 has an actuating portion 1063 and a peripheral portion 1065, and the outer ring of the actuating portion 1063 has a third fluid channel 1062 and a connecting portion 1064, and the connecting portion 1064 is used to connect the actuating portion 1063 and the peripheral portion 1065.
值得注意的是,第二基板103、第三基板106可以是單晶矽、多晶矽或非晶矽。第二基板103、第三基板106也可以使用沉積或薄化製程而來。It is worth noting that the second substrate 103 and the third substrate 106 can be single crystal silicon, polycrystalline silicon or amorphous silicon. The second substrate 103 and the third substrate 106 can also be made by deposition or thinning process.
壓電組件107更包含下電極層1071、壓電層1072、絕緣層1073及上電極層1074。壓電層1072疊設於下電極層1071上;絕緣層1073鋪設於壓電層1072之部分表面上及下電極層1071之部分表面上,其中絕緣層1073為電性絕緣;上電極層1074疊設於絕緣層1073上以及壓電層1072未設有絕緣層1073之其餘表面上。值得注意的是,壓電層1072為圓形設置於第三基板106之致動部1063上方,使致動部1063亦呈圓形。此外,值得注意的是,壓電層1072的直徑為140~500 μm,但不以此為限,壓電層1072的直徑,可視微型流體泵浦10整體大小加以調整。另外,值得注意的是,壓電層1072與致動部1063的直徑比例範圍為1:1.3~1:3.6,換言之,壓電層1072的尺寸小於致動部1063的尺寸。 The piezoelectric component 107 further includes a lower electrode layer 1071, a piezoelectric layer 1072, an insulating layer 1073, and an upper electrode layer 1074. The piezoelectric layer 1072 is stacked on the lower electrode layer 1071; the insulating layer 1073 is laid on a portion of the surface of the piezoelectric layer 1072 and a portion of the surface of the lower electrode layer 1071, wherein the insulating layer 1073 is electrically insulating; and the upper electrode layer 1074 is stacked on the insulating layer 1073 and on the remaining surface of the piezoelectric layer 1072 where the insulating layer 1073 is not provided. It is worth noting that the piezoelectric layer 1072 is circularly disposed above the actuating portion 1063 of the third substrate 106, so that the actuating portion 1063 is also circular. In addition, it is worth noting that the diameter of the piezoelectric layer 1072 is 140 to 500 μm , but is not limited thereto. The diameter of the piezoelectric layer 1072 can be adjusted according to the overall size of the microfluidic pump 10. In addition, it is worth noting that the diameter ratio of the piezoelectric layer 1072 to the actuating portion 1063 is in the range of 1:1.3 to 1:3.6. In other words, the size of the piezoelectric layer 1072 is smaller than the size of the actuating portion 1063.
透過壓電組件107的作動,致動部1063亦跟著上下振動,第二基板103的振動部1032隨之呈不同相位振動,使共振腔室1061形成負壓,流體便由流體通槽1011通過第一流體通道1012,再經過第二流體通道104,並由第二基板103的穿孔1031繼續流經共振腔室1061,最後通過第三基板106的第三流體通道1062完成流體的輸送。值得注意的是致動部1063的作動頻率為0.1~1.5MHz高頻範圍,藉此微流體可以積少成多產生更多的流量,但不以此為限,致動部1063的作動頻率可由整體微型流體泵浦10之設計加以調整。此外,值得注意的是,致動部1063呈圓形且直徑為400~550 μm,但不以此為限,致動部1063的形狀尺寸亦可由整體微型流體泵浦10之設計加以調整。 Through the actuation of the piezoelectric component 107, the actuator 1063 also vibrates up and down, and the vibrating portion 1032 of the second substrate 103 vibrates in different phases, so that the resonance chamber 1061 forms a negative pressure, and the fluid passes through the first fluid channel 1012 from the fluid groove 1011, and then passes through the second fluid channel 104, and continues to flow through the resonance chamber 1061 through the through hole 1031 of the second substrate 103, and finally passes through the third fluid channel 1062 of the third substrate 106 to complete the fluid delivery. It is worth noting that the actuation frequency of the actuator 1063 is in the high frequency range of 0.1 to 1.5 MHz, so that the microfluid can accumulate a small amount to generate more flow, but it is not limited to this. The actuation frequency of the actuator 1063 can be adjusted by the design of the overall microfluid pump 10. In addition, it is worth noting that the actuator 1063 is circular and has a diameter of 400-550 μm , but is not limited thereto. The shape and size of the actuator 1063 can also be adjusted by the design of the overall microfluidic pump 10.
微型流體泵浦10的工作電壓為2~12V,值得一提的是,微型流體泵浦10的工作電壓、第三基板106的致動部1063之作動頻率、第三基板106的厚度以及第二基板103的振動部1032之共振皆會影響流體的輸送量與效率。The working voltage of the microfluid pump 10 is 2-12V. It is worth mentioning that the working voltage of the microfluid pump 10, the operating frequency of the actuator 1063 of the third substrate 106, the thickness of the third substrate 106 and the resonance of the vibration part 1032 of the second substrate 103 will all affect the delivery amount and efficiency of the fluid.
請參閱第3T圖,係為本案之微型流體泵浦之第二實施例,與第一實施例主要的差異處在於第三基板206具有蝕刻一深度。於本實施例中,微型流體泵浦20包含第一基板201、第一接著層202、第二基板203、第二接著層205、第三基板206及壓電組件207第一基板201設有流體通槽2011以及至少一第一流體通道2012,其中流體通槽2011為深槽狀;第一基板201、第一接著層202、第二基板203依序由下而上疊設,並定義出第二流體通道204,第二流體通道204頂端設有穿孔2031,穿孔2031係位於第二基板203的中心,穿孔2031的外圍由振動部2032環繞,振動部2032由固定部2033環繞;第二基板203、第二接著層205、第三基板206依序由下而上疊設,並定義出共振腔室2061;第三基板206更包含至少一第三流體通道2062、致動部2063、連接部2064與外周部2065,其中外周部2065環設於致動部2063的外圍,外周部2065並透過連接部2064耦接致動部2063,第三流體通道2062則貫通第三基板206,使第三流體通道2062、共振腔室2061得透過穿孔2031依序連通第二流體通道204、第一流體通道2012、流體通槽2011;壓電組件207疊設於致動部2063之上,包含下電極層2071、壓電層2072、絕緣層2073及上電極層2074。Please refer to FIG. 3T, which is a second embodiment of the microfluid pump of the present invention. The main difference from the first embodiment is that the third substrate 206 is etched to a depth. In this embodiment, the microfluid pump 20 comprises a
請參閱第1A圖至第1C圖及第3A圖至第3T圖,如第3A圖所示,步驟1.準備一第一基板201。值得注意的是,第一基板201係為矽基材(Si),厚度為270~430
μm,但不以此為限。
Please refer to FIG. 1A to FIG. 1C and FIG. 3A to FIG. 3T. As shown in FIG. 3A, step 1. prepare a
如第3B圖所示,步驟2.蝕刻第一基板201的一上表面,形成至少一第一凹槽201A。值得注意的是,此蝕刻方式係可以物理或化學方式蝕刻。As shown in FIG. 3B , step 2. etching an upper surface of the
如第3C圖所示,步驟3.蝕刻第一基板201的上表面,形成第二凹槽201B,其中第一凹槽201A位於第二凹槽201B的底部。值得注意的是,此蝕刻方式係可以物理或化學方式蝕刻。As shown in FIG. 3C , step 3. etching the upper surface of the
如第3D圖所示,步驟4.沉積第一接著層202於第一基板201之至少一第一凹槽201A及第二凹槽201B的表面上。值得注意的是,第一接著層202係藉由物理氣相沉積或化學氣相沉積或熱氧化形成於第一基板201的表面,第一接著層202係為氧化矽,厚度範圍為1~5
μm。
As shown in FIG. 3D, step 4. depositing a
如第3E圖所示,步驟5.準備第三基板206。值得注意的是,第三基板206可以是一絕緣層上覆矽(SOI)晶圓,但不以此為限。As shown in FIG. 3E , step 5. prepare the third substrate 206. It should be noted that the third substrate 206 can be a silicon-on-insulation (SOI) wafer, but is not limited thereto.
如第3F圖所示,步驟6.沉積第二接著層205於第三基板206的表面上。值得注意的是,第二接著層205係藉由物理氣相沉積或化學氣相沉積或熱氧化形成於第三基板206的表面,第二接著層205的厚度範圍為1-5 μm。 As shown in FIG. 3F, step 6. depositing a second bonding layer 205 on the surface of the third substrate 206. It is worth noting that the second bonding layer 205 is formed on the surface of the third substrate 206 by physical vapor deposition or chemical vapor deposition or thermal oxidation, and the thickness of the second bonding layer 205 ranges from 1 to 5 μm .
如第3G圖所示,步驟7.圖案化蝕刻第二接著層205。值得注意的是,經步驟7.圖案化蝕刻第二接著層205後,產生一共振腔室2061。As shown in FIG. 3G , step 7. patterning the second subsequent layer 205. It is worth noting that after step 7. patterning the second subsequent layer 205, a resonant chamber 2061 is generated.
如第3H圖所示,經步驟7.圖案化蝕刻第二接著層205後,更包含蝕刻第三基板206至一深度。值得注意的是,第三基板206蝕刻至一深度,使得如第3T圖所示之共振腔室2061的空間提高了,適當降低擠壓膜阻尼(squeeze film damping),且當壓電組件207作動帶動第三基板206的致動部2063振動時,也較不易與第二基板203的振動部2032產生沾黏(stiction)效應。As shown in FIG. 3H, after the second connecting layer 205 is patterned and etched in step 7, the third substrate 206 is further etched to a depth. It is worth noting that the third substrate 206 is etched to a depth such that the space of the resonance chamber 2061 shown in FIG. 3T is increased, the squeeze film damping is appropriately reduced, and when the piezoelectric component 207 is actuated to drive the actuating portion 2063 of the third substrate 206 to vibrate, it is less likely to produce a stiction effect with the vibrating portion 2032 of the second substrate 203.
如第3I圖所示,步驟8.準備第二基板203,將第二基板203與第三基板206之圖案化蝕刻的第二接著層205相互結合。值得注意的是,第二基板203可以是一絕緣層上覆矽(SOI)晶圓,但不以此為限。As shown in FIG. 3I, step 8. prepare the second substrate 203, and bond the second substrate 203 to the patterned second bonding layer 205 of the third substrate 206. It should be noted that the second substrate 203 can be a silicon-on-insulation (SOI) wafer, but is not limited thereto.
如第3J圖所示,步驟9.移除部分的第二基板203。值得注意的是,經步驟9.移除部分的第二基板203剩餘的厚度範圍為1-5 μm。 As shown in FIG. 3J, step 9. removes part of the second substrate 203. It is worth noting that the remaining thickness of the second substrate 203 after the part of the second substrate 203 is removed in step 9. is in the range of 1-5 μm .
如第3K圖所示,步驟10.圖案化蝕刻第二基板203。值得注意的是,經步驟10.圖案化蝕刻第二基板203後,第二基板203區分為一穿孔2031、一振動部2032及一固定部2033。As shown in FIG. 3K , step 10. patterning the second substrate 203. It is worth noting that after step 10. patterning the second substrate 203, the second substrate 203 is divided into a through hole 2031, a vibration portion 2032 and a fixed portion 2033.
如第3L圖所示,步驟11.將第一基板201具有至少一第一凹槽201A及第二凹槽201B的表面與第二基板203相互結合。值得注意的是,將第二基板203接合第三基板206的順序優先於將第二基板203接合第一基板201。其中,基板接合的順序係考量避免在接合時產生接合不良(Poor Bonding)所造成微型流體泵浦20的良率問題,因此先將第二基板203與第三基板206接合後再與第一基板201接合可以提升接合良率。As shown in FIG. 3L, step 11. The surface of the
如第3M圖所示,步驟12.移除部分的第三基板206。值得注意的是,經步驟12.移除部分的第三基板206剩餘的厚度範圍為5-20 μm。 As shown in FIG. 3M , step 12. removes part of the third substrate 206. It is worth noting that the remaining thickness of the third substrate 206 after the part of the third substrate 206 is removed in step 12. ranges from 5 to 20 μm .
如第3N圖所示,步驟13.依序沉積下電極層2071及壓電層2072於第三基板206上。As shown in FIG. 3N , step 13. depositing the lower electrode layer 2071 and the piezoelectric layer 2072 on the third substrate 206 in sequence.
如第3O圖所示,步驟14.圖案化蝕刻下電極層2071及壓電層2072。As shown in FIG. 30 , step 14: patterning and etching the lower electrode layer 2071 and the piezoelectric layer 2072.
如第3P圖所示,步驟15.沉積絕緣層2073,並圖案化蝕刻絕緣層2073。As shown in FIG. 3P, step 15 is to deposit an insulating layer 2073 and pattern-etch the insulating layer 2073.
如第3Q圖所示,步驟16.沉積上電極層2074,並圖案化蝕刻上電極層2074。As shown in FIG. 3Q, step 16. depositing an upper electrode layer 2074 and patterning and etching the upper electrode layer 2074.
如第3R圖所示,步驟17.圖案化蝕刻絕緣層2073及第三基板206。值得注意的是,經步驟17.圖案化蝕刻絕緣層2073及第三基板206後,產生至少一第三流體通道2062,第三基板206區分為致動部2063、至少一外周部2065,其中,至少一連接部2064連接致動部2063與外周部2065,至少一第三流體通道2062亦介於致動部2063與外周部2065之間。此外,值得注意的是,位於第三基板206之致動部2063上的下電極層2071、壓電層2072、絕緣層2073及上電極層2074係為壓電組件207。另外,值得注意的是,壓電層2072為圓形設置於第三基板206之致動部2063上方,使致動部2063亦呈圓形。As shown in FIG. 3R, step 17. patterning the insulating layer 2073 and the third substrate 206. It is worth noting that after step 17. patterning the insulating layer 2073 and the third substrate 206, at least one third fluid channel 2062 is generated, and the third substrate 206 is divided into an actuating portion 2063 and at least one peripheral portion 2065, wherein at least one connecting portion 2064 connects the actuating portion 2063 and the peripheral portion 2065, and at least one third fluid channel 2062 is also between the actuating portion 2063 and the peripheral portion 2065. In addition, it is worth noting that the lower electrode layer 2071, the piezoelectric layer 2072, the insulating layer 2073 and the upper electrode layer 2074 on the actuating portion 2063 of the third substrate 206 are the piezoelectric component 207. In addition, it is worth noting that the piezoelectric layer 2072 is circularly disposed above the actuating portion 2063 of the third substrate 206, so that the actuating portion 2063 is also circular.
如第3S圖所示,步驟18.圖案化蝕刻第一基板201的一下表面。As shown in FIG. 3S , step 18 is to pattern-etch a lower surface of the
如第3T圖所示,步驟19.蝕刻第一接著層202。即完成微型流體泵浦20的製作。As shown in FIG. 3T, step 19 is to etch the
值得注意的是,如第3T圖所示之流體通槽2011為分段蝕刻,解決了先前技術的蝕刻角度過大或高深寬比蝕刻問題,並且降低了流體流通第一流體通道2012的流阻。此外,第一接著層202係為氧化矽,但厚度調整為1~5
μm,可以避免與第二基板203接合所造成的應力剝離問題。另外,第二流體通道204則以蝕刻第一基板201來定義出。
It is worth noting that the fluid channel 2011 shown in FIG. 3T is etched in sections, which solves the problem of excessive etching angle or high aspect ratio etching in the prior art, and reduces the flow resistance of the fluid flowing through the first fluid channel 2012. In addition, the
再者,值得注意的是,如第3T圖所示之第二基板203係為矽結構層,可以由SOI晶片轉移而來,厚度為1~5 μm,但不以此為限,第二基板203的厚度可視設計需求加以調整。第二基板203區分為穿孔2031、振動部2032及固定部2033三個區域,穿孔2031位於中心位置,振動部2032位於穿孔2031的周邊區域,固定部2033位於第二基板203的周緣區域。 Furthermore, it is worth noting that the second substrate 203 shown in FIG. 3T is a silicon structure layer, which can be transferred from an SOI wafer, and has a thickness of 1 to 5 μm , but is not limited thereto. The thickness of the second substrate 203 can be adjusted according to design requirements. The second substrate 203 is divided into three regions: a through hole 2031, a vibration portion 2032, and a fixed portion 2033. The through hole 2031 is located at the center, the vibration portion 2032 is located at the peripheral region of the through hole 2031, and the fixed portion 2033 is located at the peripheral region of the second substrate 203.
另外,值得注意的是,如第3T圖所示之第二接著層205係為氧化矽,厚度為1~5
μm。第一接著層202的厚度可以等於第二接著層205的厚度,其厚度可以是1.1
μm,但不以此為限,第一接著層202的厚度與第二接著層205的厚度亦可以不相等,可視設計需求加以調整。第二接著層205堆疊於第二基板203上方。
In addition, it is worth noting that the second connecting layer 205 shown in FIG. 3T is silicon oxide with a thickness of 1-5 μm . The thickness of the first connecting
除此,值得注意的是,如第3T圖所示之第三基板206係為矽結構層,可以由SOI晶片轉移而來,厚度為10~20 μm,但不以此為限,第三基板206的厚度可視設計需求加以調整;第三基板206堆疊於第二接著層205上方,形成共振腔室2061;第三基板206具有致動部2063及外周部2065,致動部2063的外環具有第三流體通道2062及連接部2064,連接部2064係用以連接致動部2063與外周部2065。 In addition, it is worth noting that the third substrate 206 shown in FIG. 3T is a silicon structure layer, which can be transferred from an SOI chip, and has a thickness of 10 to 20 μm , but is not limited thereto. The thickness of the third substrate 206 can be adjusted according to design requirements; the third substrate 206 is stacked on top of the second bonding layer 205 to form a resonance chamber 2061; the third substrate 206 has an actuating portion 2063 and a peripheral portion 2065, and the outer ring of the actuating portion 2063 has a third fluid channel 2062 and a connecting portion 2064, and the connecting portion 2064 is used to connect the actuating portion 2063 and the peripheral portion 2065.
值得注意的是,第二基板203、第三基板206可以是單晶矽、多晶矽或非晶矽。第二基板203、第三基板206也可以使用沉積或薄化製程而來。It is worth noting that the second substrate 203 and the third substrate 206 can be single crystal silicon, polycrystalline silicon or amorphous silicon. The second substrate 203 and the third substrate 206 can also be made by deposition or thinning process.
壓電組件207更包含下電極層2071、壓電層2072、絕緣層2073及電極層2074。壓電層2072疊設於下電極層2071上;絕緣層2073鋪設於壓電層2072之部分表面上及下電極層2071之部分表面上,其中絕緣層2073為電性絕緣;上電極層2074疊設於絕緣層2073上以及壓電層2072未設有絕緣層2073之其餘表面上。值得注意的是,壓電層2072為圓形設置於第三基板206之致動部2063上方,使致動部2063亦呈圓形。此外,值得注意的是,壓電層2072的直徑為140~500 μm,但不以此為限,壓電層2072的直徑,可視微型流體泵浦20整體大小加以調整。另外,值得注意的是,壓電層2072與致動部2063的直徑比例範圍為1:1.3~1:3.6,換言之,壓電層2072的尺寸小於致動部2063的尺寸。 The piezoelectric component 207 further includes a lower electrode layer 2071, a piezoelectric layer 2072, an insulating layer 2073 and an electrode layer 2074. The piezoelectric layer 2072 is stacked on the lower electrode layer 2071; the insulating layer 2073 is laid on a portion of the surface of the piezoelectric layer 2072 and a portion of the surface of the lower electrode layer 2071, wherein the insulating layer 2073 is electrically insulating; and the upper electrode layer 2074 is stacked on the insulating layer 2073 and on the remaining surface of the piezoelectric layer 2072 where the insulating layer 2073 is not provided. It is worth noting that the piezoelectric layer 2072 is circularly disposed above the actuating portion 2063 of the third substrate 206, so that the actuating portion 2063 is also circular. In addition, it is worth noting that the diameter of the piezoelectric layer 2072 is 140 to 500 μm , but is not limited thereto. The diameter of the piezoelectric layer 2072 can be adjusted according to the overall size of the microfluidic pump 20. In addition, it is worth noting that the diameter ratio of the piezoelectric layer 2072 to the actuating portion 2063 is in the range of 1:1.3 to 1:3.6. In other words, the size of the piezoelectric layer 2072 is smaller than the size of the actuating portion 2063.
透過壓電組件207的作動,致動部2063亦跟著上下振動,第二基板203的振動部2032隨之呈不同相位振動,使共振腔室2061形成負壓,流體便由流體通槽2011通過第一流體通道2012,再經過第二流體通道204,並由第二基板203的穿孔2031繼續流經共振腔室2061,最後通過第三基板206的第三流體通道2062完成流體的輸送。值得注意的是致動部2063的作動頻率為0.1~1.5MHz高頻範圍,藉此微流體可以積少成多產生更多的流量,但不以此為限,致動部2063的作動頻率可由整體微型流體泵浦20之設計加以調整。此外,值得注意的是,致動部2063呈圓形且直徑為400~550 μm,但不以此為限,致動部2063的形狀尺寸亦可由整體微型流體泵浦20之設計加以調整。 Through the actuation of the piezoelectric component 207, the actuator 2063 also vibrates up and down, and the vibrating part 2032 of the second substrate 203 vibrates in different phases, so that the resonance chamber 2061 forms a negative pressure, and the fluid passes through the first fluid channel 2012 from the fluid groove 2011, and then passes through the second fluid channel 204, and continues to flow through the resonance chamber 2061 through the through hole 2031 of the second substrate 203, and finally passes through the third fluid channel 2062 of the third substrate 206 to complete the fluid delivery. It is worth noting that the actuation frequency of the actuator 2063 is in the high frequency range of 0.1 to 1.5 MHz, so that the microfluid can accumulate a small amount to generate more flow, but it is not limited to this. The actuation frequency of the actuator 2063 can be adjusted by the design of the overall microfluid pump 20. In addition, it is worth noting that the actuator 2063 is circular and has a diameter of 400-550 μm , but is not limited thereto. The shape and size of the actuator 2063 can also be adjusted by the design of the overall microfluidic pump 20.
微型流體泵浦20的工作電壓為2~12V,值得一提的是,微型流體泵浦20的工作電壓、第三基板206的致動部2063之作動頻率、第三基板206的厚度以及第二基板203的振動部2032之共振皆會影響流體的輸送量與效率。The working voltage of the microfluid pump 20 is 2-12V. It is worth mentioning that the working voltage of the microfluid pump 20, the operating frequency of the actuator 2063 of the third substrate 206, the thickness of the third substrate 206 and the resonance of the vibration part 2032 of the second substrate 203 will all affect the delivery amount and efficiency of the fluid.
另外,值得注意的是,第二實施例與第一實施例最主要的差異在於第三基板206具有蝕刻一深度,其改良的特色在於,因為共振腔室2061的空間提高了,可以適當降低擠壓膜阻尼(squeeze film damping),且當壓電組件207作動帶動第三基板206的致動部2063振動時,也較不易與第二基板203的振動部2032產生沾黏(stiction)效應。In addition, it is worth noting that the main difference between the second embodiment and the first embodiment is that the third substrate 206 has an etched depth. The improved feature is that because the space of the resonance chamber 2061 is increased, the squeeze film damping can be appropriately reduced, and when the piezoelectric component 207 is actuated to drive the actuating portion 2063 of the third substrate 206 to vibrate, it is less likely to produce a stiction effect with the vibrating portion 2032 of the second substrate 203.
請參閱第4S圖,係為本案之微型流體泵浦之第三實施例,與第一實施例主要的差異處在於第二接著層305係為氧化矽-多晶矽-氧化矽的複合結構。於本實施例中,微型流體泵浦30包含第一基板301、第一接著層302、第二基板303、第二接著層305、第三基板306及壓電組件307第一基板301設有流體通槽3011以及至少一第一流體通道3012,其中流體通槽3011為深槽狀;第一基板301、第一接著層302、第二基板303依序由下而上疊設,並定義出第二流體通道304,第二流體通道304頂端設有穿孔3031,穿孔3031係位於第二基板303的中心,穿孔3031的外圍由振動部3032環繞,振動部3032由固定部3033環繞;第二基板303、第二接著層305、第三基板306依序由下而上疊設,並定義出共振腔室3061;第三基板306更包含至少一第三流體通道3062、致動部3063、連接部3064與外周部3065,其中外周部3065環設於致動部3063的外圍,外周部3065並透過連接部3064耦接致動部3063,第三流體通道3062則貫通第三基板306,使第三流體通道3062、共振腔室3061得透過穿孔3031依序連通第二流體通道304、第一流體通道3012、流體通槽3011;壓電組件307疊設於致動部3063之上,包含下電極層3071、壓電層3072、絕緣層3073及上電極層3074。Please refer to FIG. 4S, which is a third embodiment of the microfluid pump of the present invention. The main difference from the first embodiment is that the second bonding layer 305 is a composite structure of silicon oxide-polysilicon-silicon oxide. In this embodiment, the microfluid pump 30 comprises a
請參閱第1A圖至第1C圖及第4A圖至第4S圖,如第4A圖所示,步驟1.準備一第一基板301。值得注意的是,第一基板301係為矽基材(Si),厚度為270~430
μm,但不以此為限。
Please refer to FIG. 1A to FIG. 1C and FIG. 4A to FIG. 4S. As shown in FIG. 4A, step 1. prepare a
如第4B圖所示,步驟2.蝕刻第一基板301的一上表面,形成至少一第一凹槽301A。值得注意的是,此蝕刻方式係可以物理或化學方式蝕刻。As shown in FIG. 4B , step 2. etching an upper surface of the
如第4C圖所示,步驟3.蝕刻第一基板301的上表面,形成第二凹槽301B,其中第一凹槽301A位於第二凹槽301B的底部。值得注意的是,此蝕刻方式係可以物理或化學方式蝕刻。As shown in FIG. 4C , step 3. etching the upper surface of the
如第4D圖所示,步驟4.沉積第一接著層302於第一基板301之至少一第一凹槽301A及第二凹槽301B的表面上。值得注意的是,第一接著層302係藉由物理氣相沉積或化學氣相沉積或熱氧化形成於第一基板301的表面,第一接著層302係為氧化矽,厚度範圍為1~5
μm。
As shown in FIG. 4D, step 4. depositing a
如第4E圖所示,步驟5.準備第三基板30。值得注意的是,第三基板306可以是一絕緣層上覆矽(SOI)晶圓,但不以此為限。As shown in FIG. 4E , step 5. prepare the third substrate 306. It should be noted that the third substrate 306 can be a silicon-on-insulation (SOI) wafer, but is not limited thereto.
如第4F圖所示,步驟6.沉積第二接著層305於第三基板306的表面上。值得注意的是,第二接著層305更包含至少一多晶矽層3052,多晶矽層3052之下層3051與上層3053各為矽氧化層所包覆,但不以此為限,第二接著層305除了矽氧化層-多晶矽層-矽氧化層外,第二接著層305更可具有多個多晶矽層3052,如矽氧化層-多晶矽層-矽氧化層-多晶矽層-矽氧化層。As shown in FIG. 4F, step 6. depositing a second bonding layer 305 on the surface of the third substrate 306. It is worth noting that the second bonding layer 305 further includes at least one polysilicon layer 3052, and the lower layer 3051 and the upper layer 3053 of the polysilicon layer 3052 are each covered by a silicon oxide layer, but not limited to this. In addition to silicon oxide layer-polysilicon layer-silicon oxide layer, the second bonding layer 305 may also have multiple polysilicon layers 3052, such as silicon oxide layer-polysilicon layer-silicon oxide layer-polysilicon layer-silicon oxide layer.
如第4G圖所示,步驟7.圖案化蝕刻第二接著層305。值得注意的是,經步驟7.圖案化蝕刻第二接著層305後,產生一共振腔室3061。值得注意的是,第二接著層305具有蝕刻一深度,使得如第4S圖所示之共振腔室3061的空間提高了,適當降低擠壓膜阻尼(squeeze film damping),且當壓電組件307作動帶動第三基板306的致動部3063振動時,也較不易與第二基板303的振動部3032產生沾黏(stiction)效應。As shown in FIG. 4G, step 7. patterning the second connecting layer 305. It is worth noting that after step 7. patterning the second connecting layer 305, a resonance chamber 3061 is generated. It is worth noting that the second connecting layer 305 has a depth of etching, so that the space of the resonance chamber 3061 shown in FIG. 4S is increased, the squeeze film damping is appropriately reduced, and when the piezoelectric component 307 is actuated to drive the actuating portion 3063 of the third substrate 306 to vibrate, it is less likely to produce a stiction effect with the vibrating portion 3032 of the second substrate 303.
如第4H圖所示,步驟8.準備第二基板303,將第二基板303與第三基板306之圖案化蝕刻的第二接著層305相互結合。值得注意的是,第二基板303可以是一絕緣層上覆矽(SOI)晶圓,但不以此為限。As shown in FIG. 4H, step 8. prepare the second substrate 303, and bond the second substrate 303 to the patterned second bonding layer 305 of the third substrate 306. It is worth noting that the second substrate 303 can be a silicon-on-insulation (SOI) wafer, but is not limited thereto.
如第4I圖所示,步驟9.移除部分的第二基板303。值得注意的是,經步驟9.移除部分的第二基板303剩餘的厚度範圍為1-5 μm。 As shown in FIG. 4I , step 9. removes part of the second substrate 303. It is worth noting that the remaining thickness of the second substrate 303 after the part of the second substrate 303 is removed in step 9. is in the range of 1-5 μm .
如第4J圖所示,步驟10.圖案化蝕刻第二基板303。值得注意的是,經步驟10.圖案化蝕刻第二基板303後,第二基板303區分為一穿孔3031、一振動部3032及一固定部3033。As shown in FIG. 4J , step 10. patterning the second substrate 303. It is worth noting that after step 10. patterning the second substrate 303, the second substrate 303 is divided into a through hole 3031, a vibration portion 3032 and a fixed portion 3033.
如第4K圖所示,步驟11.將第一基板301具有至少一第一凹槽301A及第二凹槽301B的表面與第二基板303相互結合。值得注意的是,將第二基板303接合第三基板306的順序優先於將第二基板303接合第一基板301。其中,基板接合的順序係考量避免在接合時產生接合不良(Poor Bonding)所造成微型流體泵浦30的良率問題,因此先將第二基板303與第三基板306接合後再與第一基板301接合可以提升接合良率。As shown in FIG. 4K, step 11. The surface of the
如第4L圖所示,步驟12.移除部分的第三基板306。值得注意的是,經步驟12.移除部分的第三基板306剩餘的厚度範圍為5-20 μm。 As shown in FIG. 4L , step 12. removes a portion of the third substrate 306. It is worth noting that the remaining thickness of the third substrate 306 after the portion is removed in step 12. ranges from 5 to 20 μm .
如第4M圖所示,步驟13.依序沉積下電極層3071及壓電層3072於第三基板306上。As shown in FIG. 4M , step 13. depositing the lower electrode layer 3071 and the piezoelectric layer 3072 on the third substrate 306 in sequence.
如第4N圖所示,步驟14.圖案化蝕刻下電極層3071及壓電層3072。As shown in FIG. 4N , step 14: patterning and etching the lower electrode layer 3071 and the piezoelectric layer 3072.
如第4O圖所示,步驟15.沉積絕緣層3073,並圖案化蝕刻絕緣層3073。As shown in FIG. 40 , step 15: depositing an insulating layer 3073 and patterning and etching the insulating layer 3073 .
如第4P圖所示,步驟16.沉積上電極層3074,並圖案化蝕刻上電極層3074。As shown in FIG. 4P, step 16. depositing an upper electrode layer 3074 and pattern-etching the upper electrode layer 3074.
如第4Q圖所示,步驟17.圖案化蝕刻絕緣層3073及第三基板306。值得注意的是,經步驟17.圖案化蝕刻絕緣層3073及第三基板306後,產生至少一第三流體通道3062,第三基板306區分為致動部3063、至少一外周部3065,其中,至少一連接部3064連接致動部3063與外周部3065,至少一第三流體通道3062亦介於致動部3063與外周部3065之間。此外,值得注意的是,位於第三基板306之致動部3063上的下電極層3071、壓電層3072、絕緣層3073及上電極層3074係為壓電組件307。另外,值得注意的是,壓電層3072為圓形設置於第三基板306之致動部3063上方,使致動部3063亦呈圓形。As shown in FIG. 4Q, step 17. patterning the insulating layer 3073 and the third substrate 306. It is worth noting that after step 17. patterning the insulating layer 3073 and the third substrate 306, at least one third fluid channel 3062 is generated, and the third substrate 306 is divided into an actuating portion 3063 and at least one peripheral portion 3065, wherein at least one connecting portion 3064 connects the actuating portion 3063 and the peripheral portion 3065, and at least one third fluid channel 3062 is also between the actuating portion 3063 and the peripheral portion 3065. In addition, it is worth noting that the lower electrode layer 3071, the piezoelectric layer 3072, the insulating layer 3073 and the upper electrode layer 3074 on the actuating portion 3063 of the third substrate 306 are the piezoelectric component 307. In addition, it is worth noting that the piezoelectric layer 3072 is circularly disposed above the actuating portion 3063 of the third substrate 306, so that the actuating portion 3063 is also circular.
如第4R圖所示,步驟18.圖案化蝕刻第一基板301的一下表面。As shown in FIG. 4R , step 18 is to pattern-etch a lower surface of the
如第4S圖所示,步驟19.蝕刻第一接著層302。即完成微型流體泵浦30的製作。As shown in FIG. 4S, step 19 is to etch the
值得注意的是,如第4S圖所示之流體通槽3011為分段蝕刻,解決了先前技術的蝕刻角度過大或高深寬比蝕刻問題,並且降低了流體流通第一流體通道3012的流阻。此外,第一接著層302係為氧化矽,但厚度調整為1~5
μm,可以避免與第二基板303接合所造成的應力剝離問題。另外,第二流體通道304則以蝕刻第一基板301來定義出。
It is worth noting that the fluid channel 3011 shown in FIG. 4S is etched in sections, which solves the problem of excessive etching angle or high aspect ratio etching in the prior art, and reduces the flow resistance of the fluid flowing through the first fluid channel 3012. In addition, the
再者,值得注意的是,如第4S圖所示之第二基板303係為矽結構層,可以由SOI晶片轉移而來,厚度為1~5 μm,但不以此為限,第二基板303的厚度可視設計需求加以調整。第二基板303區分為穿孔3031、振動部3032及固定部3033三個區域,穿孔3031位於中心位置,振動部3032位於穿孔3031的周邊區域,固定部3033位於第二基板303的周緣區域。 Furthermore, it is worth noting that the second substrate 303 shown in FIG. 4S is a silicon structure layer, which can be transferred from an SOI wafer, and has a thickness of 1 to 5 μm , but is not limited thereto. The thickness of the second substrate 303 can be adjusted according to design requirements. The second substrate 303 is divided into three regions: a through hole 3031, a vibration portion 3032, and a fixed portion 3033. The through hole 3031 is located at the center, the vibration portion 3032 is located at the peripheral region of the through hole 3031, and the fixed portion 3033 is located at the peripheral region of the second substrate 303.
另外,值得注意的是,如第4S圖所示之第二接著層305係為氧化矽層-多晶矽層-氧化矽層,厚度為1~10
μm。第一接著層302的厚度可以等於第二接著層305的厚度,其厚度可以是1.1
μm,但不以此為限,第一接著層302的厚度與第二接著層305的厚度亦可以不相等,可視設計需求加以調整。第二接著層305堆疊於第二基板303上方。
In addition, it is worth noting that the second connecting layer 305 shown in FIG. 4S is a silicon oxide layer-polysilicon layer-silicon oxide layer, and has a thickness of 1-10 μm . The thickness of the first connecting
除此,值得注意的是,如第4S圖所示之第三基板306係為矽結構層,可以由SOI晶片轉移而來,厚度為10~20 μm,但不以此為限,第三基板306的厚度可視設計需求加以調整;第三基板306堆疊於第二接著層305上方,形成共振腔室3061;第三基板306具有致動部3063及外周部3065,致動部3063的外環具有第三流體通道3062及連接部3064,連接部3064係用以連接致動部3063與外周部3065。 In addition, it is worth noting that the third substrate 306 shown in FIG. 4S is a silicon structure layer, which can be transferred from an SOI chip, and has a thickness of 10 to 20 μm , but is not limited thereto. The thickness of the third substrate 306 can be adjusted according to design requirements; the third substrate 306 is stacked on top of the second bonding layer 305 to form a resonance chamber 3061; the third substrate 306 has an actuating portion 3063 and a peripheral portion 3065, and the outer ring of the actuating portion 3063 has a third fluid channel 3062 and a connecting portion 3064, and the connecting portion 3064 is used to connect the actuating portion 3063 and the peripheral portion 3065.
值得注意的是,第二基板303、第三基板306可以是單晶矽、多晶矽或非晶矽。第二基板303、第三基板306也可以使用沉積或薄化製程而來。It is worth noting that the second substrate 303 and the third substrate 306 can be single crystal silicon, polycrystalline silicon or amorphous silicon. The second substrate 303 and the third substrate 306 can also be made by deposition or thinning process.
壓電組件307更包含下電極層3071、壓電層3072、絕緣層3073及上電極層3074。壓電層3072疊設於下電極層3071上;絕緣層3073鋪設於壓電層3072之部分表面上及下電極層3071之部分表面上,其中絕緣層3073為電性絕緣;上電極層3074疊設於絕緣層3073上以及壓電層3072未設有絕緣層3073之其餘表面上。值得注意的是,壓電層3072為圓形設置於第三基板306之致動部3063上方,使致動部3063亦呈圓形。此外,值得注意的是,壓電層3072的直徑為140~500 μm,但不以此為限,壓電層3072的直徑,可視微型流體泵浦30整體大小加以調整。另外,值得注意的是,壓電層3072與致動部3063的直徑比例範圍為1:1.3~1:3.6,換言之,壓電層3072的尺寸小於致動部3063的尺寸。 The piezoelectric component 307 further includes a lower electrode layer 3071, a piezoelectric layer 3072, an insulating layer 3073, and an upper electrode layer 3074. The piezoelectric layer 3072 is stacked on the lower electrode layer 3071; the insulating layer 3073 is laid on a portion of the surface of the piezoelectric layer 3072 and a portion of the surface of the lower electrode layer 3071, wherein the insulating layer 3073 is electrically insulating; and the upper electrode layer 3074 is stacked on the insulating layer 3073 and on the remaining surface of the piezoelectric layer 3072 where the insulating layer 3073 is not provided. It is worth noting that the piezoelectric layer 3072 is circularly disposed above the actuating portion 3063 of the third substrate 306, so that the actuating portion 3063 is also circular. In addition, it is worth noting that the diameter of the piezoelectric layer 3072 is 140 to 500 μm , but is not limited thereto. The diameter of the piezoelectric layer 3072 can be adjusted according to the overall size of the microfluidic pump 30. In addition, it is worth noting that the diameter ratio of the piezoelectric layer 3072 to the actuating portion 3063 is in the range of 1:1.3 to 1:3.6. In other words, the size of the piezoelectric layer 3072 is smaller than the size of the actuating portion 3063.
透過壓電組件307的作動,致動部3063亦跟著上下振動,第二基板303的振動部3032隨之呈不同相位振動,使共振腔室3061形成負壓,流體便由流體通槽3011通過第一流體通道3012,再經過第二流體通道304,並由第二基板303的穿孔3031繼續流經共振腔室3061,最後通過第三基板306的第三流體通道3062完成流體的輸送。值得注意的是致動部3063的作動頻率為0.1~1.5MHz高頻範圍,藉此微流體可以積少成多產生更多的流量,但不以此為限,致動部3063的作動頻率可由整體微型流體泵浦30之設計加以調整。此外,值得注意的是,致動部3063呈圓形且直徑為400~550 μm,但不以此為限,致動部3063的形狀尺寸亦可由整體微型流體泵浦30之設計加以調整。 Through the actuation of the piezoelectric component 307, the actuator 3063 also vibrates up and down, and the vibrating part 3032 of the second substrate 303 vibrates in different phases, so that the resonance chamber 3061 forms a negative pressure, and the fluid passes through the first fluid channel 3012 from the fluid groove 3011, and then passes through the second fluid channel 304, and continues to flow through the resonance chamber 3061 through the through hole 3031 of the second substrate 303, and finally passes through the third fluid channel 3062 of the third substrate 306 to complete the fluid delivery. It is worth noting that the actuation frequency of the actuator 3063 is in the high frequency range of 0.1 to 1.5 MHz, so that the microfluid can accumulate a small amount to generate more flow, but it is not limited to this. The actuation frequency of the actuator 3063 can be adjusted by the design of the overall microfluid pump 30. In addition, it is worth noting that the actuator 3063 is circular and has a diameter of 400-550 μm , but is not limited thereto. The shape and size of the actuator 3063 can also be adjusted by the design of the overall microfluidic pump 30.
微型流體泵浦30的工作電壓為2~12V,值得一提的是,微型流體泵浦30的工作電壓、第三基板306的致動部3063之作動頻率、第三基板306的厚度以及第二基板303的振動部3032之共振皆會影響流體的輸送量與效率。The working voltage of the microfluid pump 30 is 2-12V. It is worth mentioning that the working voltage of the microfluid pump 30, the operating frequency of the actuator 3063 of the third substrate 306, the thickness of the third substrate 306 and the resonance of the vibration part 3032 of the second substrate 303 will all affect the delivery amount and efficiency of the fluid.
另外,值得注意的是,第三實施例與第一實施例最主要的差異在於第二接著層305係為氧化矽-多晶矽-氧化矽的複合結構,其改良的特色在於,因為共振腔室3061的空間提高了,可以適當降低擠壓膜阻尼(squeeze film damping),且當壓電組件307作動帶動第三基板306的致動部3063振動時,也較不易與第二基板303的振動部3032產生沾黏(stiction)效應。In addition, it is worth noting that the main difference between the third embodiment and the first embodiment is that the second bonding layer 305 is a composite structure of silicon oxide-polycrystalline silicon-silicon oxide. The improved feature is that because the space of the resonance chamber 3061 is increased, the squeeze film damping can be appropriately reduced, and when the piezoelectric component 307 is actuated to drive the actuator part 3063 of the third substrate 306 to vibrate, it is less likely to produce a stiction effect with the vibration part 3032 of the second substrate 303.
綜上所述,本案提供一種微型流體泵浦的製造方法,係利用半導體製程來完成微型流體泵浦的結構,以利縮小泵浦的體積,此外改善了先前技術在錐狀的第一流體通道蝕刻的問題,降低流阻,更改善了流體進入微型流體泵浦的效率,另外,於第二實施例及第三實施例更增加了第三基板的致動部與第二基板的振動部之間的距離,降低共振腔室的阻尼,也較不易使第三基板的致動部與第二基板的振動部產生沾黏效應,提高了微型流體泵浦的使用壽命,極具產業之利用價值,爰依法提出申請。In summary, this case provides a method for manufacturing a microfluid pump, which uses a semiconductor process to complete the structure of the microfluid pump to reduce the size of the pump. In addition, the problem of etching the tapered first fluid channel in the prior art is improved, the flow resistance is reduced, and the efficiency of the fluid entering the microfluid pump is improved. In addition, in the second and third embodiments, the distance between the actuating portion of the third substrate and the vibrating portion of the second substrate is increased to reduce the damping of the resonance chamber, and it is less likely to cause the actuating portion of the third substrate and the vibrating portion of the second substrate to produce a sticking effect, thereby increasing the service life of the microfluid pump. It has great industrial utilization value, and therefore an application is filed in accordance with the law.
本案得由熟習此技術之人士任施匠思而為諸般修飾,然皆不脫如附申請專利範圍所欲保護者。This case can be modified in various ways by a person familiar with this technology, but all of them will not deviate from the scope of protection sought by the attached patent application.
10、20、30:微型流體泵浦 101、201、301:第一基板 1011、2011、3011:流體通槽 101A、201A、301A:第一凹槽 101B、201B、301B:第二凹槽 1012、2012、3012:第一流體通道 102、202、302:第一接著層 103、203、303:第二基板 1031、2031、3031:穿孔 1032、2032、3032:振動部 1033、2033、3033:固定部 104、204、304:第二流體通道 105、205、305:第二接著層 3051:下層 3052:多晶矽層 3053:上層 106、206、306:第三基板 1061、2061、3061:共振腔室 1062、2062、3062:第三流體通道 1063、2063、3063:致動部 1064、2064、3064:連接部 1065、2065、3065:外周部 107、207、307:壓電組件 1071、2071、3071:下電極層 1072、2072、3072:壓電層 1073、2073、3073:絕緣層 1074、2074、3074:上電極層 90:微型流體泵浦 901:第一基板 9011:第一流體通道 902:第一接著層 9021:第二流體通道 903:第二基板 9031:矽結構層 9032:穿孔 9033:振動部 9034:固定部 9035:第二接著層 9036:共振腔室 9037:矽薄化層 9038:致動部 9039:外周部 903A:連接部 903B:第三流體通道 904:壓電組件 9041:下電極層 9042:壓電層 9043:絕緣層 9044:上電極層 S1~S19:步驟 10, 20, 30: microfluid pump 101, 201, 301: first substrate 1011, 2011, 3011: fluid channel 101A, 201A, 301A: first groove 101B, 201B, 301B: second groove 1012, 2012, 3012: first fluid channel 102, 202, 302: first bonding layer 103, 203, 303: second substrate 1031, 2031, 3031: perforation 1032, 2032, 3032: vibration part 1033, 2033, 3033: fixing part 104, 204, 304: second fluid channel 105, 205, 305: second bonding layer 3051: lower layer 3052: polysilicon layer 3053: upper layer 106, 206, 306: third substrate 1061, 2061, 3061: resonance chamber 1062, 2062, 3062: third fluid channel 1063, 2063, 3063: actuator 1064, 2064, 3064: connection part 1065, 2065, 3065: peripheral part 107, 207, 307: piezoelectric component 1071, 2071, 3071: lower electrode layer 1072, 2072, 3072: piezoelectric layer 1073, 2073, 3073: insulating layer 1074, 2074, 3074: upper electrode layer 90: microfluid pump 901: first substrate 9011: first fluid channel 902: first connecting layer 9021: second fluid channel 903: second substrate 9031: silicon structure layer 9032: perforation 9033: vibration part 9034: fixing part 9035: second connecting layer 9036: resonance chamber 9037: silicon thinning layer 9038: actuator part 9039: peripheral part 903A: connecting part 903B: third fluid channel 904: piezoelectric component 9041: lower electrode layer 9042: piezoelectric layer 9043: Insulation layer 9044: Upper electrode layer S1~S19: Steps
第1A圖至第1C圖為本案之微型流體泵浦的製造方法的步驟流程圖。 第2A圖至第2S圖為本案之微型流體泵浦的製造方法之第一實施例步驟示意圖。 第3A圖至第3T圖為本案之微型流體泵浦的製造方法之第二實施例步驟示意圖。 第4A圖至第4S圖為本案之微型流體泵浦的製造方法之第三實施例步驟示意圖。 第5圖為先前技術中微型流體泵浦的示意圖。 Figures 1A to 1C are step flow charts of the manufacturing method of the microfluid pump of the present invention. Figures 2A to 2S are schematic diagrams of the steps of the first embodiment of the manufacturing method of the microfluid pump of the present invention. Figures 3A to 3T are schematic diagrams of the steps of the second embodiment of the manufacturing method of the microfluid pump of the present invention. Figures 4A to 4S are schematic diagrams of the steps of the third embodiment of the manufacturing method of the microfluid pump of the present invention. Figure 5 is a schematic diagram of a microfluid pump in the prior art.
S1~S7:步驟 S1~S7: Steps
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