TW202414812A - Led wafer, circuit board, display and method for making same - Google Patents

Abstract

Embodiments of the present application relate to the field of display technology, and aim to solve the technical problem of improving production yield of displays using micro LEDs or mini LEDs as display pixels. An LED wafer, a circuit board, a display, and a method for making the display are provided. A partial area of the LED wafer is defined as an LED crystal block. The LED crystal block includes a light-transmitting substrate, a plurality of LEDs, a plurality of P electrodes and a plurality of N electrodes, and a plurality of N wirings. A row of the P electrodes and a row of the N electrodes are alternately and periodically repeated. A side of each LED away from the substrate is provided with one of the P-electrodes and one of the N-electrodes spaced apart from each other. Each of the N wirings is in direct contact with and electrically connected to the N-electrodes of all the LEDs in a corresponding row.

Description

LED wafer, circuit board, display and manufacturing method thereof

The present application relates to the field of display technology, and more specifically, to an LED wafer, a circuit board, a display, and a method for manufacturing the display.

A known method for preparing a display using micro light emitting diodes (micro LEDs) or mini light emitting diodes (mini LEDs) as display pixels includes a mass transfer step of transferring a plurality of micro LEDs or mini LEDs from a wafer to a circuit board. The circuit board is known to include at least two layers of wiring, one layer of wiring is a wiring, which is used to electrically connect the P electrodes of all light-emitting elements corresponding to the wiring, and the other layer of wiring is a column wiring, which is used to electrically connect the N electrodes of all light-emitting elements corresponding to the column wiring. In addition, the circuit board also needs to be provided with dense through holes to connect the wiring of the lower layer of the two layers of wiring to the pads of the wiring of the upper layer. However, as the display's resolution requirements become higher and higher, the size of the light-emitting element becomes smaller and smaller. Due to the limitations of the minimum drill hole size and the minimum drill hole tolerance of the circuit board, the area of each through hole plus the tolerance in the conventional circuit board is even larger than the pad of the light-emitting element. In addition, as the display's resolution requirements become higher and higher, the spacing between adjacent light-emitting elements becomes smaller and smaller. Also due to the limitations of the minimum drill hole size and the minimum drill hole tolerance of the circuit board, adjacent through holes in the conventional circuit board are almost short-circuited together. Therefore, the production yield of conventional displays using micro LED or mini LED as display pixels needs to be improved.

The first aspect of the present application provides an LED wafer. A partial area of the LED wafer is defined as an LED die, and the LED die includes: A light-transmitting substrate; A plurality of LEDs, spaced apart on the substrate, arranged as a plurality of columns along a first direction, and arranged as a plurality of rows along a second direction intersecting the first direction; A plurality of P electrodes and a plurality of N electrodes, the plurality of P electrodes and the plurality of N electrodes are arranged alternately and periodically, with one row of the P electrodes and one row of the N electrodes being arranged at intervals on a side of each LED away from the substrate; and A plurality of N-electrode traces, each of which is in direct contact with and electrically connected to the N electrodes of all the LEDs in a corresponding row.

The LED wafer of the first aspect of the present application electrically connects the N electrodes of all LEDs in a row through an N-pole wiring, so that when the LED wafer is electrically tested, it is not necessary to make a top pin corresponding to the N electrode of each LED for power supply and testing. Instead, it is only necessary to make a top pin corresponding to the N electrode of one of the LEDs in each row for power supply and testing. Therefore, the electrical testing of the LED wafer can reduce the cost of the jig for making the top pin and reduce the error rate of defective top pins. Moreover, the substrate of the LED wafer is light-transmitting or transparent, so that after the LED chip is bonded to the circuit board, the substrate does not need to be removed, but is retained in the display and covered as a transparent cover. Thereby, in the display manufacturing process, the step of separating the substrate from the LED is reduced, simplifying the process. Furthermore, since the substrate can function as a transparent cover plate, there is no need to set up an additional cover plate, thus saving the lamination process and reducing the cost of the cover plate.

The second aspect of the present application provides a circuit board. The circuit board includes: an insulating substrate; a plurality of P-pole traces, spaced apart on the substrate; a plurality of P-pole pads, spaced apart on the substrate, the plurality of P-pole pads being arranged in a plurality of rows along a first direction, all the P-pole pads in each row being electrically connected by a corresponding P-pole trace, the plurality of P-pole pads being arranged in a plurality of rows along a second direction intersecting the first direction, the two adjacent P-pole pads in each row being insulated and isolated; and A plurality of N-pole pads are arranged in a plurality of rows along the second direction, each row of the N-pole pads has at least two N-pole pads, wherein the plurality of P-pole pads and the plurality of N-pole pads are arranged alternately and periodically with one row of the P-pole pads and one row of the N-pole pads; and a driving chip is located on the substrate and electrically connected to the plurality of P-pole traces and the plurality of N-pole pads.

In the circuit board of the second aspect of the present application, the N-pole pad, the P-pole pad and the P-pole trace are in the same circuit layer, and the P-pole pads in the same row for connecting LEDs are connected together by the P-pole trace, so there is no need to set a large number of dense through holes, thus avoiding the reduction in the yield of the circuit board and the display caused by the drilling process. In particular, the yield of the through holes of the known circuit board becomes worse and worse as the LED spacing becomes smaller and smaller, and even cannot be made. However, the circuit board of the embodiment of the present application, because it is a single-layer LED trace setting, does not need through holes, which is conducive to improving the yield, especially to improving the yield and production capacity of high-resolution displays that use mini LEDs or micro LEDs as light-emitting elements.

The third aspect of the present application provides a method for preparing a display. The method for preparing the display comprises: Providing the circuit board described in the second aspect of the present application, and cutting the LED wafer described in the first aspect of the present application to obtain the LED crystal block; and The LED crystal block is bonded to the circuit board, wherein one row of the P electrodes corresponds to one row of the P electrode pads, the multiple P electrode pads are electrically connected to the multiple P electrodes one by one, one row of the N electrodes corresponds to one row of the N electrode pads, the number of the multiple N electrode pads is less than or equal to the number of the multiple N electrodes, and each N electrode pad is electrically connected to a corresponding N electrode. The driver chip is electrically connected to the P electrodes of a row of the LEDs via one P electrode trace, one row of the P electrode pads, and the driver chip is electrically connected to the N electrodes of a row of the LEDs via one row of the N electrode pads, one N electrode trace.

The display manufacturing method of the third aspect of the present application integrally bonds the LED crystal block to the circuit board, and can realize the transfer of a large number of LEDs at one time. Compared with the method of aligning a large number of LEDs one by one and transferring them to the circuit board, the number of alignment times is reduced, the manufacturing process is simplified, and the yield and production capacity of mass transfer are improved. Moreover, in the display manufacturing method, after the LED crystal block is bonded to the circuit board, the substrate does not need to be removed, and the substrate can be used as a cover plate of the display, thereby saving the cover plate bonding cost and the cover plate material cost.

The fourth aspect of the present application provides a display. The display comprises the circuit board described in the second aspect of the present application and an LED chip combined with the circuit board; The LED chip comprises: A light-transmitting substrate; A plurality of LEDs, spaced on the substrate, arranged in a plurality of columns along a first direction and in a plurality of rows along a second direction intersecting the first direction; A plurality of P electrodes and a plurality of N electrodes, the plurality of P electrodes and the plurality of N electrodes being arranged alternately and periodically in a row of the P electrodes and a row of the N electrodes, and one P electrode and one N electrode are spaced on a side of each LED away from the substrate; and A plurality of N-pole traces, each of which is in direct contact with and electrically connected to the N electrodes of all the LEDs in a corresponding row; Among them, one row of the P electrodes corresponds to one row of the P electrode pads, the multiple P electrode pads are electrically connected to the multiple P electrodes one by one, one row of the N electrodes corresponds to one row of the N electrode pads, the number of the multiple N electrode pads is less than or equal to the number of the multiple N electrodes, each N electrode pad is electrically connected to a corresponding N electrode, the driver chip is electrically connected to the P electrodes of a row of the LEDs through one P electrode trace and one row of the P electrode pads, and the driver chip is electrically connected to the N electrodes of a row of the LEDs through one row of the N electrode pads and one N electrode trace.

In the display of the fourth aspect of the present application, the N-electrode of the LED is electrically connected via the N-electrode trace on the LED chip, and the P-electrode of the LED is electrically connected via the P-electrode trace on the circuit board. Since the N-electrode trace is arranged on the LED chip instead of the circuit board, the circuit board is a single-layer trace, and no through-holes are required, thus avoiding the reduction in the yield of the circuit board and the display caused by the drilling process. Moreover, since no through-holes are required on the circuit board, it is beneficial to improve the yield of the circuit board, especially to improve the yield and production capacity of high-resolution displays that use mini LEDs or micro LEDs as light-emitting elements.

FIG1 is a schematic plan view of a known circuit board. As shown in FIG1 , the circuit board includes a plurality of N-pole pads 2 and P-pole pads 3. The arrangement of the plurality of N-pole pads 2 and P-pole pads 3 is a row of N-pole pads 2 and a row of P-pole pads 3 that are alternately and periodically arranged. An N-pole pad 2 and an adjacent P-pole pad 3 form a group, which are used to electrically connect the N-pole and P-pole of an LED, respectively. The circuit board also includes two layers of wiring, one layer of wiring is the wiring 4, which is used to electrically connect the P electrodes of all LEDs corresponding to the wiring 4, and the other layer of wiring is the row wiring (not shown), which is used to electrically connect the N electrodes of all LEDs corresponding to the row wiring, wherein the two layers of wiring connect the wiring of the lower layer to the pad of the wiring of the upper layer through the through hole 5. However, as the display has higher and higher requirements for resolution, the size of LEDs is getting smaller and smaller. Due to the limitation of the minimum diameter of the drilling hole size of the circuit board of 50μm and the minimum drilling hole tolerance of 50μm on one side, in the known circuit board, the area of each through hole plus the tolerance is even larger than the pad of the light-emitting element. In addition, as the resolution requirements of displays become higher and higher, the spacing between adjacent light-emitting elements is also getting smaller and smaller. Similarly, due to the limitations of the minimum drilling hole size and the minimum drilling hole tolerance of the circuit board, adjacent through holes in the conventional circuit board are almost short-circuited together. In other words, when the pitch of LEDs is less than 150μm, the drilling process yield will drop significantly. Therefore, the production yield of conventional displays using micro LEDs or mini LEDs as light-emitting elements needs to be improved.

The following will clearly and completely describe the technical solutions in the embodiments of this application in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments.

FIG2 is a schematic plan view of an LED wafer of an embodiment of the present application. As shown in FIG2, an LED wafer 10a includes a circular substrate 11. A partial area of the LED wafer 10a is defined as an LED die 10. The LED die 10 includes a substrate 11, a plurality of LEDs 12, a plurality of N electrodes 131, a plurality of P electrodes 132, and a plurality of N electrode traces 141. The plurality of LEDs 12 are spaced apart on the substrate 11, and are arranged in a plurality of columns along a first direction D1, and are arranged in a plurality of rows along a second direction D2 intersecting the first direction D1. In the embodiment of the present application, the first direction D1 is perpendicular to the second direction D2. The plurality of P electrodes 132 are spaced apart and arranged in a plurality of rows and columns, and the plurality of N electrodes 131 are spaced apart and arranged in a plurality of rows and columns. Each LED 12 corresponds to a P electrode 132 and an N electrode 131. The plurality of P electrodes 132 and the plurality of N electrodes 131 are arranged alternately and periodically in a row of P electrodes 132 and a row of N electrodes 131. Each N electrode wiring 141 extends along the first direction D1 and directly contacts and electrically connects with the N electrodes 131 of all LEDs 12 in a corresponding row. The plurality of N electrode wirings 141 are arranged at intervals along the second direction D2.

It should be noted that in the embodiment of the present application, the LED wafer refers to the overall structure on which LED stacks are grown on a wafer. The diameter size of the wafer is, for example, 6 inches, 8 inches, 12 inches, or even larger specifications such as 14 inches, 15 inches, 16 inches, 20 inches or more. The LED block can refer to a partial area on the LED wafer (not yet cut from other parts of the LED wafer 10a), or it can refer to a separated block that has been cut from the LED wafer. In addition, the shape and size of the LED block can be divided according to the shape and size of the display area of the display to be formed, and it can be any shape. In the embodiment shown in Figure 2, the LED block 10 is rectangular. In other embodiments, the shape of the LED chip 10 can be divided according to the shape and size of the display area of the display to be formed. For example, if the display area is circular, the LED chip 10 can be circular, or if the display area is irregular, the LED chip 10 can be irregular.

In some embodiments, LED 12 is a micro LED, which refers to an LED 12 with a grain size of less than 100 microns. In other embodiments, LED 12 is a mini LED. Mini LED is also called a sub-millimeter light-emitting diode, which has a size between a traditional LED and a micro LED, and generally refers to an LED with a grain size of approximately 100 to 200 microns.

FIG3 is a schematic cross-sectional view along line III-III of FIG2 . FIG4 is a schematic cross-sectional view along line IV-IV of FIG2 . Please refer to FIG2 to FIG4 in combination. Two adjacent LEDs 12 are arranged at intervals along the second direction D2. Each LED 12 includes an N-type semiconductor layer 121, a light-emitting layer 122, and a P-type semiconductor layer 123. The N-type semiconductor layer 121 is located on the surface of the substrate 11. The light-emitting layer 122 is located between the N-type semiconductor layer 121 and the P-type semiconductor layer 123. The P-electrode 132 is located on a side of the P-type semiconductor layer 123 of the LED 12 away from the substrate 11. The N-electrode 131 is located on a side of the N-type semiconductor layer 121 of a corresponding LED 12 away from the substrate 11. The N-pole trace 141 is at least partially located between the N-type semiconductor layer 121 and the N-electrode 131, and is directly in contact with and electrically connected to the N-type semiconductor layer 121 and the N-electrode 131, respectively. The N-pole trace 141 can be formed by a photolithography process. The N-electrode 131 includes an N-electrode metal layer 1311 and an N-electrode solder layer 1312. Along the second direction D2, the N-electrode metal layer 1311 completely covers the corresponding N-pole trace 141, and is in direct contact with the corresponding N-type semiconductor layer 121. The N-electrode solder layer 1312 covers the surface of the N-electrode metal layer 1311 away from the substrate 11. The P-electrode 132 includes a P-electrode metal layer 1321 and a P-electrode solder layer 1322. Along the second direction D2, the P-electrode metal layer 1321 directly contacts the corresponding P-type semiconductor layer 123 and partially covers the corresponding P-type semiconductor layer 123. The P-electrode solder layer 1322 covers the surface of the P-electrode metal layer 1321 away from the substrate 11. The material of the N-electrode solder layer 1312 and the P-electrode solder layer 1322 is, for example, tin. When the LED chip 10 is bonded to the circuit board, the side of the substrate 11 facing away from the LED 12 can be irradiated with laser so that the N-electrode solder layer 1312 and the P-electrode solder layer 1322 are melted and bonded to the corresponding N-electrode pad and P-electrode pad on the circuit board.

The material of the N-type semiconductor layer 121 is, for example, N-type gallium nitride, the material of the P-type semiconductor layer 123 is, for example, P-type gallium nitride, and the material of the light-emitting layer 122 is, for example, a multi-quantum well layer, but not limited thereto.

The LED die 10 further includes a barrier 15 located between adjacent LEDs 12 to prevent light interference between adjacent LEDs 12 .

Specifically, the baffle 15 is located on the surface of the substrate 11 and directly contacts the N-type semiconductor layer 121 and the N-electrode 131 of one LED 12, and directly contacts the N-type semiconductor layer 121, the light-emitting layer 122, and the P-type semiconductor layer 123 of another LED 12. The material of the baffle 15 is a light-proof material, such as a black matrix. The baffle 15 can be formed by a photolithography process.

Along the first direction D1, the N-type semiconductor layer 121 of all LEDs 12 in a corresponding row is covered by the N-type trace 141, and is directly in contact with and electrically connected to the N-electrodes 131 of all LEDs 12 in the corresponding row. The portion of the N-electrode trace 141 between two adjacent LEDs 12 is in direct contact with the surface of the substrate 11. The N-electrode 131 of each LED 12 is located away from the surface of the substrate 11 at the corresponding N-electrode trace 141.

In the embodiment of the present application, the N electrodes 131 of all LEDs 12 in a row are electrically connected by an N electrode wiring 141, so that when the LED wafer 10a is electrically tested, it is not necessary to make a pin corresponding to the N electrode 131 of each LED 12 for power supply and testing, but only the N electrode 131 corresponding to one LED 12 in each row of LEDs 12 needs to be made to supply power and test. Therefore, the electrical testing of the LED wafer 10a can reduce the cost of the fixture for making the pin and reduce the error rate of bad pins.

In addition, in the embodiment of the present application, the substrate 11 is light-transmitting or transparent, and its material is, for example, sapphire. By setting the substrate 11 to be light-transmitting, after the LED crystal block 10 is bonded to the circuit board, the substrate 11 does not need to be removed, but is retained in the display and used as a transparent cover. In this way, in the display manufacturing process, the step of separating the substrate 11 from the LED 12 is reduced, simplifying the process. Moreover, since the substrate 11 can be used as a transparent cover lens, there is no need to set up an additional cover, saving the bonding process and reducing the cost of the cover.

Fig. 5 is a schematic plan view of a circuit board according to an embodiment of the present application. The circuit board is used to be bonded with the above-mentioned LED die to form a display.

As shown in FIG5 , the circuit board 20 includes an insulated substrate 21, a plurality of P-pole traces 241, a plurality of P-pole pads 232, and a plurality of N-pole pads 231. Specifically, the plurality of P-pole traces 241 are arranged at intervals along the first direction D1. The plurality of P-pole pads 232 are located at intervals on the substrate 21, and are arranged in a plurality of rows along the first direction D1, and are arranged in a plurality of rows along the second direction D2. The two adjacent P-pole pads 232 in each row are insulated and isolated. All the P-pole pads 232 in each row are electrically connected by a corresponding P-pole trace 241. The plurality of N-pole pads 231 are located at intervals on the substrate 21, and are arranged in a plurality of rows along the second direction D2. The plurality of P-pole pads 232 and the plurality of N-pole pads 231 are arranged alternately and periodically in a row of P-pole pads 232 and a row of N-pole pads 231 .

In the embodiment shown in FIG. 5 , each row has two N-pole pads 231. Each N-pole pad 231 is either between two P-pole pads 232 in the first column or between two P-pole pads 232 in the last column. Each P-pole pad 232 is used to be electrically connected to a corresponding P-electrode 132 of an LED 12, and each N-pole pad 231 is used to be electrically connected to a corresponding N-electrode 131 of an LED 12. A P-pole pad 232 and an N-pole pad 231 in a dotted frame form a group to electrically connect the P-electrode 132 and the N-electrode 131 of the same LED 12, respectively. Therefore, on the circuit board 20, for the LEDs 12 to be received, the first and last columns have N-pole pads 231 and P-pole pads 232, respectively, and the middle column between the first and last columns has only P-pole pads 232, but no N-pole pads 231. In this way, the number of pads on the circuit board 20 can be reduced, the welding time can be reduced, and the defect rate caused by welding can be reduced.

In other embodiments, the number of N-pole pads 231 in each row may be more than two. For example, an N-pole pad 231 is provided in the first column and the last column respectively. In the middle column, an N-pole pad 231 may also be provided on the P-pole trace 241 between the corresponding P-pole pads 232 (the P-pole trace 241 and the N-pole pad 231 may be insulated by providing a solder mask 25). In this way, the positions for the electrical connection between the N-pole pad 231 on the circuit board 20 and a row of LEDs 12 may be increased, thereby avoiding the problem of failure of the electrical connection between the circuit board 20 and the row of LEDs 12 when the electrical connection between the first and last N-pole pads 231 and the N-pole 131 of the corresponding LED 12 is poor.

Among the plurality of rows of pads formed by the plurality of P-pole pads 232 and the plurality of N-pole pads 231, at least two pads at the beginning of the first row, at the end of the first row, at the beginning of the last row, and at the end of the last row (or pads at the corners of the circuit board 20) include a main body and a first protrusion and a second protrusion extending from the main body in the first direction D1 and the second direction D2, respectively. The pads at non-corner positions include only the main body. The main body is generally rectangular, but not limited thereto.

By providing protrusions on the pads at the corners of the circuit board 20, they can be used as alignment marks for the bonding of the LED 12 during the transfer of the LED die 10. In this way, there is no need to make additional alignment marks on the circuit board 20, which saves space on the circuit board 20 and facilitates the design of a narrow frame for the display.

Specifically, in the embodiment shown in FIG. 5 , the first row of pads is an N-pole pad 231, and the last row of pads is a P-pole pad 232. The N-pole pad 231 at the beginning of the first row and the N-pole pad 231 at the end of the first row each include a body portion 231a for electrically connecting to the N-electrode 131 of the LED 12, and a first protrusion 231b extending from the body portion 231a along the first direction D1 and a second protrusion 231c extending from the body portion 231a along the second direction D2. The first protrusion 231b of the N-pole pad 231 at the beginning of the first row and the N-pole pad 231 at the end of the first row extend from the negative direction and the positive direction of the first direction, respectively.

The P-pole pad 232 at the beginning of the last row and the P-pole pad 232 at the end of the last row each include a body portion 232a for electrically connecting to the P-electrode 231 of the LED 12, and a first protrusion 232b extending from the body portion 232a along the first direction D1 and a second protrusion 232c extending from the body portion 232a along the second direction D2. The P-pole pad 232 at the beginning of the last row and the first protrusion 232b at the end of the last row extend from the negative direction and the positive direction of the first direction, respectively.

When the LED chip 10 is bonded to the circuit board 20, it is only necessary to align the two adjacent edges of the corresponding LED 12 on the LED chip 10 with the boundaries of the body and the first protrusion, and the boundaries of the body and the second protrusion respectively; or, to align the vertices of the corners of the corresponding LED 12 on the LED chip 10 with the intersection of the body, the first protrusion, and the second protrusion. In some embodiments, the first protrusion 231b and the first protrusion 232b extend beyond the first direction D1 by more than 40μm, and the second protrusion 231c and the second protrusion 232c extend beyond the second direction D2 by more than 40μm (such as 40μm, 50μm, etc.). When the length of the first protrusion 231b and/or the second protrusion 231c extending beyond the main body 231a is too long, and when the first protrusion 232b and/or the second protrusion 232c extending beyond the main body 232a is too long, it will occupy a large space of the circuit board 20; and when the length of the first protrusion 231b and/or the second protrusion 231c extending beyond the main body 231a is too short, and when the first protrusion 232b and/or the second protrusion 232c extending beyond the main body 232a is too short, it will affect the alignment accuracy.

Compared to the known double-layer routing design in which the N-pole pad and the P-pole pad of the LED are connected respectively by the routing layer and the column routing layer, and a large number of dense through holes are provided, in the embodiment of the present application, the N-pole pad 231, the P-pole pad 232 and the P-pole routing 241 are in the same wiring layer, and the P-pole pad 232 in the same column for connecting the LED 12 is connected together by the P-pole routing 241, and there is no need to provide a large number of dense through holes, thereby avoiding the decrease in the yield of the circuit board and the display caused by the drilling process. In particular, the conventional circuit board has a lower yield rate of through holes as the LED spacing becomes smaller and smaller, and even cannot be manufactured. However, the circuit board of the embodiment of the present application, because it is a single-layer LED wiring arrangement, does not need through holes, which is conducive to improving the yield rate, especially the yield rate and production capacity of high-resolution displays using mini LEDs or micro LEDs as light-emitting elements. In addition, because there is no need for through holes, the circuit board 20 of the embodiment of the present application can even use materials that are not easy to be through holes as the substrate 21, such as glass.

It is understandable that the circuit board 20 further includes a driver chip 22 (shown in FIG. 7 ) and a solder mask 25 (shown in FIG. 7 ) located on the substrate 21. The driver chip 22 is electrically connected to a plurality of P-pole traces 241 and a plurality of N-pole pads 231. The solder mask 25 at least covers a portion of each P-pole trace 241 between two adjacent P-pole pads 232. When the LED chip 10 is bonded to the circuit board 20, the N-pole pad 231 on the circuit board 20 is electrically connected to the N-pole of the corresponding LED 12, and the P-pole pad 232 is electrically connected to the P-pole 132 of the corresponding LED 12. The solder mask 25 is located between the N-pole 131 and the P-pole trace 241 to insulate and isolate the N-pole 131 and the P-pole trace 241. The driver chip 22 is electrically connected to the P-pole 132 of a row of LEDs 12 via a P-pole trace 241, a row of P-pole pads 232, and thereby applies a driving voltage to the P-pole 132 of the corresponding row of LEDs 12. The driver chip 22 is electrically connected to the N electrode 131 of a row of LEDs 12 via a row of N electrode pads 231 and an N electrode trace 141, so that the N electrodes 131 of the corresponding row of LEDs 12 maintain a common cathode voltage (such as grounding). When the P electrode 132 and the N electrode 131 of the LED 12 have a voltage difference, the LED 12 emits light.

The present application embodiment also provides a method for preparing a display, which includes the following steps S1 and S2.

Step S1: Provide a circuit board and cut the LED wafer to obtain LED chips.

Specifically, in step S1, the circuit board is, for example, the circuit board 20 shown in FIG. 5. The LED wafer is, for example, the LED 12 wafer shown in FIG. 2. In step S1, the pads and lines on the circuit board 20 can be designed according to the shape and size of the display area of the display 100, and the LED die 10 of the corresponding shape and size can be cut out.

Please refer to FIG. 2 and FIG. 5 , a row of P electrodes 132 on the LED chip 10 corresponds to a row of P electrode pads 232 on the circuit board 20, and the number of P electrodes 132 on the LED12 chip is the same as the number of P electrode pads 232 on the circuit board 20, and the arrangement positions correspond one to one. A row of N electrodes 131 on the LED chip 10 corresponds to a row of N electrode pads 231 on the circuit board 20, and the number of N electrodes 131 on the LED12 chip is greater than the number of N electrode pads 231 on the circuit board 20. In terms of position arrangement, the first and last rows of N electrodes 131 on the LED chip 10 correspond one to one with the first and last rows of N electrode pads 231 on the circuit board 20. In addition, the N-electrode 131 corresponding to the middle column on the LED chip 10 is not provided with an N-electrode pad 231 on the circuit board 20, but is located at a position corresponding to the P-electrode trace 241 (it should be noted that a solder mask 25 is provided on the P-electrode trace 241 at this position, and the material of the solder mask 25 is, for example, solder mask ink, so that after the LED chip 10 is transferred to the circuit board 20, the N-electrode 131 and the P-electrode trace 241 are insulated and isolated).

Step S2: Bond the LED chip to the circuit board.

Specifically, please refer to FIG. 2, FIG. 5 and FIG. 6, and take the pad at the upper left corner as an example, and transfer the LED chip 10 to the circuit board 20 so that the long side of the left side of the LED 12 at the upper left corner of the LED chip 10 is aligned with the boundary between the first protrusion 231b and the body 231a, and the short side of the upper side of the LED 12 at the upper left corner of the LED chip 10 is aligned with the boundary between the second protrusion 231c and the body 231a, and then transfer the LED chip 10 to the circuit board 20. The pad at the lower left corner, the pad at the lower right corner, and the pad at the upper right corner are transferred similarly as the alignment mark.

After the LED chip 10 is transferred to the circuit board 20 , a laser is used to irradiate the side of the LED chip 10 away from the circuit board 20 to melt the N-electrode solder layer 1312 and the P-electrode solder layer 1322 , so that the multiple P-electrode pads 232 are electrically connected to the multiple P-electrodes 132 one by one, and each N-electrode pad 231 is electrically connected to a corresponding N-electrode 131 . The driver chip 22 is electrically connected to the P electrode 132 of a row of LEDs 12 via a P electrode trace 241 and a row of P electrode pads 232, and the driver chip 22 is electrically connected to the N electrode 131 of a row of LEDs 12 via a row of N electrode pads 231 and a N electrode trace 141. Thus, the display 100 is obtained.

It should be noted that in the embodiment of the present application, the substrate 11 of the LED crystal block 10 is light-transmissive or transparent. After the LED 12 crystal block is bonded to the circuit board 20, the substrate 11 does not need to be removed. The substrate 11 can be used as a cover plate of the display 100, thereby saving the cover plate bonding cost and the cover plate material cost. In addition, the manufacturing method of the display, the LED crystal block 10 is integrally bonded to the circuit board 20, which can realize a large number of LEDs to be transferred at one time. Compared with the method of aligning a large number of LEDs one by one and transferring them to the circuit board, the number of alignment times is reduced, the process is simplified, and the yield and production capacity of mass transfer are improved.

FIG7 is a schematic cross-sectional view taken along line VII-VII of FIG6. As shown in FIG6 and FIG7, the display 100 includes a circuit board 20 and an LED chip 10 combined with the circuit board 20. The LED chip 10 includes a light-transmitting substrate 11, a plurality of LEDs 12 spaced apart on the substrate 11, a plurality of P electrodes 132, a plurality of N electrodes 131, and a plurality of N electrode traces 141. The plurality of LEDs 12 are arranged in a plurality of rows along a first direction D1 and in a plurality of lines along a second direction D2 intersecting the first direction D1. Each LED 12 includes an N-type semiconductor layer 121, a light-emitting layer 122, and a P-type semiconductor layer 123, wherein the N-type semiconductor layer 121 is located on the surface of the substrate 11, and the light-emitting layer 122 is located between the N-type semiconductor layer 121 and the P-type semiconductor layer 123. Each P electrode 132 is located on a side of the P-type semiconductor layer 123 of a corresponding LED 12 away from the substrate 11. Each N-electrode 131 is located on a side of the N-type semiconductor layer 121 of a corresponding LED 12 away from the substrate 11, wherein the plurality of P-electrodes 132 and the plurality of N-electrodes 131 are arranged alternately and periodically in a row of P-electrodes 132 and a row of N-electrodes 131. Each N-electrode trace 141 covers the N-type semiconductor layer 121 of all LEDs 12 in a corresponding row, and is in direct contact with and electrically connected to the N-electrodes 131 of all LEDs 12 in the corresponding row. A row of P electrodes 132 corresponds to a row of P electrode pads 232, and the plurality of P electrode pads 232 are electrically connected to the plurality of P electrodes 132 one by one. A row of N electrodes 131 corresponds to a row of N electrode pads 231, and the number of the plurality of N electrode pads 231 is less than or equal to the number of the plurality of N electrodes 131. Each N electrode pad 231 is electrically connected to The driver chip 22 is electrically connected to a corresponding N electrode 131 through a P electrode trace 241 and a P electrode pad 232 and a row of LEDs 12 through a row of N electrode pads 231 and a N electrode trace 141. The first protrusion 231b, the first protrusion 232b, the second protrusion 231c, and the second protrusion 232c all extend beyond the substrate 11.

In the display of the embodiment of the present application, the N-electrode of the LED is electrically connected via the N-electrode trace on the LED chip, and the P-electrode of the LED is electrically connected via the P-electrode trace on the circuit board. Since the N-electrode trace is arranged on the LED chip instead of the circuit board, the circuit board is a single-layer trace, and no through-holes are required, thus avoiding the reduction in the yield of the circuit board and the display caused by the drilling process. Moreover, since no through-holes are required on the circuit board, it is beneficial to improve the yield of the circuit board, especially to improve the yield and production capacity of high-resolution displays that use mini LEDs or micro LEDs as light-emitting elements.

The above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention is described in detail with reference to the preferred embodiments, ordinary technicians in this field should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

10a: LED wafer 10: LED block 11: Substrate 12: LED 121: N-type semiconductor layer 122: Light-emitting layer 123: P-type semiconductor layer 131: N-electrode 1311: N-electrode metal layer 1312: N-electrode solder layer 132: P-electrode 1321: P-electrode metal layer 1322: P-electrode solder layer 141: N-electrode trace 15: Baffle 20: Circuit board 21: Base 22: Driver chip 231, 2: N-electrode pad 231a, 232a: Main body 231b, 232b: first protrusion 231c, 232c: second protrusion 232, 3: P-pole pad 241: P-pole trace 25: solder mask D1: first direction D2: second direction 100: display 4: trace 5: through hole

FIG. 1 is a schematic plan view of a conventional circuit board.

FIG. 2 is a schematic plan view of an LED wafer according to an embodiment of the present application.

FIG3 is a schematic cross-sectional view along line III-III in FIG2 .

FIG. 4 is a schematic cross-sectional view along line IV-IV of FIG. 2 .

FIG5 is a schematic plan view of a circuit board according to an embodiment of the present application.

FIG. 6 is a schematic plan view of a display according to an embodiment of the present application.

FIG. 7 is a schematic cross-sectional view along line VII-VII of FIG. 6 .

10:LED crystal block

11: Base material

12:LED

131:N electrode

132:P electrode

141: N-pole routing

20: Circuit board

21: Base

231b, 232b: first protrusion

231c, 232c: second protrusion

241: P pole routing

D1: First direction

D2: Second direction

100: Display

Claims (10)

An LED wafer, wherein a partial area of the LED wafer is defined as an LED crystal block, and the LED crystal block includes: A light-transmitting substrate; A plurality of LEDs, spaced on the substrate, arranged in a plurality of columns along a first direction and arranged in a plurality of rows along a second direction intersecting the first direction; A plurality of P electrodes and a plurality of N electrodes, wherein the plurality of P electrodes and the plurality of N electrodes are arranged alternately and periodically, with one row of the P electrodes and one row of the N electrodes being spaced apart on a side of each LED away from the substrate; and A plurality of N-electrode traces, each of which is in direct contact with and electrically connected to the N electrodes of all the LEDs in a corresponding row. As described in claim 1, the LED wafer, wherein the LED die further includes a baffle located between adjacent LEDs to prevent light interference between adjacent LEDs. A circuit board, comprising: an insulating substrate; a plurality of P-pole traces, spaced apart on the substrate; a plurality of P-pole pads, spaced apart on the substrate, the plurality of P-pole pads being arranged in a plurality of rows along a first direction, all the P-pole pads in each row being electrically connected via a corresponding P-pole trace, the plurality of P-pole pads being arranged in a plurality of rows along a second direction intersecting the first direction, the two adjacent P-pole pads in each row being insulated and isolated; and A plurality of N-pole pads are arranged in a plurality of rows along the second direction, each row of the N-pole pads has at least two N-pole pads, wherein the plurality of P-pole pads and the plurality of N-pole pads are arranged alternately and periodically with one row of the P-pole pads and one row of the N-pole pads; and a driving chip is located on the substrate and electrically connected to the plurality of P-pole traces and the plurality of N-pole pads. A circuit board as described in claim 3, wherein the circuit board further includes a solder mask layer, wherein the solder mask layer at least covers a portion of each of the P-pole traces located between two adjacent P-pole pads. A circuit board as described in claim 3 or 4, wherein, among the multiple rows of solder pads formed by the multiple P-pole solder pads and the multiple N-pole solder pads, among the solder pad at the beginning of the first row, the solder pad at the end of the first row, the solder pad at the beginning of the last row, and the solder pad at the end of the last row, at least two solder pads include a main body and a first protrusion and a second protrusion extending beyond the main body from the first direction and the second direction, respectively. A method for preparing a display, comprising: Providing a circuit board as described in any one of claims 3 to 5, and cutting the LED wafer according to claim 1 or 2 to obtain the LED crystal block; and The LED crystal block is bonded to the circuit board, wherein one row of the P electrodes corresponds to one row of the P electrode pads, the multiple P electrode pads are electrically connected to the multiple P electrodes one by one, one row of the N electrodes corresponds to one row of the N electrode pads, the number of the multiple N electrode pads is less than or equal to the number of the multiple N electrodes, and each N electrode pad is electrically connected to a corresponding N electrode. The driver chip is electrically connected to the P electrodes of a row of the LEDs via one P electrode trace, one row of the P electrode pads, and the driver chip is electrically connected to the N electrodes of a row of the LEDs via one row of the N electrode pads, one N electrode trace. A method for preparing a display as described in claim 6, wherein, in the step of bonding the LED chip to the circuit board, the protrusions are used as alignment marks under the condition that "among the plurality of rows of pads formed by the plurality of P-pole pads and the plurality of N-pole pads, at least two pads among the pads at the beginning of the first row, the pads at the end of the first row, the pads at the beginning of the last row, and the pads at the end of the last row include a main body and a first protrusion and a second protrusion extending from the first direction and the second direction beyond the main body, respectively." A display, comprising a circuit board as described in any one of claims 3 to 5 and an LED chip combined with the circuit board; The LED chip comprises: A light-transmitting substrate; A plurality of LEDs, spaced apart on the substrate, the plurality of LEDs arranged in a plurality of columns along a first direction and in a plurality of rows along a second direction intersecting the first direction; A plurality of P electrodes and a plurality of N electrodes, the plurality of P electrodes and the plurality of N electrodes being arranged alternately and periodically in a row of the P electrodes and a row of the N electrodes, and one of the P electrodes and one of the N electrodes being spaced apart on a side of each of the LEDs away from the substrate; and A plurality of N-pole traces, each of which is in direct contact with and electrically connected to the N-electrodes of all the LEDs in a corresponding row; Among them, one row of the P electrodes corresponds to one row of the P electrode pads, the multiple P electrode pads are electrically connected to the multiple P electrodes one by one, one row of the N electrodes corresponds to one row of the N electrode pads, the number of the multiple N electrode pads is less than or equal to the number of the multiple N electrodes, each N electrode pad is electrically connected to a corresponding N electrode, the driver chip is electrically connected to the P electrodes of a row of the LEDs through one P electrode trace and one row of the P electrode pads, and the driver chip is electrically connected to the N electrodes of a row of the LEDs through one row of the N electrode pads and one N electrode trace. A display as described in claim 8, wherein, in the case where "the circuit board further includes a solder resist layer, the solder resist layer at least covers a portion of each of the P-pole traces located between two adjacent P-pole pads", the solder resist layer is located between the N-electrode and the P-pole traces to insulate and isolate the N-electrode and the P-pole traces. A display as described in claim 8 or 9, wherein, in the case of "among the multiple rows of solder pads formed by the multiple P-pole solder pads and the multiple N-pole solder pads, among the solder pad at the beginning of the first row, the solder pad at the end of the first row, the solder pad at the beginning of the last row, and the solder pad at the end of the last row, at least two solder pads include a main body and a first protrusion and a second protrusion extending from the first direction and the second direction beyond the main body, respectively", the first protrusion and the second protrusion extend beyond the substrate.

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