JP2004047617A - Mounting structure of electronic component and manufacturing method thereof - Google Patents

Mounting structure of electronic component and manufacturing method thereof Download PDF

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Publication number
JP2004047617A
JP2004047617A JP2002201295A JP2002201295A JP2004047617A JP 2004047617 A JP2004047617 A JP 2004047617A JP 2002201295 A JP2002201295 A JP 2002201295A JP 2002201295 A JP2002201295 A JP 2002201295A JP 2004047617 A JP2004047617 A JP 2004047617A
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Prior art keywords
electronic component
insulating layer
thickness
mounting structure
chip
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JP2002201295A
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Japanese (ja)
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Toshiaki Iwabuchi
岩渕　寿章
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Sony Corp
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Sony Corp
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Priority to JP2002201295A priority Critical patent/JP2004047617A/en
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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L2224/2405—Shape
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    • H01L2224/82009—Pre-treatment of the connector or the bonding area
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Led Device Packages (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mounting structure of an electronic component and its manufacturing method wherein a connection hole is easily formed and reliability in wiring is enhanced. <P>SOLUTION: The thickness of an insulating layer 2 is so controlled as to match a difference in thicknesses of a resin chip 5 and an IC chip 6 to be mounted. The insulating layers 2 and 3 are partially removed and mounted directly on a substrate 1. The resin chip 5 is mounted on an insulating layer 3. Thus, an electrode 9 of the IC chip 6 is formed to have the same height as that of an electrode 11b of the resin chip 5. Therefore, the connection holes for these electrodes are worked in batch under identical work conditions, and a connection hole 15a of bottom layer wiring can be made shallow with a low aspect ratio for proper wiring. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、電子部品の実装構造及びその製造方法に関し、特に、接続孔の加工が容易な電子部品の実装構造及びその製造方法に関するものである。
【０００２】
【従来の技術】
従来、画像表示装置の製造方法としては、ウェーハからダイシングして電子部品（例えば半導体チップ）を分離し、分離した電子部品をダイシングシートからチップトレイに移送し、所定の加工及び転写工程を経た後に、チップトレイから電子部品を真空吸着でピックアップして、基板にマウント若しくは接続した後に配線するという方法が知られている。
【０００３】
【発明が解決しようとする課題】
図１１及び図１２は、上記した画像表示装置（以下、単に装置と称することがある。）の一例を示す概略図であり、それぞれ発光素子として、発光ダイオード（以下、ＬＥＤと称することがある。）４０ａを樹脂封止した樹脂チップ３５ａ、又はＬＥＤ４０ｂを樹脂封止した樹脂チップ３５ｂが実装されている。
【０００４】
いずれも、基板３１上に積層された絶縁層３２（厚さ：約５μｍ）、３３（厚さ：約５μｍ）上に、前記樹脂チップ３５ａ又は３５ｂが設けられ、これに隣接してこれらのＬＥＤ駆動用のＩＣチップ３６が並設されている。そしてこれらを被覆する絶縁層３４に接続孔４３、４４、４５ａ、４５ｂを形成後に、配線４６が形成され、全体の高さＨは約１１０〜１３０μｍに形成されている。
【０００５】
そして、図１１に示す装置３０のＬＥＤ４０ａは、上部にｐ電極４１ａと下部にｎ電極（図示省略）とが形成され、下地成長層４７上に形成された六角錐形状のＬＥＤ４０ａにおける発光が、六角錐の斜面内側での反射を伴い基板３１側から取り出される。
【０００６】
また、図１２に示す装置５０のＬＥＤ４０ｂ（プレーナタイプ）は、下部にｐ電極４１ａと上部にｎ電極４１ｂとを有し、ＬＥＤ４０ｂにおける発光が同様に基板３１側から取り出せるようになっている。なお、ｐ電極４１ａの反対側の電極４１ｃはプロービング検査用である。
【０００７】
しかしながら、図１１及び図１２に示すように、基板３１からの樹脂チップ３５ａ又は３５ｂの高さＡ（約５０〜７０μｍ）及びＩＣチップ３６の高さＢ（約８０〜９０μｍ）が異なるため、これとの接続孔４３と４４（５０〜２００μｍφ）の深さも異なり、これ以外の下地配線３８ａ、３８ｂとの接続孔４５ａ、４５ｂを合せて、４種類の深さの接続孔が必要であり、それぞれ接続孔の加工条件が異なる上に、深い接続孔はアスペクト比が高く、導通を得ることが困難であった。このため、特に、上記ＡとＢが異なることが問題となっている。
【０００８】
また、これらのチップ部品のマウント精度は転写位置により決められていて、転写を繰り返すことにより、同一位置に多数のデバイスをマウントするため位置ずれが累積され、配線基板上にマウントした時には大きく位置がずれることがあった。
【０００９】
なお、このような電子部品の実装に関して、特開平９−３２１４０８号公報においては、半導体チップの端子にスタッドバンプを形成後に、半導体チップをプリント基板に埋め込み、これを被覆した絶縁部材に孔をあけてスタッドバンプを露出させ、これと配線パターンとを接続することにより、強固な配線ができることが開示されている。
【００１０】
また、特開平１０−２８２１４５号公報には、ガラス基板に設けた凹みに電子部品を配し、その電極に接続した配線を凹み以外の領域に延設し、この配線上に同じ高さのバンプを形成することにより、ＩＣ検査を容易にできることが開示されている。
【００１１】
また、特開平１０−２２３８３２号公報には、プリント基板上に電子部品を特定の高さに支持し、この状態で電子部品を基板にはんだ付けすることにより、低コストで良好なはんだ付けが可能になることが開示されている。
【００１２】
また、特開平１０−２２３８３２号公報には、基板上に設けた導電層上に、電極にバンプを設けた半導体チップ及び導電ブロックを配し、これを樹脂膜で被覆して表面を平坦化することで、ベア半導体チップの高さのばらつきを吸収できることが開示されている。
【００１３】
また、特開平１１−２６６３１号公報には、半導体素子の突起状電極の先端に導電性接着材を設けることにより、これを搭載する基板のうねりに対する突起電極の高さを調整できることが開示されている。
【００１４】
しかし、上記公報（以下、先願発明と称する。）のいずれも上記問題を解決するものではなく、本発明とは構成要件が異なると共に、本発明の構成を意図したものではない。
【００１５】
そこで本発明の目的は、接続孔の形成が容易、かつ配線の信頼性が高められる電子部品の実装構造及びその製造方法を提供することにある。
【００１６】
【課題を解決するための手段】
即ち、本発明は、実装基体上に複数の電子部品が固定され、これらの電子部品を被覆する絶縁層に形成された接続孔を介して各電子部品の電極が取り出されている電子部品の実装構造において、
前記実装基体上に設けられた下地層の厚みの制御によって、前記複数の電子部品の各電極に対する前記接続孔の深さがほぼ同一となっている、電子部品の実装構造（以下、本発明の実装構造と称する。）に係るものである。
【００１７】
本発明の実装構造によれば、基体上に設ける下地層の厚みを制御するので、各電子部品の電極の位置を同一高さに形成できるため、これらの電子部品を被覆する絶縁層において、各電子部品の電極に対する接続孔を同一加工条件の下で、一括加工することができる。その結果、接続不良のない良好な配線を形成することができ、信頼性が高められると共に、接続孔の種類が減り、製造工程の簡素化された電子部品の実装構造を提供できる。
【００１８】
また、本発明は、実装基体上に複数の電子部品が固定され、これらの電子部品を被覆する絶縁層に形成された接続孔を介して各電子部品の電極が取り出されている電子部品の実装構造を製造する方法において、
前記実装基体上に制御された厚みに下地層を形成する工程と、
前記下地層上に前記複数の電子部品を固定する工程と、
前記絶縁層を形成する工程と、
この絶縁層に前記接続孔を形成する工程と
を有する、電子部品の実装構造を製造する方法（以下、本発明の製造方法と称する。）に係るものである。
【００１９】
本発明の製造方法によれば、実装基体上に制御された厚みに下地層を形成し、この下地層上に複数の電子部品を固定し、この電子部品を被覆する絶縁層を形成してこの絶縁層に接続孔を形成するので、電子部品の電極に対する接続孔を同一加工条件で形成できるため、上記した本発明の実装構造と同様の効果が奏せられる、再現性の良い製造方法が提供できる。
【００２０】
【発明の実施の形態】
以下、本発明の好ましい実施の形態を説明する。
【００２１】
上記した本発明の実装構造及び製造方法においては、厚みの制御された前記下地層の面に、前記実装基体上の最下層の配線を設けることにより、この配線の位置を高めることが可能になるため、アスペクト比の低い接続孔を形成でき、接続不良のない配線により信頼性が高められる点で望ましい。
【００２２】
この場合、前記複数の電子部品の厚みの差に対応する膜厚の下地絶縁層を形成し、この絶縁層上に、厚みの小さい方の電子部品を固定することにより、厚みの小さい電子部品の電極と厚みの大きい電子部品の電極の高さを同一にし易い点で望ましい。
【００２３】
但し、前記最下層の配線を前記実装基体に直接設けて、前記下地層に形成した接続孔を介して、前記下地層上に前記最下層の配線を導出するようにしてもよい。
【００２４】
更に、前記複数の電子部品のうち厚みの大きい方の電子部品の下部において、前記下地絶縁層を除去して凹部を形成し、この凹部内に前記厚みの大きい電子部品を固定することが、この電子部品の位置精度が高められると共に、厚みの小さい電子部品との高さを制御し易い点で望ましい。
【００２５】
これにより、前記複数の電子部品間が、前記絶縁層に形成された前記接続孔を介して電気的に良好に接続され、配線の信頼性が高められる点で望ましい。
【００２６】
この場合、前記複数の電子部品の一方を発光素子とし、他方を発光素子駆動用の半導体チップとして、更に、前記発光素子を樹脂封止したチップ状態で実装することにより、画像表示装置として構成することができる。
【００２７】
次に、上記した好ましい実施の形態を図面参照下で具体的に説明する。
【００２８】
実施の形態１
図１は、本実施の形態による実装構造の装置２５を示し、（ａ）は概略断面図、（ｂ）はその一部分の拡大断面図である。
【００２９】
この装置２５は、既述した図１２と同様なタイプのＬＥＤ５を具備したものであるが、従来と異なる特徴は、一方の電子部品としての樹脂チップ５の電極１１ｂと、他方の電子部品としてのＩＣチップ６の電極９の高さが同一に形成されていることにより、これらの電極に対する接続孔１３及び１４が同一であること、ＩＣチップ６が基板１上に直接マウントされていること、最下層の配線８ａに対する接続孔１５ａが浅く形成され、このアスペクト比が低く形成されていることである。
【００３０】
この実装構造は、図１（ａ）に示すように、基板１上に積層された絶縁層２、３の一部分が選択的に除去され、この部分にＩＣチップ６がダイボンディング材７を介して基板１上に直接固定され、樹脂チップ５は積層された絶縁層３の上にダイボンディング材７を介して固定されている。その結果、樹脂チップ５の電極１１ｂとＩＣチップ６の電極９が同一の高さに形成されているが、この高さはＩＣチップ６の厚さ（約７０〜８０μｍ）と樹脂チップ５の厚さ（約４０〜６０μｍ）の差に一致させて、絶縁層２の厚さを制御することにより形成されている。
【００３１】
即ち、既述したように、図１１又は図１２に示した従来の装置において、１層目の絶縁層３２の厚さ：約５μｍ、２層目の絶縁層３３の厚さ：約５μｍ、絶縁層３２又は３３を含むＡの高さ：約５０〜７０μｍ及びＢの高さ：約８０〜９０μｍであることから、両絶縁層の厚みの合計１０μｍを差引くと、Ｂの高さのうちのＩＣチップ３６の厚さは７０〜８０μｍ、Ａの高さのうちの樹脂チップ３５ａ（又は３５ｂ）の厚さは４０〜６０μｍである。
【００３２】
従って、図１１又は図１２における実際のＢとＡの差（Ａ−Ｂ）は１０〜４０μｍであることから、本実施の形態における１層目の絶縁層２の厚さ（ｔ）は１０〜４０μｍ（例えば１０μｍ）に形成し、樹脂チップ５及びＩＣチップ６の電極を同一高さに形成している。
【００３３】
つまり、図１（ｂ）に示すように、１層目の絶縁層２の厚さｔ、ＩＣチップ６の厚さｘ及び樹脂チップ５の厚さｙは、ｔ＝ｘ−ｙの関係になっている。また、樹脂チップ５はＬＥＤ１０及びその電極等を封止するために、上部に封止樹脂の厚みｚを有して全体の厚さｙが構成されている。従って、２層目の絶縁層３の厚さｚは封止樹脂の厚みに合せることにより、ＩＣチップ６の電極９と樹脂チップ５の電極１１ｂの高さを同一にすることができる。
【００３４】
そして、図１（ａ）に示すように、１層目の絶縁層２の上に最下層の配線８ａが配され、２層目の絶縁層３の上に２層目の下層配線８ｂが配されることにより、クロス配線を可能としている。このようにクロス配線に不可欠な２層構造の上方の絶縁層３の上に樹脂チップ５が配されるため、２層目の絶縁層３の厚み（ｚ）を樹脂チップ５の封止樹脂の厚み（ｚ）と同様の膜厚に形成することにより、ｔ＝ｘ−ｙの関係を構成し、樹脂チップ５の電極１１ｂとＩＣチップ６の電極９の高さを同一に配置している。
【００３５】
また、最下層の配線８ａが、制御された膜厚（従来より厚い）の絶縁層２の上に配置されることにより、基板１からの高さｈ（図１参照）は従来に比べて高くなるため、この接続孔１５ａの深さが浅くなり、アスペクト比が低く形成されている。
【００３６】
従って、図１（ａ）に示すように、ＩＣチップ６及び樹脂チップ５の電極９、１１ｂに対する接続孔１３、１４が同一に形成されるため、ＩＣチップ６と樹脂チップ５の電極９、１１ｂに対する接続孔の種類が減り、製造プロセスを簡素化することができると共に、下層配線８ａに対しても低いアスペクト比の接続孔１５ａを形成できる。
【００３７】
図２〜図４に上記装置の製造プロセスの概略断面図を示す。
【００３８】
まず、図２（ａ）に示す基板１上に、図２（ｂ）に示すように１層目の絶縁層２を形成し、この一端（図中左側）寄りにアルミニウム（Ａｌ）からなる最下層の配線８ａを配する。この際、実装するＩＣチップ６と樹脂チップ５の厚みの差ｔを予め測定しておき、この差に一致した厚さに絶縁層２を形成する。
【００３９】
次いで、図２（ｃ）に示すように、２層目の絶縁層３を積層する。そしてこの膜厚は上記した如く、この上に固定する樹脂チップ５の封止樹脂の厚さ（図１におけるｚ）と同一の厚さに形成する。
【００４０】
次いで、図２（ｄ）に示すように、最下層の配線８ａとは反対側の端部寄りの２層目の絶縁層３上に、Ａｌからなる次の下層配線８ｂを配する。なお、本実施の形態の下層配線は２層であるが、配線層が多層の場合は、２層目の配線８ｂの上に更に絶縁層を積層して、配線層を更に形成する。
【００４１】
次いで、図２（ｅ）に示すように、ＩＣチップ６をマウントするために、絶縁層２、３の除去部１８を形成する。従って、配線はこの除去部を通らないように設計しておく。これにより、ＩＣチップ６と樹脂チップ５の高さを同一にし易いと共に、位置ずれが吸収されてＩＣチップ６のマウント精度を高めることができる。
【００４２】
次いで、図３（ｆ）に示すように、上記除去部１８にＩＣチップ６をダイボンディング材７を介して固定し、これに隣接して絶縁層３上に樹脂チップ５をダイボンディング材７を介して固定する。
【００４３】
次いで、図３（ｇ）に示すように、マウントしたＩＣチップ６及び樹脂チップ５を含む絶縁層３の上部を被覆するように、絶縁層４を形成する。
【００４４】
次いで、図３（ｈ）に示すように、各下層配線８ａ、８ｂ及びＩＣチップ６の電極９と樹脂チップ５の電極１１ｂに対し、これらの電極と接続させるための接続孔１５ａ、１５ｂ、１３及び１４をレーザビーム１９の照射によって形成する。
【００４５】
ＩＣチップ６の電極９及び樹脂チップ５の電極１１ｂも下層配線８ａ、８ｂと同様にアルミニウムで形成されているため、レーザ光照射時に熱吸収率の低いアルミニウムの特性によって、電極等がレーザによって損傷され難いため、高出力の短波長レーザによる接続孔の加工が容易である。
【００４６】
レーザビーム１９による接続孔の加工は、図３（ｈ）に示すように、接続孔の深さ毎にマスク２０を選択し、レンズ２１により焦点を絞り、更に、深い接続孔用のレーザ又は浅い接続孔用のレーザを用い、レーザビーム１９のショット数を変えてアブレーションすることにより、各種の深さの接続孔を任意に形成でき、この加工に伴って接続孔の径及びテーパが形成される。
【００４７】
特に、ＩＣチップ６及び樹脂チップ５の電極に対する接続孔１３、１４は同一条件の下で一括加工できる。また、下層配線８ａ、８ｂに対する接続孔１５ａ、１５ｂは、底部の面積も大きく、テーパ角も大きくとれるので接続孔入り口での配線の段切れも生じ難くなる。
【００４８】
次いで、図４（ｉ）に示すように、各接続孔１５ａ、１５ｂ、１３及び１４を含む絶縁層４の上面にスパッタリング等の物理的成膜法によりＣｕ（銅）膜１６Ａを被着する。この際、電極等のＡｌとＣｕに接続性のよい無電解Ｎｉめっき（図示省略）を予め施しておくことにより、Ａｌからなる下層配線８ａ、８ｂ、ＩＣチップ６の電極９、樹脂チップ５の電極１１ｂ等とＣｕ膜１６Ａとの接続性及び導電性を高めることができる。
【００４９】
次いで、図４（ｊ）に示すように、被着したＣｕ膜１６ＡをフォトリソグラフィーでパターニングしてＣｕ配線１６を形成する。そして、配線１６の形成後、保護層（図示せず）を配線１６上に形成し、画像表示装置のパネルを完成する。
【００５０】
本実施の形態によれば、実装する樹脂チップ５とＩＣチップ６との厚みの差に一致させて、基板１上に配する１層目の絶縁層２の厚みを制御し、２層目の絶縁層３を樹脂チップ５の封止樹脂の厚み（ｚ）と同一の厚さで積層して、樹脂チップ５をこの絶縁層３上にマウントし、ＩＣチップ６はこれらの絶縁層２、３を選択的に除去して基板１上に直接マウントするので、ＩＣチップ６の電極９と樹脂チップ５の電極１１ｂの基板１上における高さを同一に配置することができる。
【００５１】
従って、ＩＣチップ６の電極９及び樹脂チップ５の電極１１ｂに対する接続孔１３、１４を同一の加工条件で同一の深さに一括加工にて形成でき、製造工程を簡素化できる。しかも、制御によって厚く形成された１層目の絶縁層２上に最下層の配線８ａが配されるので、この接続孔１５ａが従来よりも浅く、低いアスペクト比に形成できる。これによりＩＣチップ６及び樹脂チップ５の電極９、１１ｂとの接続孔１３、１４と同様に、最下層の配線８ａとの接続孔１５等についても接続不良のない良好な配線を形成でき、信頼性を高めることができる。
【００５２】
上記したように、本実施の形態は、既述した先願発明が意図していない構成と特徴とを有しており、先願発明のいずれも、その構成を本実施の形態に適用することは不可能であり、無理に適用しても本実施の形態の目的を実現することはできない。
【００５３】
実施の形態２
図５は、本実施の形態による実装構造の装置２６を示し、（ａ）は概略断面図、（ｂ）はその一部分の拡大断面図である。
【００５４】
この装置２６も、基本的な構造は実施の形態１とほぼ同様であるが、厚みの薄い樹脂チップ５Ａ（電極１１ａ、１１ｂが封止樹脂外に露出している。）を実装している点が異なる。
【００５５】
即ち、この樹脂チップ５Ａも２層目の絶縁層３上に接着材１７を介して固定され、これ以外は実施の形態１と同様の構造になっている。従って、実施の形態１の樹脂チップ５に比べて、封止用の樹脂が用いられていないため、この樹脂相当分だけ厚みが薄くなるが、この場合も、ＩＣチップ６と樹脂チップ５Ａの厚みの差に一致するように、絶縁層２、３の厚みを制御することにより、ＩＣチップ６の電極９と樹脂チップ５Ａの電極１１ｂの高さが同一に形成されている。
【００５６】
つまり、図５（ｂ）に示すように、この場合の絶縁層の厚さｔは、１層目の絶縁層２及び２層目の絶縁層３の合計の厚さであり、樹脂チップ５Ａの厚さｙ’は接着材１７を含む厚さであり、実施の形態１と同様のＩＣチップ６の厚みｘとの関係は、ｔ＝ｘ−ｙ’となっている。
【００５７】
従って、最下層の配線８ａを実施の形態１と同様に形成するとすれば、１層目の絶縁層２の厚みは変らないため、２層目の絶縁層３の厚みを制御して合計の厚さｙ’が形成されている。
【００５８】
これにより、ＩＣチップ６の電極９及び樹脂チップ５Ａの電極１１ｂを、基板１上において同一の高さに形成することができるため、この両チップの各電極９、１１ｂに対する接続孔１３、１４を同一の加工条件で同一に形成することができ、実施の形態１と同等の効果を得ることができる。
【００５９】
実施の形態３
図６は、本実施の形態による実装構造の装置２７を示し、（ａ）は概略断面図、（ｂ）はその一部分の拡大断面図である。
【００６０】
この装置も、基本的な構造は実施の形態１とほぼ同様であるが、ＩＣチップ６Ａの厚みが実施の形態１の場合よりも薄く形成されている点が異なる。
【００６１】
即ち、各種の半導体チップが薄型化傾向にあり、薄型化されたＩＣチップ６Ａを用いた実装構造である。従って、図６に示すように、このＩＣチップ６Ａのマウント部は２層目の絶縁層３のみを除去し、ＩＣチップ６Ａは１層目の絶縁層２の上に固定されている。これ以外は実施の形態１と同様な構成である。
【００６２】
従って、図６（ｂ）に示すように、絶縁層２、３の厚み及び樹脂チップ５の厚みは実施の形態１と変らず、ＩＣチップ６Ａの厚みのみが異なるため、ＩＣチップ６Ａの厚み（ｘ’）は絶縁層３の厚み（ｚ’）との関係となり、ｚ’＝ｘ’−ｙ＋ｚとなっている。
【００６３】
このように、この場合も、ＩＣチップ６Ａと樹脂チップ５の厚みの差に一致させて、絶縁層３の厚みを制御することにより、ＩＣチップ６Ａの電極９と樹脂チップ５の電極１１ｂの高さが同一に形成されている。
【００６４】
また、本実施の形態は図６に示すように、ＩＣチップ６Ａを１層目の絶縁層２の上にマウントしているが、ＩＣチップ６Ａの厚さに応じて絶縁層の除去も異なる。即ち、絶縁層２の一部分も除去する必要がある場合や、絶縁層３の一部分のみの除去で足りる場合など、種々の形態が想定されるが、いずれの場合も、その状態に応じたＩＣチップ６Ａと樹脂チップ５の厚みの差を基に絶縁層の厚みを制御する。
【００６５】
これにより、ＩＣチップ６Ａの電極９及び樹脂チップ５の電極１１ｂの高さを同一に形成できるため、この両チップの各電極９、１１ｂに対する接続孔１３、１４を同一の加工条件で同一に形成することができ、実施の形態１と同等の効果を得ることができる。
【００６６】
図７に、実施の形態１の変形例を示す。
【００６７】
この装置２８が実施の形態１と異なる点は、最下層の配線８ａが基板１上に直接形成され、この配線８ａ上にプラグ２３を設けて、接続孔が２層目の配線８ｂに対する接続孔１５ｂと同一に形成されていることである。
【００６８】
従って、これ以外は実施の形態１と同様な構造であるため、ＩＣチップ６の電極９及び樹脂チップ５の電極１１ｂとの接続孔１３、１４が、同一の加工条件で同一に形成できることに加え、下層配線８ａ、８ｂとの接続孔１５ｂが同一の加工条件で、同一のアスペクト比に形成できるため、接続孔の種類を更に減らせる利点がある。
【００６９】
図８〜図１０にこの製造プロセスの概略断面図を示すが、この製造プロセスも実施の形態１の製造プロセス（図２〜図４）と類似点が多いので、異なる点を中心に説明する。
【００７０】
即ち、図８（ａ）に示すように、まず基板１上に最下層の配線８ａを形成し、この上に絶縁層２、３を積層する（図８（ｂ））。
【００７１】
次いで、図８（ｃ）に示すように、上記配線８ａに対する接続孔２４がレーザ加工され、この接続孔２４にプラグ２３を２層目の絶縁層３を超える高さに設ける。そしてこの高さは、これと反対側の端部側の絶縁層３上に形成する２層目の下層配線８ｂと同一高さに形成する（図８（ｄ））。
【００７２】
次いで、図８（ｅ）に示すように、ＩＣチップ６をマウント部するための絶縁層２、３の選択的除去を行い、続いて、この除去部１８へのＩＣチップ６の固定及び絶縁層３上への樹脂チップ５の固定を行う（図９（ｆ））。
【００７３】
次いで、図９（ｇ）〜図１０（ｊ）に示すプロセスを、実施の形態１におけるプロセス（図３（ｇ）〜図４（ｊ）参照）と同様に行う。
【００７４】
上記した各実施の形態は、本発明の技術的思想に基づいて更に変形が可能である。
【００７５】
例えば、ＩＣチップ６（６Ａ）と樹脂チップ５（５Ａ）との厚みの差に一致させて絶縁層の厚みを制御する方法は、実施の形態と同等の効果が得られれば任意であってもよく、また、実施の形態以外の制御方法で行ってもよい。
【００７６】
また、実施の形態では、一般的に樹脂チップ５よりも厚いＩＣチップ６をマウントするために、絶縁層２、３に除去部１８を設けたが、樹脂チップ５の方がＩＣチップ６よりも厚い場合には、上記除去部１８を樹脂チップ５の側に形成してもよい。
【００７７】
また、下層配線が更に多層である場合は、更に絶縁層を配線毎に積層すると共に、ＩＣチップと樹脂チップの電極の高さを同一にするための絶縁層の厚みの制御も、実態に即して適宜にすることができる。
【００７８】
また、実施の形態は、ＩＣチップ６（６Ａ）と樹脂チップ５（５Ａ）の実装に関するものであるが、図１１に示した如き構造の素子をはじめ、他の任意の素子の実装に適用することができる。
【００７９】
また、実施の形態における各部の材質、構造及び形状等も適宜にすることができる。
【００８０】
【発明の作用効果】
上述した如く、本発明の電子部品の実装構造及びその製造方法によれば、基体上に設ける下地層の厚みを制御するので、各電子部品の電極の位置を同一高さに形成できるため、これらの電子部品を被覆する絶縁層において、各電子部品の電極に対する接続孔を同一加工条件の下で、一括加工することができる。その結果、接続不良のない良好な配線を形成することができ、信頼性が高められると共に、接続孔の種類が減り、製造工程の簡素化された電子部品の実装構造を提供できる。
【図面の簡単な説明】
【図１】本発明の実施の形態１による実装構造を示し、（ａ）は概略断面図、（ｂ）は一部の拡大断面図である。
【図２】同、実装構造の製造プロセスを示す概略断面図である。
【図３】同、実装構造の他の製造プロセスを示す概略断面図である。
【図４】同、実装構造の更に他の製造プロセスを示す概略断面図である。
【図５】同、実施の形態２による電子部品の実装構造を示し、（ａ）は概略断面図、（ｂ）は一部分の拡大断面図である。
【図６】同、実施の形態３による電子部品の実装構造を示し、（ａ）は概略断面図、（ｂ）は一部分の拡大断面図である。
【図７】同、実施の形態１の変形例による実装構造の概略断面図である。
【図８】同、実装構造の製造プロセスを示す概略断面図である。
【図９】同、実装構造の他の製造プロセスを示す概略断面図である。
【図１０】同、実装構造の更に他の製造プロセスを示す概略断面図である。
【図１１】従来例による電子部品の実装構造の一例を示す概略断面図である。
【図１２】従来例による電子部品の実装構造の他の一例を示す概略断面図である。
【符号の説明】
１…基板、２、３、４…絶縁層、５、５Ａ…樹脂チップ、
６、６Ａ…ＩＣチップ、７…ダイボンディング材、８ａ、８ｂ…下層配線、
９…電極、１０…発光ダイオード、１１ａ…ｐ電極、１１ｂ…ｎ電極、
１３、１４、１５ａ、１５ｂ、２４…接続孔、１６…配線、１６Ａ…銅、
１７…接着材、１８…除去部、１９…レーザビーム、２０…マスク、
２１…レンズ、２３…プラグ、２５、２６、２７、２８…装置、
ｈ…最下層配線の基板からの高さ、ｔ…１層目の絶縁層の厚み、
ｘ、ｘ’、Ｂ…ＩＣチップの厚み、ｙ、ｙ’Ａ…樹脂チップの厚み、
ｚ…２層目の絶縁層の厚み（又は、樹脂チップ上部の厚み）[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a mounting structure of an electronic component and a method of manufacturing the same, and more particularly, to a mounting structure of an electronic component in which connection holes can be easily processed and a method of manufacturing the same.
[0002]
[Prior art]
Conventionally, as a method of manufacturing an image display device, an electronic component (for example, a semiconductor chip) is separated by dicing from a wafer, the separated electronic component is transferred from a dicing sheet to a chip tray, and after a predetermined processing and transfer process, A method is known in which electronic components are picked up from a chip tray by vacuum suction, mounted or connected to a substrate, and then wired.
[0003]
[Problems to be solved by the invention]
FIGS. 11 and 12 are schematic diagrams illustrating an example of the above-described image display device (hereinafter, may be simply referred to as a device). Each of the light-emitting elements may be referred to as a light-emitting diode (hereinafter, may be referred to as an LED). ) A resin chip 35a in which resin 40a is sealed with resin or a resin chip 35b in which LED 40b is sealed with resin is mounted.
[0004]
In any case, the resin chip 35a or 35b is provided on an insulating layer 32 (thickness: about 5 μm) or 33 (thickness: about 5 μm) laminated on a substrate 31, and these LED chips are provided adjacent to the resin chip 35a or 35b. The driving IC chips 36 are provided side by side. After forming the connection holes 43, 44, 45a, and 45b in the insulating layer 34 that covers them, the wiring 46 is formed, and the entire height H is formed to be about 110 to 130 μm.
[0005]
The LED 40a of the device 30 shown in FIG. 11 has a p-electrode 41a formed on the upper part and an n-electrode (not shown) formed on the lower part, and emits light from the hexagonal pyramid LED 40a formed on the base growth layer 47. The light is taken out from the substrate 31 side with the reflection inside the slope of the pyramid.
[0006]
The LED 40b (planar type) of the device 50 shown in FIG. 12 has a p-electrode 41a in the lower part and an n-electrode 41b in the upper part, so that the light emitted from the LED 40b can be similarly extracted from the substrate 31 side. The electrode 41c on the opposite side of the p-electrode 41a is for probing inspection.
[0007]
However, as shown in FIGS. 11 and 12, the height A (about 50 to 70 μm) of the resin chip 35a or 35b from the substrate 31 and the height B (about 80 to 90 μm) of the IC chip 36 are different. The connection holes 43 and 44 (50 to 200 μmφ) also have different depths, and the connection holes 45a and 45b with the other underlying wirings 38a and 38b are combined to form connection holes of four different depths. In addition to the different processing conditions for the connection holes, the deep connection holes have a high aspect ratio, making it difficult to obtain electrical continuity. For this reason, there is a problem that A is different from B in particular.
[0008]
In addition, the mounting accuracy of these chip components is determined by the transfer position. By repeating the transfer, many devices are mounted at the same position, and the positional deviation is accumulated. There was a shift.
[0009]
Regarding the mounting of such electronic components, in Japanese Patent Application Laid-Open No. 9-321408, after forming stud bumps on terminals of a semiconductor chip, the semiconductor chip is embedded in a printed circuit board, and a hole is formed in an insulating member covering the printed circuit board. It is disclosed that a strong wiring can be formed by exposing a stud bump and connecting it to a wiring pattern.
[0010]
Japanese Patent Application Laid-Open No. 10-282145 discloses that an electronic component is arranged in a recess provided in a glass substrate, a wiring connected to the electrode is extended to a region other than the recess, and bumps having the same height are provided on the wiring. It is disclosed that the IC inspection can be facilitated by forming the.
[0011]
Japanese Patent Application Laid-Open No. Hei 10-223832 discloses that low-cost and good soldering can be achieved by supporting an electronic component on a printed board at a specific height and soldering the electronic component to the board in this state. Is disclosed.
[0012]
Japanese Patent Application Laid-Open No. Hei 10-223832 discloses that a semiconductor chip and a conductive block provided with bumps on electrodes are arranged on a conductive layer provided on a substrate, and this is covered with a resin film to planarize the surface. Thus, it is disclosed that variations in the height of bare semiconductor chips can be absorbed.
[0013]
Japanese Patent Application Laid-Open No. H11-26631 discloses that by providing a conductive adhesive at the tip of a protruding electrode of a semiconductor element, the height of the protruding electrode with respect to the undulation of a substrate on which it is mounted can be adjusted. I have.
[0014]
However, none of the above publications (hereinafter, referred to as the prior invention) solves the above-mentioned problem, and the constitutional requirements are different from the present invention, and the constitution of the present invention is not intended.
[0015]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a mounting structure of an electronic component in which connection holes can be easily formed and wiring reliability is improved, and a method of manufacturing the same.
[0016]
[Means for Solving the Problems]
That is, the present invention provides a method for mounting an electronic component in which a plurality of electronic components are fixed on a mounting base and electrodes of each electronic component are taken out through connection holes formed in an insulating layer covering these electronic components. In structure
By controlling the thickness of a base layer provided on the mounting substrate, the mounting structure of an electronic component (hereinafter, referred to as the present invention), in which the depth of the connection hole for each electrode of the plurality of electronic components is substantially the same. Mounting structure).
[0017]
According to the mounting structure of the present invention, since the thickness of the underlayer provided on the base is controlled, the positions of the electrodes of each electronic component can be formed at the same height. The connection holes for the electrodes of the electronic component can be collectively processed under the same processing conditions. As a result, it is possible to form a favorable wiring without a connection failure, to improve reliability, to reduce the types of connection holes, and to provide a mounting structure of an electronic component with a simplified manufacturing process.
[0018]
In addition, the present invention also relates to a mounting of an electronic component in which a plurality of electronic components are fixed on a mounting base, and electrodes of the respective electronic components are taken out through connection holes formed in an insulating layer covering these electronic components. In the method of manufacturing a structure,
Forming an underlayer to a controlled thickness on the mounting substrate;
Fixing the plurality of electronic components on the underlayer,
Forming the insulating layer;
Forming the connection hole in the insulating layer;
(Hereinafter, referred to as a manufacturing method of the present invention).
[0019]
According to the manufacturing method of the present invention, an underlayer is formed at a controlled thickness on a mounting substrate, a plurality of electronic components are fixed on the underlayer, and an insulating layer covering the electronic components is formed. Since the connection hole is formed in the insulating layer, the connection hole for the electrode of the electronic component can be formed under the same processing conditions. Therefore, the same effect as the above-described mounting structure of the present invention can be obtained, and a highly reproducible manufacturing method is provided. it can.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described.
[0021]
In the mounting structure and the manufacturing method of the present invention described above, the lowermost layer wiring on the mounting base is provided on the surface of the underlayer whose thickness is controlled, whereby the position of the wiring can be increased. Therefore, a connection hole having a low aspect ratio can be formed, and the reliability is improved by wiring without connection failure.
[0022]
In this case, a base insulating layer having a film thickness corresponding to the difference in thickness between the plurality of electronic components is formed, and the electronic component having a smaller thickness is fixed on the insulating layer, whereby the electronic component having a smaller thickness is formed. This is desirable in that it is easy to make the height of the electrode of the electronic component thicker than that of the electrode.
[0023]
However, the wiring of the lowermost layer may be provided directly on the mounting base, and the wiring of the lowermost layer may be led out onto the underlying layer through a connection hole formed in the underlying layer.
[0024]
Further, it is preferable that the lower insulating layer is removed and a recess is formed below the thicker electronic component of the plurality of electronic components, and the thick electronic component is fixed in the recess. This is desirable because the position accuracy of the electronic component can be enhanced and the height of the electronic component with a small thickness can be easily controlled.
[0025]
This is desirable in that the plurality of electronic components are electrically connected well via the connection holes formed in the insulating layer, and the reliability of wiring is enhanced.
[0026]
In this case, one of the plurality of electronic components is a light emitting element, the other is a semiconductor chip for driving the light emitting element, and further, the light emitting element is mounted in a resin-sealed chip state to form an image display device. be able to.
[0027]
Next, the preferred embodiments described above will be specifically described with reference to the drawings.
[0028]
Embodiment 1
1A and 1B show a device 25 having a mounting structure according to the present embodiment, in which FIG. 1A is a schematic sectional view, and FIG. 1B is an enlarged sectional view of a part thereof.
[0029]
This device 25 is equipped with the same type of LED 5 as that of FIG. 12 described above. However, the feature different from the conventional one is that the electrode 11b of the resin chip 5 as one electronic component and the electrode 11b as the other electronic component. Since the heights of the electrodes 9 of the IC chip 6 are the same, the connection holes 13 and 14 for these electrodes are the same, that the IC chip 6 is directly mounted on the substrate 1, This means that the connection hole 15a for the lower wiring 8a is formed shallowly and has a low aspect ratio.
[0030]
In this mounting structure, as shown in FIG. 1A, a part of the insulating layers 2 and 3 laminated on the substrate 1 is selectively removed, and an IC chip 6 is attached to this part via a die bonding material 7. The resin chip 5 is directly fixed on the substrate 1, and the resin chip 5 is fixed on the laminated insulating layer 3 via a die bonding material 7. As a result, the electrodes 11b of the resin chip 5 and the electrodes 9 of the IC chip 6 are formed at the same height, but this height depends on the thickness of the IC chip 6 (about 70 to 80 μm) and the thickness of the resin chip 5. It is formed by controlling the thickness of the insulating layer 2 in accordance with the difference in thickness (about 40 to 60 μm).
[0031]
That is, as described above, in the conventional device shown in FIG. 11 or FIG. 12, the thickness of the first insulating layer 32: about 5 μm, the thickness of the second insulating layer 33: about 5 μm, Since the height of A including the layer 32 or 33 is about 50 to 70 μm and the height of B is about 80 to 90 μm, subtracting the total thickness of both insulating layers of 10 μm, The thickness of the IC chip 36 is 70 to 80 μm, and the thickness of the resin chip 35a (or 35b) of the height A is 40 to 60 μm.
[0032]
Therefore, the actual difference (AB) between B and A in FIG. 11 or FIG. 12 is 10 to 40 μm, and thus the thickness (t) of the first insulating layer 2 in this embodiment is 10 to 40 μm. The resin chip 5 and the electrode of the IC chip 6 are formed at the same height.
[0033]
That is, as shown in FIG. 1B, the thickness t of the first insulating layer 2, the thickness x of the IC chip 6, and the thickness y of the resin chip 5 have a relationship of t = xy. ing. The resin chip 5 has an overall thickness y with an encapsulating resin thickness z on the upper part in order to seal the LED 10 and its electrodes and the like. Therefore, the height z of the electrode 9 of the IC chip 6 and the height of the electrode 11b of the resin chip 5 can be made equal by adjusting the thickness z of the second insulating layer 3 to the thickness of the sealing resin.
[0034]
Then, as shown in FIG. 1A, the lowermost wiring 8a is disposed on the first insulating layer 2, and the second lower wiring 8b is disposed on the second insulating layer 3. This enables cross wiring. As described above, since the resin chip 5 is disposed on the insulating layer 3 above the two-layer structure indispensable for cross wiring, the thickness (z) of the second insulating layer 3 is determined by the thickness of the sealing resin of the resin chip 5. By forming the same thickness as the thickness (z), a relationship of t = xy is formed, and the height of the electrode 11b of the resin chip 5 and the height of the electrode 9 of the IC chip 6 are the same.
[0035]
Further, since the lowermost wiring 8a is disposed on the insulating layer 2 having a controlled thickness (thicker than the conventional one), the height h from the substrate 1 (see FIG. 1) is higher than that of the conventional one. Therefore, the depth of the connection hole 15a is reduced and the aspect ratio is formed low.
[0036]
Therefore, as shown in FIG. 1A, since the connection holes 13 and 14 for the electrodes 9 and 11b of the IC chip 6 and the resin chip 5 are formed in the same manner, the electrodes 9 and 11b of the IC chip 6 and the resin chip 5 are formed. The number of types of connection holes for the semiconductor device can be reduced, the manufacturing process can be simplified, and the connection holes 15a having a low aspect ratio can be formed for the lower wiring 8a.
[0037]
2 to 4 show schematic cross-sectional views of a manufacturing process of the above device.
[0038]
First, a first insulating layer 2 is formed on a substrate 1 shown in FIG. 2 (a) as shown in FIG. 2 (b). The lower wiring 8a is provided. At this time, the thickness difference t between the IC chip 6 to be mounted and the resin chip 5 is measured in advance, and the insulating layer 2 is formed to have a thickness corresponding to the difference.
[0039]
Next, as shown in FIG. 2C, a second insulating layer 3 is laminated. As described above, this film thickness is formed to be the same as the thickness (z in FIG. 1) of the sealing resin of the resin chip 5 fixed thereon.
[0040]
Next, as shown in FIG. 2D, the next lower wiring 8b made of Al is arranged on the second insulating layer 3 near the end opposite to the lowermost wiring 8a. Although the lower wiring of this embodiment has two layers, in the case of a multilayer wiring layer, an insulating layer is further laminated on the second wiring 8b to further form a wiring layer.
[0041]
Next, as shown in FIG. 2E, in order to mount the IC chip 6, a removed portion 18 of the insulating layers 2, 3 is formed. Therefore, the wiring is designed so as not to pass through the removed portion. This makes it easy to make the height of the IC chip 6 and the height of the resin chip 5 the same, and the positional deviation is absorbed, so that the mounting accuracy of the IC chip 6 can be improved.
[0042]
Next, as shown in FIG. 3 (f), the IC chip 6 is fixed to the above-mentioned removed portion 18 via the die bonding material 7, and the resin chip 5 is attached to the insulating layer 3 on the insulating layer 3 adjacent thereto. Fixed through.
[0043]
Next, as shown in FIG. 3G, the insulating layer 4 is formed so as to cover the upper part of the insulating layer 3 including the mounted IC chip 6 and the resin chip 5.
[0044]
Then, as shown in FIG. 3 (h), the connection holes 15a, 15b, 13 for connecting the lower wirings 8a, 8b, the electrode 9 of the IC chip 6 and the electrode 11b of the resin chip 5 to these electrodes are formed. And 14 are formed by irradiation with a laser beam 19.
[0045]
The electrodes 9 of the IC chip 6 and the electrodes 11b of the resin chip 5 are also formed of aluminum similarly to the lower wirings 8a and 8b. Therefore, it is easy to process the connection hole by using a high-output short-wavelength laser.
[0046]
As shown in FIG. 3H, the processing of the connection hole by the laser beam 19 selects a mask 20 for each depth of the connection hole, narrows the focus by the lens 21, and further performs a laser for a deep connection hole or a shallow laser. By using a laser for a connection hole and performing ablation while changing the number of shots of the laser beam 19, connection holes of various depths can be arbitrarily formed, and the diameter and the taper of the connection hole are formed with this processing. .
[0047]
In particular, the connection holes 13 and 14 for the electrodes of the IC chip 6 and the resin chip 5 can be collectively processed under the same conditions. In addition, the connection holes 15a and 15b for the lower layer wirings 8a and 8b have a large bottom area and a large taper angle, so that disconnection of the wiring at the entrance of the connection hole hardly occurs.
[0048]
Next, as shown in FIG. 4I, a Cu (copper) film 16A is deposited on the upper surface of the insulating layer 4 including the connection holes 15a, 15b, 13 and 14 by a physical film forming method such as sputtering. At this time, by preliminarily applying electroless Ni plating (not shown) having good connectivity to Al and Cu such as electrodes, the lower wirings 8a and 8b made of Al, the electrodes 9 of the IC chip 6, and the The connectivity and conductivity between the electrode 11b and the like and the Cu film 16A can be improved.
[0049]
Next, as shown in FIG. 4J, the Cu film 16A thus deposited is patterned by photolithography to form a Cu wiring 16. Then, after the formation of the wiring 16, a protective layer (not shown) is formed on the wiring 16, thereby completing the panel of the image display device.
[0050]
According to the present embodiment, the thickness of the first insulating layer 2 disposed on the substrate 1 is controlled in accordance with the difference in thickness between the resin chip 5 and the IC chip 6 to be mounted. The insulating layer 3 is laminated with the same thickness (z) as the sealing resin of the resin chip 5, the resin chip 5 is mounted on the insulating layer 3, and the IC chip 6 is Is selectively removed and mounted directly on the substrate 1, so that the electrodes 9 of the IC chip 6 and the electrodes 11b of the resin chip 5 can be arranged at the same height on the substrate 1.
[0051]
Therefore, the connection holes 13 and 14 for the electrode 9 of the IC chip 6 and the electrode 11b of the resin chip 5 can be formed at the same depth under the same processing conditions by batch processing, and the manufacturing process can be simplified. In addition, since the lowermost wiring 8a is arranged on the first insulating layer 2 which is formed thicker by control, the connection hole 15a can be formed shallower and lower in aspect ratio than the conventional one. As a result, similar to the connection holes 13 and 14 with the electrodes 9 and 11b of the IC chip 6 and the resin chip 5, the connection holes 15 and the like with the wiring 8a in the lowermost layer can be formed with good wiring without poor connection. Can be enhanced.
[0052]
As described above, the present embodiment has the configuration and features not intended by the prior invention described above, and any of the prior inventions applies the configuration to the present embodiment. Is impossible, and the object of the present embodiment cannot be realized even if it is forcibly applied.
[0053]
Embodiment 2
5A and 5B show a device 26 having a mounting structure according to the present embodiment, in which FIG. 5A is a schematic sectional view, and FIG. 5B is an enlarged sectional view of a part thereof.
[0054]
This device 26 also has a basic structure substantially similar to that of the first embodiment, except that a thin resin chip 5A (electrodes 11a and 11b are exposed outside the sealing resin) is mounted. Are different.
[0055]
That is, the resin chip 5A is also fixed on the second insulating layer 3 via the adhesive 17, and has the same structure as that of the first embodiment except for this. Therefore, compared to the resin chip 5 of the first embodiment, since the resin for sealing is not used, the thickness is reduced by the amount corresponding to this resin. By controlling the thicknesses of the insulating layers 2 and 3 so as to match the difference between the two, the height of the electrode 9 of the IC chip 6 and the height of the electrode 11b of the resin chip 5A are the same.
[0056]
That is, as shown in FIG. 5B, the thickness t of the insulating layer in this case is the total thickness of the first insulating layer 2 and the second insulating layer 3, and the thickness of the resin chip 5A is The thickness y ′ is a thickness including the adhesive 17, and the relationship with the thickness x of the IC chip 6 as in the first embodiment is t = xy ′.
[0057]
Accordingly, if the lowermost wiring 8a is formed in the same manner as in the first embodiment, the thickness of the first insulating layer 2 does not change, so that the total thickness of the second insulating layer 3 is controlled. Is formed.
[0058]
As a result, the electrodes 9 of the IC chip 6 and the electrodes 11b of the resin chip 5A can be formed at the same height on the substrate 1, so that the connection holes 13, 14 for the electrodes 9, 11b of both chips are formed. It is possible to form the same under the same processing conditions, and to obtain the same effect as in the first embodiment.
[0059]
Embodiment 3
6A and 6B show a device 27 having a mounting structure according to the present embodiment, wherein FIG. 6A is a schematic sectional view and FIG. 6B is an enlarged sectional view of a part thereof.
[0060]
The basic structure of this device is almost the same as that of the first embodiment, except that the thickness of the IC chip 6A is smaller than that of the first embodiment.
[0061]
That is, various semiconductor chips tend to be thinner, and the mounting structure uses the thinned IC chip 6A. Accordingly, as shown in FIG. 6, only the second insulating layer 3 is removed from the mounting portion of the IC chip 6A, and the IC chip 6A is fixed on the first insulating layer 2. Otherwise, the configuration is the same as that of the first embodiment.
[0062]
Therefore, as shown in FIG. 6B, the thicknesses of the insulating layers 2 and 3 and the thickness of the resin chip 5 are the same as those of the first embodiment, and only the thickness of the IC chip 6A is different. x ′) has a relationship with the thickness (z ′) of the insulating layer 3, and z ′ = x′−y + z.
[0063]
Thus, also in this case, the height of the electrode 9 of the IC chip 6A and the height of the electrode 11b of the resin chip 5 are controlled by controlling the thickness of the insulating layer 3 in accordance with the difference in thickness between the IC chip 6A and the resin chip 5. Are formed identically.
[0064]
In this embodiment, as shown in FIG. 6, the IC chip 6A is mounted on the first insulating layer 2, but the removal of the insulating layer differs depending on the thickness of the IC chip 6A. That is, various forms are conceivable, such as a case where it is necessary to remove a part of the insulating layer 2 or a case where it is sufficient to remove only a part of the insulating layer 3. In any case, an IC chip corresponding to the state is assumed. The thickness of the insulating layer is controlled based on the difference between the thickness of 6A and the thickness of the resin chip 5.
[0065]
As a result, the height of the electrode 9 of the IC chip 6A and the height of the electrode 11b of the resin chip 5 can be made the same, so that the connection holes 13 and 14 for the electrodes 9 and 11b of the two chips are formed identically under the same processing conditions. Therefore, the same effect as in the first embodiment can be obtained.
[0066]
FIG. 7 shows a modification of the first embodiment.
[0067]
This device 28 is different from the first embodiment in that the lowermost wiring 8a is formed directly on the substrate 1, a plug 23 is provided on this wiring 8a, and a connection hole is formed for the second layer wiring 8b. 15b.
[0068]
Therefore, since the structure other than the above is the same as that of the first embodiment, the connection holes 13 and 14 for the electrode 9 of the IC chip 6 and the electrode 11b of the resin chip 5 can be formed identically under the same processing conditions. Since the connection holes 15b for the lower wirings 8a and 8b can be formed with the same processing conditions and the same aspect ratio, there is an advantage that the types of connection holes can be further reduced.
[0069]
FIGS. 8 to 10 show schematic cross-sectional views of this manufacturing process. Since this manufacturing process has many similarities to the manufacturing process of the first embodiment (FIGS. 2 to 4), different points will be mainly described.
[0070]
That is, as shown in FIG. 8A, the lowermost wiring 8a is first formed on the substrate 1, and the insulating layers 2 and 3 are stacked thereon (FIG. 8B).
[0071]
Next, as shown in FIG. 8C, a connection hole 24 for the wiring 8a is laser-processed, and a plug 23 is provided in the connection hole 24 at a height exceeding the second insulating layer 3. This height is formed to be the same as the height of the second-layer lower wiring 8b formed on the insulating layer 3 on the opposite end side (FIG. 8D).
[0072]
Next, as shown in FIG. 8E, the insulating layers 2 and 3 for mounting the IC chip 6 are selectively removed. Subsequently, the IC chip 6 is fixed to the removed portion 18 and the insulating layer is removed. The resin chip 5 is fixed on the top 3 (FIG. 9F).
[0073]
Next, the processes shown in FIGS. 9G to 10J are performed in the same manner as the processes in the first embodiment (see FIGS. 3G to 4J).
[0074]
Each of the embodiments described above can be further modified based on the technical idea of the present invention.
[0075]
For example, the method of controlling the thickness of the insulating layer in accordance with the difference in thickness between the IC chip 6 (6A) and the resin chip 5 (5A) may be arbitrary as long as the same effect as in the embodiment can be obtained. Alternatively, control may be performed by a control method other than the embodiment.
[0076]
Further, in the embodiment, in order to mount the IC chip 6 which is generally thicker than the resin chip 5, the removing portions 18 are provided in the insulating layers 2 and 3. However, the resin chip 5 is larger than the IC chip 6. When the thickness is thick, the removal portion 18 may be formed on the resin chip 5 side.
[0077]
In the case where the lower wiring is further multilayered, an insulating layer is further laminated for each wiring, and the control of the thickness of the insulating layer in order to make the heights of the electrodes of the IC chip and the resin chip the same is also immediate. And can be made appropriately.
[0078]
Although the embodiment relates to the mounting of the IC chip 6 (6A) and the resin chip 5 (5A), the embodiment is applied to the mounting of any other element including the element having the structure shown in FIG. be able to.
[0079]
Further, the material, structure, shape, and the like of each part in the embodiment can be appropriately set.
[0080]
Operation and Effect of the Invention
As described above, according to the electronic component mounting structure and the method of manufacturing the same of the present invention, since the thickness of the base layer provided on the base is controlled, the positions of the electrodes of each electronic component can be formed at the same height. In the insulating layer covering the electronic component, the connection holes for the electrodes of each electronic component can be collectively processed under the same processing conditions. As a result, it is possible to form a favorable wiring without a connection failure, to improve reliability, to reduce the types of connection holes, and to provide a mounting structure of an electronic component with a simplified manufacturing process.
[Brief description of the drawings]
1A and 1B show a mounting structure according to a first embodiment of the present invention, wherein FIG. 1A is a schematic cross-sectional view, and FIG. 1B is a partially enlarged cross-sectional view.
FIG. 2 is a schematic cross-sectional view showing a manufacturing process of the mounting structure.
FIG. 3 is a schematic sectional view showing another manufacturing process of the mounting structure.
FIG. 4 is a schematic sectional view showing still another manufacturing process of the mounting structure.
5A and 5B show a mounting structure of an electronic component according to the second embodiment, wherein FIG. 5A is a schematic cross-sectional view and FIG. 5B is a partially enlarged cross-sectional view.
6A and 6B show a mounting structure of an electronic component according to the third embodiment, wherein FIG. 6A is a schematic cross-sectional view and FIG. 6B is an enlarged cross-sectional view of a part.
FIG. 7 is a schematic sectional view of a mounting structure according to a modification of the first embodiment.
FIG. 8 is a schematic sectional view showing a manufacturing process of the mounting structure.
FIG. 9 is a schematic sectional view showing another manufacturing process of the mounting structure.
FIG. 10 is a schematic sectional view showing still another manufacturing process of the mounting structure.
FIG. 11 is a schematic sectional view showing an example of a mounting structure of an electronic component according to a conventional example.
FIG. 12 is a schematic sectional view showing another example of a mounting structure of an electronic component according to a conventional example.
[Explanation of symbols]
1 ... substrate, 2,3,4 ... insulating layer, 5,5A ... resin chip,
6, 6A: IC chip, 7: Die bonding material, 8a, 8b: Lower wiring,
9 ... electrode, 10 ... light emitting diode, 11a ... p electrode, 11b ... n electrode,
13, 14, 15a, 15b, 24 ... connection hole, 16 ... wiring, 16A ... copper,
17 adhesive, 18 removal part, 19 laser beam, 20 mask,
21 ... lens, 23 ... plug, 25, 26, 27, 28 ... device,
h: height of the lowermost wiring from the substrate; t: thickness of the first insulating layer;
x, x ', B: thickness of IC chip, y, y'A: thickness of resin chip,
z: The thickness of the second insulating layer (or the thickness of the upper part of the resin chip)

Claims (18)

実装基体上に複数の電子部品が固定され、これらの電子部品を被覆する絶縁層に形成された接続孔を介して各電子部品の電極が取り出されている電子部品の実装構造において、
前記実装基体上に設けられた下地層の厚みの制御によって、前記複数の電子部品の各電極に対する前記接続孔の深さがほぼ同一となっている、電子部品の実装構造。In a mounting structure of an electronic component in which a plurality of electronic components are fixed on a mounting base, and electrodes of each electronic component are taken out through connection holes formed in an insulating layer covering these electronic components,
An electronic component mounting structure, wherein a depth of the connection hole for each electrode of the plurality of electronic components is substantially the same by controlling a thickness of a base layer provided on the mounting substrate. 厚みの制御された前記下地層の面に、前記実装基体上の最下層の配線が設けられている、請求項１に記載した電子部品の実装構造。2. The electronic component mounting structure according to claim 1, wherein a wiring of a lowermost layer on the mounting substrate is provided on a surface of the underlayer whose thickness is controlled. 3. 前記複数の電子部品の厚みの差に対応する膜厚の下地絶縁層が、厚みの小さい方の電子部品の下地層として設けられている、請求項１に記載した電子部品の実装構造。2. The electronic component mounting structure according to claim 1, wherein a base insulating layer having a thickness corresponding to a difference in thickness between the plurality of electronic components is provided as a base layer of the smaller electronic component. 3. 前記複数の電子部品のうち厚みの大きい方の電子部品の下部において、前記下地絶縁層が除去されて凹部が形成され、この凹部内に前記厚みの大きい電子部品が固定されている、請求項３に記載した電子部品の実装構造。4. The lower part of the electronic component having a larger thickness of the plurality of electronic components, the base insulating layer is removed to form a recess, and the electronic component having a larger thickness is fixed in the recess. The mounting structure of the electronic component described in. 前記最下層の配線が前記実装基体に直接設けられ、前記下地層に形成された接続孔を介して、前記下地層上に前記最下層の配線が導出されている、請求項２に記載した電子部品の実装構造。The electronic device according to claim 2, wherein the lowermost wiring is provided directly on the mounting base, and the lowermost wiring is led out onto the base layer through a connection hole formed in the base layer. 4. Component mounting structure. 前記複数の電子部品間が、前記絶縁層に形成された前記接続孔を介して電気的に接続されている、請求項１に記載した電子部品の実装構造。The electronic component mounting structure according to claim 1, wherein the plurality of electronic components are electrically connected to each other through the connection holes formed in the insulating layer. 前記複数の電子部品の一方が発光素子であり、他方が発光素子駆動用の半導体チップである、請求項６に記載した電子部品の実装構造。The electronic component mounting structure according to claim 6, wherein one of the plurality of electronic components is a light emitting element, and the other is a semiconductor chip for driving the light emitting element. 前記発光素子が樹脂封止されたチップ状態で実装されている、請求項７に記載した電子部品の実装構造。The electronic component mounting structure according to claim 7, wherein the light emitting element is mounted in a resin-sealed chip state. 画像表示装置を構成する、請求項７に記載した電子部品の実装構造。The electronic component mounting structure according to claim 7, which constitutes an image display device. 実装基体上に複数の電子部品が固定され、これらの電子部品を被覆する絶縁層に形成された接続孔を介して各電子部品の電極が取り出されている電子部品の実装構造を製造する方法において、
前記実装基体上に制御された厚みに下地層を形成する工程と、
前記下地層上に前記複数の電子部品を固定する工程と、
前記絶縁層を形成する工程と、
この絶縁層に前記接続孔を形成する工程と
を有する、電子部品の実装構造を製造する方法。In a method of manufacturing a mounting structure of an electronic component, a plurality of electronic components are fixed on a mounting base, and electrodes of each electronic component are taken out through connection holes formed in an insulating layer covering these electronic components. ,
Forming an underlayer to a controlled thickness on the mounting substrate,
Fixing the plurality of electronic components on the underlayer;
Forming the insulating layer;
Forming the connection hole in the insulating layer. 厚みの制御された前記下地層の面に、前記実装基体上の最下層の配線を設ける、請求項１０に記載した電子部品の実装構造を製造する方法。The method for manufacturing a mounting structure of an electronic component according to claim 10, further comprising: providing a lowermost layer wiring on the mounting substrate on a surface of the underlayer whose thickness is controlled. 前記複数の電子部品の厚みの差に対応する膜厚の下地絶縁層を形成し、この絶縁層上に厚みの小さい方の電子部品を固定する、請求項１０に記載した電子部品の実装構造を製造する方法。The electronic component mounting structure according to claim 10, wherein a base insulating layer having a thickness corresponding to a difference in thickness between the plurality of electronic components is formed, and the electronic component having a smaller thickness is fixed on the insulating layer. How to make. 前記複数の電子部品のうち厚みの大きい方の電子部品の下部において、前記下地絶縁層を除去して凹部を形成し、この凹部内に前記厚みの大きい電子部品を固定する、請求項１２に記載した電子部品の実装構造を製造する方法。13. The electronic component according to claim 12, wherein the lower insulating layer is removed to form a concave portion below the electronic component having a larger thickness among the plurality of electronic components, and the electronic component having a larger thickness is fixed in the concave portion. For manufacturing a mounting structure of a manufactured electronic component. 前記最下層の配線を前記実装基体に直接設け、前記下地層に形成された接続孔を介して、前記下地層上に前記最下層の配線を導出する、請求項１１に記載した電子部品の実装構造を製造する方法。12. The mounting of the electronic component according to claim 11, wherein the lowermost layer wiring is provided directly on the mounting substrate, and the lowermost layer wiring is led out onto the base layer through a connection hole formed in the base layer. The method of manufacturing the structure. 前記複数の電子部品間を、前記絶縁層に形成された前記接続孔を介して電気的に接続する、請求項１０に記載した電子部品の実装構造を製造する方法。The method according to claim 10, wherein the plurality of electronic components are electrically connected to each other through the connection holes formed in the insulating layer. 前記複数の電子部品の一方を発光素子とし、他方を発光素子駆動用の半導体チップとする、請求項１５に記載した電子部品の実装構造を製造する方法。The method according to claim 15, wherein one of the plurality of electronic components is a light emitting element, and the other is a semiconductor chip for driving the light emitting element. 前記発光素子を樹脂封止されたチップ状態で実装する、請求項１６に記載した電子部品の実装構造を製造する方法。The method according to claim 16, wherein the light emitting element is mounted in a resin-sealed chip state. 画像表示装置を製造する、請求項１６に記載した電子部品の実装構造を製造する方法。The method for manufacturing an electronic component mounting structure according to claim 16, wherein the image display device is manufactured.
JP2002201295A 2002-07-10 2002-07-10 Mounting structure of electronic component and manufacturing method thereof Pending JP2004047617A (en)

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JP2010541227A (en) * 2007-09-28 2010-12-24 シーメンス アクチエンゲゼルシヤフト Electronic circuit comprising partial circuit and method for manufacturing the same
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US8441114B2 (en) 2007-09-28 2013-05-14 Siemens Aktiengesellschaft Electronic circuit composed of sub-circuits and method for producing
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