TW202410493A - Semiconductor sealing package structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor sealing package structure includes a substrate, at least one semiconductor element, an adhesive material, a cover plate and a metal layer. A groove is formed on an outer side of a surrounding portion of the substrate which is relatively far away from a carrier portion. The semiconductor element is electrically connected to the carrier portion of the substrate. The adhesive material is disposed in the groove. The cover plate is disposed on the outer side of the surrounding portion and covers the semiconductor element. The metal layer is disposed on the cover plate and covers the adhesive material. The substrate, the adhesive material, the metal layer and the cover plate seal the semiconductor element.

Description

Semiconductor sealed packaging structure and manufacturing method thereof

The present invention relates to a packaging structure and a manufacturing method thereof, and in particular, to a semiconductor sealing packaging structure and a manufacturing method thereof.

Generally speaking, the shorter the wavelength of ultraviolet light emitted by the LED, the more damaging it is to organic materials. Therefore, it is particularly important to choose the right material for packaging. According to the type of packaging material, the deep ultraviolet (DUV) packaging structure can be divided into semi-inorganic packaging and inorganic packaging for sealing. However, the inorganic packaging process is complicated and costly, such as material liquefaction pressure control and coplanarity affecting the flow uniformity of adhesive materials; semi-inorganic packaging cannot prevent the reflection and refraction of deep ultraviolet light on organic materials, causing material aging and cracking, and damage to the seal leading to cavity leakage.

The present invention provides a semiconductor sealing package structure having better structural reliability.

The present invention also provides a method for manufacturing a semiconductor sealing package structure, which is used to produce the above-mentioned semiconductor sealing package structure, which has the advantages of simple manufacturing process and reduced process complexity.

The semiconductor sealed packaging structure of the present invention includes a substrate, at least one semiconductor element, an adhesive material, a cover plate and a metal layer. The substrate includes a supporting portion and a surrounding portion. The surrounding portion is arranged on the supporting portion and defines a receiving groove with the supporting portion. The surrounding portion has a groove on an outer side relatively far from the supporting portion. The semiconductor element is arranged in the receiving groove and is electrically connected to the supporting portion of the substrate. The adhesive material is arranged in the groove. The cover plate is arranged on the outer side of the surrounding portion and covers the semiconductor element. The metal layer is arranged on the cover plate and covers the adhesive material. The substrate, the adhesive material, the metal layer and the cover plate seal the semiconductor element.

In an embodiment of the present invention, the groove has a first side and a second side opposite to each other. The height of the first side is equal to or greater than the height of the second side.

In an embodiment of the present invention, the above-mentioned cover plate is a flat plate.

In an embodiment of the present invention, the above-mentioned cover plate includes a flat plate part and a lens part. The lens portion is disposed on a side of the flat plate portion relatively away from the metal layer and is disposed corresponding to the semiconductor element.

In an embodiment of the present invention, the above-mentioned at least one semiconductor device includes at least one light-emitting diode and a Zener diode.

In an embodiment of the present invention, the light emitting wavelength of the above-mentioned light-emitting diode is between 200 nanometers and 400 nanometers.

In one embodiment of the present invention, the light transmittance of the cover plate for light with a wavelength of 200 nm to 280 nm is greater than 85%.

In an embodiment of the present invention, the material of the cover plate includes quartz or sapphire.

In one embodiment of the present invention, the metal layer is a multi-layer metal film.

In one embodiment of the present invention, the material of the substrate includes ceramic material or metal material.

The method for manufacturing a semiconductor sealed packaging structure of the present invention includes the following steps. A substrate is provided. The base plate includes a carrying part and a surrounding part. The surrounding portion is disposed on the bearing portion and defines a receiving groove with the bearing portion. An outer side of the surrounding portion relatively away from the bearing portion has a groove. At least one semiconductor element is arranged in the accommodating groove, wherein the semiconductor element is electrically connected to the carrying portion of the substrate. Fill the groove with an adhesive material. A cover plate with a metal layer formed thereon is pressed onto the substrate. The cover plate is disposed on the outside of the surrounding portion and covers the semiconductor element. The metal layer covers the adhesive material. The substrate, adhesive material, metal layer and cover seal the semiconductor device.

In one embodiment of the present invention, the supporting portion of the substrate comprises a ceramic substrate having a working circuit, and the surrounding portion of the substrate is formed on the supporting portion by ceramic sintering or copper electroplating.

In one embodiment of the present invention, the surrounding portion is formed on the supporting portion by metal bonding or copper plating.

In an embodiment of the present invention, the groove has a first side and a second side opposite to each other. The height of the first side is equal to or greater than the height of the second side.

In one embodiment of the present invention, the cover plate is a flat plate.

In an embodiment of the present invention, the above-mentioned cover plate includes a flat plate part and a lens part. The lens portion is disposed on a side of the flat plate portion relatively away from the metal layer and is disposed corresponding to the semiconductor element.

In one embodiment of the present invention, the semiconductor device includes at least one light emitting diode and one Zener diode.

In one embodiment of the present invention, the light emitting wavelength of the light emitting diode is between 200 nanometers and 400 nanometers.

In one embodiment of the present invention, the light transmittance of the cover plate for light with a wavelength of 200 nm to 280 nm is greater than 85%.

In one embodiment of the present invention, the material of the cover plate includes quartz or sapphire.

Based on the above, in the design of the semiconductor sealing package structure of the present invention, the metal layer disposed on the cover plate covers the adhesive material disposed in the groove, thereby effectively preventing or avoiding the adhesive material from being irradiated by, for example, deep ultraviolet light and causing aging and cracking, and maintaining the viscosity of the adhesive material, so as to effectively improve the structural reliability of the semiconductor sealing package structure of the present invention. In addition, the groove design on the surrounding portion of the substrate can not only accommodate the adhesive material and locate the position of the adhesive material, but also effectively control the amount of the adhesive material, which can improve the process reliability.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

1A to 1C are schematic cross-sectional views of a method for manufacturing a semiconductor sealing package structure according to an embodiment of the present invention. FIG. 1D is a schematic bottom view of the cover plate in FIG. 1C.

Please refer to FIG. 1A for the method of manufacturing the semiconductor sealed package structure of the present embodiment. First, a substrate 110a is provided. The substrate 110a includes a supporting portion 112a and a surrounding portion 114a. The surrounding portion 114a is disposed on the supporting portion 112a and defines a receiving groove C with the supporting portion 112a. In particular, the surrounding portion 114a has a groove 115a on an outer side S that is relatively far away from the supporting portion 112a. In a top view, the groove 115a is, for example, in the shape of a rectangular ring with rounded corners, but is not limited thereto.

Specifically, the carrying portion 112a of the substrate 110a is, for example, a ceramic substrate with a working circuit, that is, the material of the carrying portion 112a can be a ceramic material. The surrounding portion 114a of the substrate 110a is formed around the carrying portion 112a by, for example, ceramic sintering or copper electroplating. That is, the material of the surrounding portion 114a can be a ceramic material or a metal material. That is to say, the carrying portion 112a and the surrounding portion 114a of the substrate 110a are not integrally formed, and can be made of the same or different materials. In one embodiment, the surrounding portion 114a can also be formed on the carrying portion 112a by metal adhesion or copper plating. In this embodiment, the periphery of the carrying portion 112a can be aligned with the periphery of the surrounding portion 114a, but is not limited to this.

In one embodiment, the size and circuit of the supporting part 112a can be made on a ceramic substrate according to the required size, wherein the number of the ceramic substrate-type supporting parts 112a can be multiple and arranged in a matrix, for example. Then, the surrounding part 114a can be made on each supporting part 112a by ceramic sintering or electroplating, and the groove 115a is formed on the upper edge of the surrounding part 114a by etching. Here, the groove 115a has a first side E1 and a second side E2 opposite to each other, wherein the height of the first side E1 can be, for example, equal to the height of the second side E2, but is not limited thereto.

Next, please refer to FIG. 1A again, a metal layer 120 can be selectively formed on the outer side S of the surrounding portion 114a and extends to cover the inner wall of the groove 115a. Here, the method of forming the metal layer 120 is, for example, electroplating, but is not limited thereto. Here, the metal layer 120 is configured to be conformal to the groove 115a and the outer side S of the surrounding portion 114a, for example. In one embodiment, the metal layer 120 is gold, for example, but is not limited thereto.

Next, please refer to FIG. 1B , and configure at least one semiconductor element (schematically showing two semiconductor elements 130 and 135) in the receiving groove C, wherein the semiconductor elements 130 and 135 are electrically connected to the supporting portion 112a of the substrate 110a, for example, through solders 132 and 137. Here, the semiconductor element 130 is, for example, a light-emitting diode (schematically showing a light-emitting diode), wherein the light-emitting wavelength of the light-emitting diode is, for example, between 200 nanometers and 400 nanometers. That is, the light-emitting diode is a light-emitting diode that can emit deep ultraviolet light. The semiconductor element 135 is, for example, a Zener diode, which is used to protect the light-emitting diode, but is not limited thereto. In one embodiment, the number of light-emitting diodes can be multiple according to the needs, which still falls within the scope of protection of the present invention.

Next, please refer to FIG. 1B again, and fill an adhesive material 140 into the groove 115a. When a metal layer 120 is provided in the groove 115a, the adhesive material 140 may be located on the metal layer 120. Here, the adhesive material 140 may be formed in the groove 115a by, for example, a glue-scribing method, wherein the adhesive material 140 may be, for example, an organic adhesive silicone, rubber or epoxy resin, or a metal inorganic material, but is not limited thereto. In one embodiment, the adhesive material 140 may contain flux or may not contain flux, but is not limited thereto. It should be noted that when the adhesive material 140 is an inorganic metal material, the metal layer 120 must be provided; and when the adhesive material 140 is an organic material, the metal layer 120 may be provided selectively. The provision of the groove 115 a can not only accommodate the adhesive material 140 to locate the position of the adhesive material 140 , but also effectively control the amount of the adhesive material 140 .

Afterwards, please refer to FIG. 1B and FIG. 1D simultaneously, and provide a cover plate 150a on the substrate 110a, wherein a metal layer 160 is formed on the lower surface 151 of the cover plate 150a. The metal layer 160 is, for example, a multi-layer metal film, and may include a first layer 162 and a second layer 164. The first layer 162 is directly formed on the cover plate 150a, and the second layer 164 is formed on the first layer 162. Here, the cover plate 150a is, for example, a flat plate, and may be made of a material with the best ultraviolet light transmission, such as quartz or sapphire, but not limited thereto. In particular, the light transmittance of the cover plate 150a for light with a wavelength of 200 nanometers to 280 nanometers (i.e., deep ultraviolet light) is greater than 85%. In another embodiment, other wavelengths can be enhanced or blocked by selecting or applying optical coating layers according to wavelength requirements and material properties.

In one embodiment, the metal-plated area of the cover plate 150a (i.e., the area where the metal layer 160 is located) can be designed to be a rectangular ring with rounded corners according to the size of the groove 115a to be matched with the substrate 110a. After the cover plate 150a is cleaned, a first layer 162 can be formed in the designed rectangular ring range by evaporating a material such as titanium, chromium or platinum to serve as an intermediate interface layer between the cover plate 150a and the second layer 164. Afterwards, the second layer 164 is formed on the first layer 162 by evaporating a material such as gold to serve as a contact surface with the adhesive material 140. Finally, the cover plate 150a is singulated and cut into the required size according to the required size, thereby completing the formation of the metal layer 160 on the cover plate 150a.

Finally, please refer to FIG. 1B and FIG. 1C at the same time. The cover plate 150 a on which the metal layer 160 has been formed is pressed onto the substrate 110 by thermal compression. The cover plate 150 a is disposed on the outer side S of the surrounding portion 114 a and covers it. Semiconductor elements 130,135. Here, the periphery of the cover 150a may be aligned with the periphery of the substrate 110a, but is not limited thereto. When the adhesive material 140 is an organic material and is provided with a metal layer 120, the metal layer 160 directly contacts the metal layer 120, so that the adhesive material 140 is coated between the metal layer 120 and the metal layer 160, thereby forming an inorganic material (ie, metal layer 120). layer 120 and metal layer 160) covering the organic material (ie, adhesive material 140). The substrate 110a, the adhesive material 140, the metal layer 160 and the cover 150a seal the semiconductor elements 130 and 135. That is to say, the semiconductor devices 130 and 135 are sealed in the cavity defined by the substrate 110a, the adhesive material 140, the metal layer 160 and the cover plate 150a.

In this embodiment, since the adhesive material 140 is filled in the groove 115a, when the cover plate 150a is pressed onto the substrate 110a by hot pressing, the adhesive material 140 can fill the groove 115a, and the groove 115a can limit the flow of the adhesive material 140 to effectively control the adhesive material 140. Furthermore, after the cover plate 150a is pressed, the adhesive material 140 can be hidden in the groove 115a and protected by the metal layer 160 on the cover plate 150a, or the metal layer 120 in the groove 115a, so that the adhesive material 140 is not irradiated by the deep ultraviolet light emitted by the semiconductor element 130. In this way, the adhesive material 140 can be effectively prevented or avoided from being aging and cracking due to being irradiated by the deep ultraviolet light, and the viscosity of the adhesive material 140 can be maintained. In addition, the metal layer 160 can also prevent the deep ultraviolet rays from refracting and penetrating the adhesive material 140 below, which can avoid or prevent the adhesive material 140 from aging and cracking to allow water vapor to penetrate the chamber, thereby affecting the light extraction rate of the semiconductor element 130. Afterwards, the adhesive material 140 can be cured by baking in an oven. Finally, if the supporting parts 112a on the ceramic substrate are arranged in a matrix, the ceramic substrate can be singulated and cut to complete the production of the semiconductor sealing package structure 100a.

Structurally, please refer to FIG. 1C again. The semiconductor sealed package structure 100a in this embodiment includes a substrate 110a, semiconductor elements 130, 135, an adhesive material 140, a cover plate 150a and a metal layer 160. The substrate 110a includes a supporting portion 112a and a surrounding portion 114a. The surrounding portion 114a is disposed on the supporting portion 112a and defines a receiving groove C with the supporting portion 112a. The surrounding portion 114a has a groove 115a on the outer side S away from the supporting portion 112a. Here, the groove 115a has a first side E1 and a second side E2 opposite to each other, wherein the height of the first side E1 is, for example, equal to the height of the second side E2, but is not limited thereto. The semiconductor components 130 and 135 are disposed in the receiving groove C and are electrically connected to the supporting portion 112a of the substrate 110a, for example, through solders 132 and 137. Here, the semiconductor component 130 is, for example, a light-emitting diode with a light-emitting wavelength between 200 nanometers and 400 nanometers, and the semiconductor component 135 is, for example, a Zener diode, but is not limited thereto. The adhesive material 140 is disposed in the groove 115a, wherein the adhesive material 140 may include an organic material or an inorganic metal material. When the adhesive material 140 is an inorganic metal material, the metal layer 120 must be provided; and when the adhesive material 140 is an organic material, the metal layer 120 may be provided selectively. The cover plate 150a is disposed on the outer side S of the surrounding portion 114a and covers the semiconductor elements 130 and 135. Here, the cover plate 150a is a flat plate, and the material of the cover plate 150a is, for example, quartz or sapphire, and the light transmittance of the cover plate 150a for light with a wavelength of 200 nanometers to 280 nanometers is, for example, greater than 85%. The metal layer 160 is disposed on the cover plate 150a and covers the adhesive material 140. Here, the metal layer 160 is, for example, a multi-layer metal film, and may include a first layer 162 and a second layer 164. The first layer 162 directly contacts the cover plate 150a, and the second layer 164 is disposed on the first layer 162. The substrate 110a, the adhesive material 140, the metal layer 160 and the cover plate 150a seal the semiconductor elements 130 and 135.

In short, the adhesive material 140 of this embodiment is disposed in the groove 115a, and the metal layer 160 on the cover 150a covers the adhesive material 140, thereby preventing or preventing the adhesive material 140 from being irradiated by deep ultraviolet light and generating organic materials. The cracking and aging can maintain the viscosity of the adhesive material 140, thereby effectively improving the structural reliability of the semiconductor sealing package structure 100a of this embodiment. Furthermore, the design of the groove 115a on the surrounding portion 114a of the substrate 110a can not only accommodate the adhesive material 140 to position the adhesive material 140, but also effectively control the amount of the adhesive material 140 without deliberately controlling the cover 150a. The pressing pressure is used to prevent the adhesive material 140 from overflowing or insufficient adhesion, thereby improving process reliability. In addition, when the adhesive material 140 is made of organic material, since it is a semi-inorganic package, compared with inorganic packaging, the process can be effectively simplified to reduce the complexity of the process.

It should be noted that the following embodiments use the component numbers and some contents of the previous embodiments, wherein the same number is used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the previous embodiments, and the following embodiments will not be repeated.

FIG. 2 is a schematic cross-sectional view of a semiconductor sealing package structure according to an embodiment of the present invention. Please refer to FIG. 1C and FIG. 2 at the same time. The semiconductor sealed package structure 100b of this embodiment is similar to the semiconductor sealed package structure 100a of FIG. 114b is formed integrally, for example. The material of the substrate 110b is, for example, ceramic material or metal material.

FIG3 is a cross-sectional schematic diagram of a semiconductor sealed package structure according to an embodiment of the present invention. Referring to FIG2 and FIG3 at the same time, the semiconductor sealed package structure 100c of this embodiment is similar to the semiconductor sealed package structure 100b of FIG2 , and the difference between the two is that in this embodiment, the edge 153 of the cover plate 150c is retracted by a distance D relative to the edge 113 of the substrate 110b. In other words, the length of the cover plate 150c of this embodiment is shorter than the length of the substrate 110b. At this time, the adhesive material 140 is still located in the groove 115a and covered by the metal layer 160 of the cover plate 150c, thereby preventing or avoiding the adhesive material 140 from being decomposed and aged by deep ultraviolet light, and maintaining the viscosity of the adhesive material 140 to effectively improve the structural reliability of the semiconductor sealing package structure 100c of this embodiment.

FIG. 4 is a schematic cross-sectional view of a semiconductor sealing package structure according to an embodiment of the present invention. Please refer to FIG. 3 and FIG. 4 at the same time. The semiconductor sealing package structure 100d of this embodiment is similar to the semiconductor sealing package structure 100c of FIG. side E1' and the second side E2, wherein the height of the first side E1' is greater than the height of the second side E2. That is to say, the height of the first side E1' of the groove 115d is different from the height of the second side E2. Here, the outer sides S1 and S2 of the surrounding portion 114a are stepped, with the outer side S1 being higher than the outer side S2. At this time, the adhesive material 140 is still located in the groove 115d and is covered by the metal layer 160 of the cover 150c, thereby preventing or avoiding the cracking and aging of the adhesive material 140 due to exposure to deep ultraviolet light, and maintaining the adhesion of the adhesive material 140. properties to effectively improve the structural reliability of the semiconductor sealing package structure 100d of this embodiment.

In an embodiment not shown, a small gap may be provided between the metal layer on the cover and the metal layer on the outer side of the surrounding portion to serve as an airflow channel to release the pressure in the groove. For example, a small gap may be provided between the edge 153 of the cover 150c of FIG. 4 and the metal layer 120 adjacent to the edge 153, and the position of the small gap is relatively far from the chamber in which the semiconductor element 130 is sealed.

FIG. 5 is a schematic cross-sectional view of a semiconductor sealing package structure according to an embodiment of the present invention. Please refer to FIG. 2 and FIG. 5 at the same time. The semiconductor sealed package structure 100e of this embodiment is similar to the semiconductor sealed package structure 100b of FIG. A lens portion 154. The lens portion 154 is disposed on the side of the flat plate portion 152 relatively away from the metal layer 160 and is provided corresponding to the semiconductor elements 130 and 135, so that the semiconductor sealing package structure 100e has a better light pattern.

In summary, in the design of the semiconductor sealed package structure of the present invention, the metal layer disposed on the cover plate covers the adhesive material disposed in the groove, thereby effectively preventing or avoiding the adhesive material from being irradiated by, for example, deep ultraviolet light and causing aging and cracking, and maintaining the viscosity of the adhesive material, so as to effectively improve the structural reliability of the semiconductor sealed package structure of the present invention. In addition, the groove design on the surrounding portion of the substrate can not only accommodate the adhesive material and locate the position of the adhesive material, but also effectively control the amount of the adhesive material, which can improve the process reliability.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

100a, 100b, 100c, 100d, 100e: semiconductor sealing package structure 110a, 110b: substrate 112a, 112b: carrier part 113, 153: edge 114a, 114b: surrounding part 115a, 115d: groove 120, 160: metal layer 130, 135: semiconductor element 132, 137: solder 140: adhesive material 150a, 150c, 150e: cover plate 151: lower surface 152: flat plate part 154: lens part 162: first layer 164: second layer C: receiving groove D: distance E1, E1’: first side E2: second side S, S1, S2: outer side

Figures 1A to 1C are cross-sectional schematic diagrams of a method for manufacturing a semiconductor sealed package structure according to an embodiment of the present invention. Figure 1D is a schematic diagram of a cover plate in Figure 1C viewed from above. Figure 2 is a cross-sectional schematic diagram of a semiconductor sealed package structure according to an embodiment of the present invention. Figure 3 is a cross-sectional schematic diagram of a semiconductor sealed package structure according to another embodiment of the present invention. Figure 4 is a cross-sectional schematic diagram of a semiconductor sealed package structure according to another embodiment of the present invention. Figure 5 is a cross-sectional schematic diagram of a semiconductor sealed package structure according to another embodiment of the present invention.

100a: Semiconductor sealed packaging structure

110a: Substrate

112a: Bearing part

114a: Surrounding part

115a: Groove

120, 160: Metal layer

130, 135: Semiconductor components

132, 137: Solder

140:Adhesive material

150a: Cover plate

151: Lower surface

162:First floor

164:Second floor

C: Storage tank

E1: First side

E2: Second side

S: Outside

Claims (20)

A semiconductor sealed packaging structure includes: A substrate including a supporting portion and a surrounding portion, wherein the surrounding portion is arranged on the supporting portion and defines a receiving groove with the supporting portion, wherein an outer side of the surrounding portion relatively far from the supporting portion has a groove; At least one semiconductor element is arranged in the receiving groove and electrically connected to the supporting portion of the substrate; An adhesive material is arranged in the groove; A cover plate is arranged on the outer side of the surrounding portion and covers the at least one semiconductor element; and A metal layer is arranged on the cover plate and covers the adhesive material, wherein the substrate, the adhesive material, the metal layer and the cover plate seal the at least one semiconductor element. The semiconductor sealing package structure of claim 1, wherein the groove has a first side and a second side opposite to each other, and the height of the first side is equal to or greater than the height of the second side. The semiconductor sealing package structure as claimed in claim 1, wherein the cover is a flat plate. A semiconductor sealed package structure as described in claim 1, wherein the cover plate includes a flat plate portion and a lens portion, the lens portion is disposed on a side of the flat plate portion that is relatively far away from the metal layer and is arranged corresponding to the at least one semiconductor element. The semiconductor sealed package structure of claim 1, wherein the at least one semiconductor element includes at least one light emitting diode and a Zener diode. A semiconductor sealed package structure as described in claim 5, wherein the light emitting wavelength of the at least one light emitting diode is between 200 nanometers and 400 nanometers. The semiconductor sealed packaging structure of claim 1, wherein the cover plate has a light transmittance greater than 85% for light with a wavelength of 200 nanometers to 280 nanometers. The semiconductor sealed packaging structure according to claim 1, wherein the cover plate is made of quartz or sapphire. The semiconductor sealing package structure of claim 1, wherein the metal layer is a multi-layer metal film. The semiconductor sealed packaging structure according to claim 1, wherein the substrate is made of ceramic material or metal material. A method for manufacturing a semiconductor sealed packaging structure, including: A base plate is provided. The base plate includes a bearing portion and a surrounding portion. The surrounding portion is disposed on the bearing portion and defines a receiving groove with the bearing portion. The surrounding portion has an outer side relatively away from the bearing portion. groove; disposing at least one semiconductor element in the accommodating groove, wherein the at least one semiconductor element is electrically connected to the carrying portion of the substrate; Filling the groove with an adhesive material; and A cover plate formed with a metal layer is pressed onto the substrate. The cover plate is disposed on the outside of the surrounding portion and covers the at least one semiconductor element. The metal layer covers the adhesive material, wherein the substrate, the adhesive material The material, the metal layer and the cover seal the at least one semiconductor component. A method for manufacturing a semiconductor sealed packaging structure as described in claim 11, wherein the supporting portion of the substrate includes a ceramic substrate having a working circuit, and the surrounding portion of the substrate is formed on the supporting portion by ceramic sintering or copper electroplating. The method for manufacturing a semiconductor sealing package structure as claimed in claim 11, wherein the surrounding portion is formed on the carrying portion by metal adhesion or copper plating. The method of manufacturing a semiconductor sealing package structure as claimed in claim 11, wherein the groove has a first side and a second side opposite to each other, and the height of the first side is equal to or greater than the height of the second side. The method for manufacturing a semiconductor sealing package structure as claimed in claim 11, wherein the cover plate is a flat plate. The method of manufacturing a semiconductor sealed package structure as claimed in claim 11, wherein the cover plate includes a flat plate part and a lens part, the lens part is disposed on a side of the flat plate part relatively away from the metal layer and corresponds to the at least one Semiconductor components set. A method for manufacturing a semiconductor sealed package structure as described in claim 11, wherein the at least one semiconductor element includes at least one light-emitting diode and one Zener diode. A method for manufacturing a semiconductor sealed package structure as described in claim 17, wherein the light emitting wavelength of the at least one light emitting diode is between 200 nanometers and 400 nanometers. The method of manufacturing a semiconductor sealed packaging structure as described in claim 11, wherein the cover plate has a light transmittance greater than 85% for light with a wavelength of 200 nanometers to 280 nanometers. A method for manufacturing a semiconductor sealed packaging structure as described in claim 11, wherein the material of the cover plate includes quartz or sapphire.

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