TW202410477A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a semiconductor structure, a gate insulating layer, a first conductive layer, a second conductive layer, a photoelectric conversion structure, a flat layer and a third conductive layer. The second conductive layer includes a first source/drain electrode, a second source/drain electrode, and a bottom electrode. The bottom electrode is separated from the first source/drain electrode and the second source/drain electrode. The photoelectric conversion structure is located on the bottom electrode. The flat layer is located above the second conductive layer. The third conductive layer is located above the flat layer and includes a connection line and a data line. The data line is electrically connected to the first source/drain electrode. The connection line is electrically connected to the second source/drain electrode and the bottom electrode.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof.

Generally speaking, when producing thin film transistors, it is usually necessary to perform multiple deposition processes. These deposition processes are used to form metal layers, semiconductor layers, and insulating layers in thin film transistors. In common thin film transistors, the gate is used to control the distribution of carriers in the semiconductor layer, thereby controlling the conduction of the current between the drain and the source.

The present invention provides a semiconductor device and a manufacturing method thereof, which can improve the problem of source/drain electrodes being damaged due to excessive static electricity during the manufacturing process.

At least one embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a semiconductor structure, a gate insulating layer, a first conductive layer, a second conductive layer, a photoelectric conversion structure, a planar layer, and a third conductive layer. The semiconductor structure is located on the substrate. The first conductive layer includes a gate. The gate overlaps the semiconductor structure, and the gate insulating layer is sandwiched between the gate and the semiconductor structure. The second conductive layer includes a first source/drain, a second source/drain, and a bottom electrode. The first source/drain and the second source/drain are electrically connected to the semiconductor structure. The bottom electrode is separated from the first source/drain and the second source/drain. The photoelectric conversion structure is located on the bottom electrode. The planar layer is located on the second conductive layer. The third conductive layer is located on the planar layer and includes a connection line and a data line. The data line is electrically connected to the first source/drain. The connection line is electrically connected to the second source/drain and the bottom electrode.

At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, including the following steps. A semiconductor structure, a first conductive layer and a gate insulating layer are formed on the substrate, wherein the first conductive layer includes a gate, and the gate overlaps the semiconductor structure, and a gate insulating layer is sandwiched between the gate and the semiconductor structure. forming a second conductive layer including a first source/drain, a second source/drain and a bottom electrode, wherein the first source/drain and the second source/drain are electrically connected to the semiconductor structure, and The bottom electrode is separated from the first source/drain electrode and the second source/drain electrode. A photoelectric conversion structure is formed on the bottom electrode. A flat layer is formed on the second conductive layer. A third conductive layer including connecting lines and data lines is formed on the flat layer, wherein the data lines are electrically connected to the first source/drain, and the connecting lines are electrically connected to the second source/drain and the bottom electrode.

As used herein, "about," "approximately," or "substantially" includes the stated value and the average within an acceptable range of deviations from the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the measurement. A specific amount of associated error (i.e., the limits of the measurement system). For example, "about," "approximately," or "substantially" may mean within one or more deviations from a stated value. The aforementioned deviation is, for example, within ±30%, ±20%, ±10%, or ±5%.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by ordinary technicians in the field to which the present invention belongs. The terms used herein can be further understood as terms defined in commonly used dictionaries, which should be interpreted as having meanings consistent with their meanings in the relevant technology and in the present invention, and will not be interpreted as idealized meanings or overly formal meanings unless the present invention explicitly defines them as such.

Example embodiments are described herein with reference to cross-sectional schematic illustrations and top schematic illustrations of idealized embodiments. Therefore, the drawings omit some shape variations that may occur as a result of manufacturing techniques and/or tolerances. Therefore, embodiments described herein should not be construed as limited to the particular shapes illustrated in the drawings but are to include deviations in shapes that result, for example, from manufacturing. For example, regions shown or described as flat in the drawings may actually have rough and/or non-linear characteristics. Additionally, acute angles shown in the drawings may actually be rounded. Therefore, the shapes shown in the drawings are schematic and not intended to show precise shapes, and the drawings are not intended to limit the scope of the claims.

1A to 11A are schematic top views of a semiconductor device 10 according to an embodiment of the present invention. FIG. 1B to 11B are schematic cross-sectional views along line a-a' of FIG. 1A to 11A, respectively. For the convenience of explanation, some components are omitted in FIG. 1A to 11A.

Referring to FIGS. 1A to 2B , a semiconductor structure 210 , a first conductive layer M1 and a gate insulating layer 120 (not shown in FIGS. 1A and 2A ) are formed on the substrate 100 . As shown in FIGS. 1A and 1B , a buffer layer 110 (not shown in FIGS. 1A and 2A ) is formed on the substrate 100 . In some embodiments, the substrate 100 may be made of glass, quartz, organic polymer, opaque/reflective material (such as conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. s material. The buffer layer 110 has a single-layer or multi-layer structure. In some embodiments, the material of the buffer layer 110 includes silicon oxide, silicon nitride, silicon oxynitride, a combination of the above materials, or other suitable materials.

A semiconductor structure 210 is formed on the buffer layer 110. In some embodiments, a semiconductor material layer (not shown) is formed on the buffer layer 110, and then the semiconductor material layer is patterned by a lithography process and an etching process to form one or more semiconductor structures 210. The semiconductor structure 210 has a single-layer or multi-layer structure. In some embodiments, the material of the semiconductor structure 210 includes amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor material, oxide semiconductor material (for example: indium zinc oxide, indium gallium zinc oxide or other suitable materials, or a combination of the above materials) or other suitable materials or a combination of the above materials.

Referring to FIGS. 2A and 2B , a gate insulating layer 120 is formed on the semiconductor structure 210 and the buffer layer 110 . In some embodiments, the material of the gate insulating layer 120 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, combinations of the above materials, or other suitable materials.

A first conductive layer M1 is formed on the gate insulating layer 120. The first conductive layer M1 includes one or more gates 220. The gate 220 overlaps the semiconductor structure 210, and the gate insulating layer 120 is sandwiched between the gate 220 and the semiconductor structure 210. In some embodiments, a first conductive material layer (not shown) is formed on the gate insulating layer 120, and then the first conductive material layer is patterned by a lithography process and an etching process to form one or more gates 220. The first conductive layer M1 has a single-layer or multi-layer structure. In some embodiments, the material of the first conductive layer M1 includes metals such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, their alloys, their metal oxides, their metal nitrides, or combinations thereof or other conductive materials.

In this embodiment, the semiconductor structure 210, the gate insulating layer 120 and the gate 220 are formed in sequence, and the semiconductor structure 210 is located below the gate 220, but the present invention is not limited thereto. In other embodiments, the gate 220, the gate insulating layer 120 and the semiconductor structure 210 are formed in sequence, and the semiconductor structure 210 is located above the gate 220.

In this embodiment, the gate insulating layer 120 blankets the semiconductor structure 210 and the buffer layer 110, but the present invention is not limited thereto. In other embodiments, the gate insulating layer 120 is patterned using the first conductive layer M1 as a mask, so that the first conductive layer M1 and the gate insulating layer 120 have the same pattern.

Referring to FIGS. 3A and 3B , an interlayer dielectric layer 130 (not shown in FIG. 3A ) is formed on the gate insulating layer 120 . In some embodiments, interlayer dielectric layer 130 covers gate 220 . In some embodiments, after the interlayer dielectric layer 130 is formed, a patterning process is performed on the interlayer dielectric layer 130 and the gate insulating layer 120 to form openings 132 and 134 exposing the semiconductor structure 210 . In some embodiments, the openings 132 and 134 pass through the interlayer dielectric layer 130 and the gate insulating layer 120 . In some embodiments, the foregoing patterning process also forms openings 136 and 138 that expose the gate 220 , wherein the openings 136 and 138 pass through the interlayer dielectric layer 130 . In some embodiments, the material of the interlayer dielectric layer 130 includes silicon oxide, silicon nitride, silicon oxynitride, organic insulating materials, combinations of the above materials, or other suitable materials.

4A and 4B , a second conductive layer M2 is formed on the interlayer dielectric layer 130. The second conductive layer M2 includes a first source/drain 230, a second source/drain 232, and a bottom electrode 234. The first source/drain 230 fills the opening 132 and is electrically connected to the semiconductor structure 210. The second source/drain 232 fills the opening 134 and is electrically connected to the semiconductor structure 210. The bottom electrode 234 is separated from the first source/drain 230 and the second source/drain 232. In some embodiments, the second conductive layer M2 further includes a scan line 236. The scanning line 236 fills the openings 136 and 138 and is electrically connected to the gate 220. In some embodiments, a second conductive material layer (not shown) is formed on the interlayer dielectric layer 130, and then the second conductive material layer is patterned by lithography and etching processes to form one or more first source/drain electrodes 230, one or more second source/drain electrodes 232, one or more bottom electrodes 234, and one or more scanning lines 236. The second conductive layer M2 has a single-layer or multi-layer structure. In some embodiments, the material of the second conductive layer M2 includes metals such as chromium, gold, silver, copper, tin, lead, cobalt, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, their alloys, their metal oxides, their metal nitrides, or combinations thereof or other conductive materials.

Although in this embodiment, the scan line 236 belongs to the second conductive layer M2, the present invention is not limited thereto. In other embodiments, the scan line 236 belongs to the first conductive layer. In other words, the scan line 236 can be formed simultaneously with the gate 220. In this embodiment, the thin film transistor T includes a semiconductor structure 210, a gate 220, a first source/drain 230, and a second source/drain 232. In this embodiment, the thin film transistor T is a top gate thin film transistor, but the present invention is not limited thereto. In other embodiments, the thin film transistor T is a bottom gate thin film transistor, a double gate thin film transistor, or other types of thin film transistors.

In this embodiment, the bottom electrode 234 is separated from the first source/drain 230 and the second source/drain 232 . Therefore, even if the bottom electrode 234 generates static electricity in subsequent processes, the charge will not cause damage to the first source/drain 230 and the second source/drain 232 . Specifically, since the width of the second source/drain 232 is small and the second source/drain 232 is not connected to other wires that can release charges, if the bottom electrode 234 is directly connected to the second source /Drain 232, the charge will be easily discharged from the position of the second source/drain 232, causing explosion damage around the second source/drain 232. In other words, if the bottom electrode 234 is directly connected to the second source/drain 232, the static electricity generated during the manufacturing process of the bottom electrode 234 with a larger area will discharge the charge through the path of the second source/drain 232, and Causes static electricity to damage components.

5A and 5B, a first insulating layer 140 (not shown in FIG. 5A) is formed on the second conductive layer M2 and the interlayer dielectric layer 130. In some embodiments, the first insulating layer 140 includes an inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide or other suitable materials. In some embodiments, the first insulating layer 140 is patterned by a lithography process and an etching process to form an opening 142 exposing the bottom electrode 234.

Referring to FIGS. 6A and 6B , a photoelectric conversion structure L is formed on the bottom electrode 234 . The photoelectric conversion structure L is connected to the bottom electrode 234 through the opening 142 in the first insulation layer 140 . In this embodiment, the photoelectric conversion structure L is a PIN diode and includes a first semiconductor layer 240, a second semiconductor layer 242, and a third semiconductor layer 244. One of the first semiconductor layer 240 and the third semiconductor layer 244 is a P-type semiconductor, and the other is an N-type semiconductor. The second semiconductor layer 242 is a low-doped semiconductor or an intrinsic semiconductor. In other embodiments, the photoelectric conversion structure L is a PN-type diode, and the second semiconductor layer 242 may be omitted. In other embodiments, the photoelectric conversion structure L can also be other photosensitive material layers, such as a silicon-rich silicon oxide layer, a silicon-rich silicon nitride layer, a silicon-rich silicon oxynitride layer, a silicon-rich silicon carbide layer, a silicon-rich silicon carbon oxide layer. layer, a hydrogenated silicon-rich silicon oxide layer, a hydrogenated silicon-rich silicon nitride layer, a hydrogenated silicon-rich silicon carbide layer, or a combination thereof.

A top electrode 250 is formed on the photoelectric conversion structure L. In some embodiments, the top electrode 250 includes a transparent conductive material, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, or a stacked layer of at least two of the above.

In some embodiments, the method for forming the photoelectric conversion structure L and the top electrode 250 includes the following steps. A first semiconductor material layer (not shown), a second semiconductor material layer (not shown), a third semiconductor material layer (not shown), and a transparent conductive material layer (not shown) are sequentially formed. Then, the transparent conductive material layer is patterned by a lithography process and an etching process to form one or more top electrodes 250. Finally, the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer are patterned by a lithography process and an etching process again to form one or more photoelectric conversion structures L. In some embodiments, the area of the top electrode 250 vertically projected on the substrate 100 is smaller than the area of the photoelectric conversion structure L vertically projected on the substrate 100, but the present invention is not limited thereto. In other embodiments, the first semiconductor material layer, the second semiconductor material layer, the third semiconductor material layer, and the transparent conductive material layer are patterned by a single etching process to form the photoelectric conversion structure L and the top electrode 250, so that the sidewalls of the photoelectric conversion structure L are aligned with the sidewalls of the top electrode 250.

Referring to FIGS. 7A and 7B , a flat layer 160 (not shown in FIG. 7A ) is formed on the second conductive layer M2. In this embodiment, the second insulating layer 150 (not shown in FIG. 7A ) is first formed on the first insulating layer 140 (not shown in FIG. 7A ), the photoelectric conversion structure L and the top electrode 250 . Then, a flat layer 160 is formed on the second insulating layer 150 . The photoelectric conversion structure L and the top electrode 250 are located between the second insulating layer 150 and the bottom electrode 234 .

In some embodiments, the second insulating layer 150 includes an inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or other suitable materials. In some embodiments, the material of the flat layer 160 includes silicon oxide, silicon nitride, silicon oxynitride, organic insulating materials, combinations of the above materials, or other suitable materials.

After the planarization layer 160 is formed, a patterning process is performed to form the first opening 164 exposing the second source/drain 232 , the second opening 166 exposing the bottom electrode 234 , the first source/drain 232 , the second opening 166 exposing the bottom electrode 234 The third opening 162 of the pole 230 and the fourth opening 168 of the top electrode 250 are exposed, wherein the fourth opening 168 overlaps the photoelectric conversion structure L. In this embodiment, the first opening 164, the second opening 166 and the third opening 162 pass through the flat layer 160, the second insulating layer 150 and the first insulating layer 140, and the fourth opening 168 passes through the flat layer 160, the second insulating layer 150 and the first insulating layer 140. layer 160 and the second insulating layer 150 . In some embodiments, the patterning process includes one or more photolithography processes and etching processes.

Referring to FIGS. 8A and 8B , a third insulating layer 170 (not shown in FIG. 8A ) is formed on the flat layer 160 . The third insulating layer 170 fills the first opening 164 , the second opening 166 , the third opening 162 and the fourth opening 168 . In some embodiments, the third insulating layer 170 includes an inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or other suitable materials.

Next, a patterning process is performed on the third insulating layer 170 to form a first through hole 174 that exposes the second source/drain electrode 232, a second through hole 176 that exposes the bottom electrode 234, and a first source electrode that is exposed. The third through hole 172 of the drain electrode 230 and the fourth through hole 178 exposing the top electrode 250 are overlapped with the photoelectric conversion structure L. The first through hole 174 , the second through hole 176 , the third through hole 172 and the fourth through hole 178 overlap with the first opening 164 , the second opening 166 , the third opening 162 and the fourth opening 168 respectively. In some examples, the areas of the first through hole 174 , the second through hole 176 , the third through hole 172 and the fourth through hole 178 are respectively smaller than the first opening 164 , the second opening 166 , the third opening 162 and The area of the fourth opening 168 , therefore, the third insulating layer 170 covers the sidewalls of the first opening 164 , the sidewalls of the second opening 166 , the sidewalls of the third opening 162 and the sidewalls of the fourth opening 168 .

Referring to FIGS. 9A and 9B , a third conductive layer M3 is formed on the flat layer 160 . In this embodiment, a third conductive layer M3 is formed on the third insulating layer 170 . The third conductive layer M3 includes data lines 260, connection lines 262 and transfer electrodes 264. In some embodiments, a third conductive material layer (not shown) is formed on the third insulating layer 170, and then the third conductive material layer is patterned through a photolithography process and an etching process to form one or more data lines. 260, one or more connecting wires 262, and one or more transfer electrodes 264. The third conductive layer M3 has a single-layer or multi-layer structure. In some embodiments, the material of the third conductive layer M3 includes chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc and other metals, the above alloys, the above metal oxides material, the above metal nitride or a combination of the above or other conductive materials.

The connecting wire 262 fills the first opening 164 and the first through hole 174 to form the first contact hole CH1, and the connecting wire 262 fills the second opening 166 and the second through hole 176 to form the second contact hole CH2. The first contact hole CH1 and the second contact hole CH2 pass through the first insulating layer 140 , the second insulating layer 150 , the flat layer 160 and the third insulating layer 170 . The connection line 262 is electrically connected to the second source/drain 232 through the first contact hole CH1, and the connection line 262 is electrically connected to the bottom electrode 234 through the second contact hole CH2. In some embodiments, the side surface of the photoelectric conversion structure L includes a groove G, and the second contact hole CH2 is located in the groove G. Through the setting of groove G, the problem of short circuit can be avoided.

The data line 260 fills the third opening 162 and the third through hole 172 to form the third contact hole CH3. The third contact hole CH3 passes through the first insulating layer 140 , the second insulating layer 150 , the flat layer 160 and the third insulating layer 170 . The data line 260 is electrically connected to the first source/drain 230 through the third contact hole CH3.

The transfer electrode 264 is filled into the fourth opening 168 and the fourth through hole 178 to form a fourth contact hole CH4. The fourth contact hole CH4 passes through the second insulating layer 150, the planar layer 160 and the third insulating layer 170. The transfer electrode 264 is electrically connected to the top electrode 250 through the fourth contact hole CH4.

In some embodiments, since the area of the bottom electrode 234 is relatively large (e.g., larger than the area of the first source/drain 230 and the area of the second source/drain 232), the bottom electrode 234 is prone to accumulate static electricity during multiple deposition and patterning processes. In this embodiment, after the third conductive layer M3 is formed, the static electricity on the bottom electrode 234 can be released through the third conductive layer M3. For example, when a third conductive material layer (not shown) is deposited to form the third conductive layer M3, the charge accumulated on the bottom electrode 234 can be uniformly released through the entire deposited third conductive material layer, thereby avoiding the problem of the first source/drain 230 and the second source/drain 232 being damaged during the manufacturing process. In some embodiments, after the third conductive material layer is patterned to form the data line 260 and the connection line 262, the charge accumulated on the bottom electrode 264 is released through the connection line 262, the second source/drain 232, the semiconductor structure 210, the first source/drain 230, and the data line 260.

Referring to FIGS. 10A and 10B , a fourth insulating layer 180 (not shown in FIG. 10A ) is formed on the third insulating layer 170 and the third conductive layer M3. In some embodiments, the fourth insulating layer 180 includes an inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or other suitable materials. In some embodiments, the fourth insulating layer 180 is patterned through a photolithography process and an etching process to form an opening 182 exposing the transfer electrode 264 .

Referring to FIG. 11A and FIG. 11B , the signal line 270 is formed on the fourth insulating layer 180 . The signal line 270 is filled in the opening 182 and electrically connected to the transfer electrode 264 . In some embodiments, a fourth conductive material layer (not shown) is formed on the fourth insulating layer 180, and then the fourth conductive material layer is patterned through a photolithography process and an etching process to form one or more signal lines. 270. The signal line 270 has a single-layer or multi-layer structure. In some embodiments, the material of the signal line 270 includes chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc and other metals, the above alloys, the above metal oxides, The above metal nitride or a combination of the above or other conductive materials.

In some embodiments, part of the signal lines 270 overlaps the semiconductor structure 210, thereby reducing the impact of external light or external electric fields on the semiconductor structure 210.

Based on the above, since the bottom electrode 234 in the second conductive layer M2 is separated from the first source/drain 230 and the second source/drain 232, it is possible to avoid the static electricity accumulated in the bottom electrode 234 during the process from affecting the first source. The pole/drain 230 and the second source/drain 232 are damaged.

FIG. 12A is a schematic top view of a semiconductor device 20 according to a comparative example of the present invention. Fig. 12B is a schematic cross-sectional view along line a-a' of Fig. 12A.

In the comparative example of FIG. 12A and FIG. 12B , the bottom electrode 234 of the semiconductor device 20 is directly connected to the second source/drain 232 , and the semiconductor device 20 does not include a connection line 262 .

FIG. 13 is a test photo of a photosensitive device according to a comparative example of the present invention. The photosensitive device in FIG. 13 includes multiple photosensitive units. The structure of each photosensitive unit is as shown in the semiconductor device 20 of FIG. 12A and FIG. 12B . FIG. 14 is a test photo of a photosensitive device according to an embodiment of the present invention. The photosensitive device in FIG. 14 includes a plurality of photosensitive units. The structure of each photosensitive unit is as shown in the semiconductor device 10 of FIGS. 11A and 11B .

Referring to FIG. 13 , the photosensitive device including the semiconductor device 20 has obvious MURA in the middle and edges of the photo. Referring to FIG. 14 , the photosensitive device including the semiconductor device 10 significantly improves the MURA at the center and edges of the photo. It can be known from the results of FIGS. 13 and 14 that by separating the bottom electrode 234 from the second source/drain 232 (please refer to FIGS. 11A and 11B ), the problem of MURA in the photosensitive device can be reduced.

10, 20:Semiconductor device 100:Substrate 110: Buffer layer 120: Gate insulation layer 130: Interlayer dielectric layer 132, 134, 136, 138, 142, 182: opening 140: First insulation layer 150: Second insulation layer 160:Flat layer 162:Third opening 164:First opening 166:Second opening 168:Fourth opening 170:Third insulation layer 172:Third through hole 174: First through hole 176: Second through hole 178:Fourth through hole 180:Fourth insulation layer 210:Semiconductor Structure 220: Gate 230: First source/drain 232: Second source/drain 234: Bottom electrode 236:Scan line 240: First semiconductor layer 242: Second semiconductor layer 244:Third semiconductor layer 250:Top electrode 260:Data line 262:Connecting line 264: Adapter electrode 270:Signal line a-a’: line CH1: first contact hole CH2: Second contact hole CH3: Third contact hole CH4: The fourth contact hole G: Groove L: Photoelectric conversion structure M1: first conductive layer M2: Second conductive layer M3: The third conductive layer T: thin film transistor

1A to 11A are schematic top views of a semiconductor device according to an embodiment of the present invention. 1B to 11B are schematic cross-sectional views along line a-a’ of FIGS. 1A to 11A respectively. FIG. 12A is a schematic top view of a semiconductor device according to a comparative example of the present invention. Fig. 12B is a schematic cross-sectional view along line a-a' of Fig. 12A. Figure 13 is a test photo of a photosensitive device according to a comparative example of the present invention. Figure 14 is a test photo of a photosensitive device according to an embodiment of the present invention.

10: Semiconductor devices

100: Substrate

110: Buffer layer

120: Gate insulation layer

130: Interlayer dielectric layer

140: First insulation layer

150: Second insulation layer

160: Flat layer

170:Third insulation layer

180:Fourth insulation layer

210:Semiconductor Structure

220: Gate

230: First source/drain

232: Second source/drain

234: Bottom electrode

240: First semiconductor layer

242: Second semiconductor layer

244:Third semiconductor layer

250: Top electrode

260: Data line

262:Connection line

264: Switching electrode

270:Signal line

a-a’: line

L: Photoelectric conversion structure

T: Thin Film Transistor

Claims (10)

A semiconductor device including: a substrate; a semiconductor structure located on the substrate; a first conductive layer including a gate, wherein the gate overlaps the semiconductor structure, and a gate insulating layer is sandwiched between the gate and the semiconductor structure; a second conductive layer, including a first source/drain, a second source/drain and a bottom electrode, wherein the first source/drain is electrically connected to the second source/drain to the semiconductor structure, and the bottom electrode is separated from the first source/drain and the second source/drain; a photoelectric conversion structure located on the bottom electrode; a flat layer located on the second conductive layer; and A third conductive layer is located on the flat layer and includes a connection line and a data line, wherein the data line is electrically connected to the first source/drain, and the connection line is electrically connected to the second source pole/drain and the bottom electrode. The semiconductor device as claimed in claim 1 further includes: an interlayer dielectric layer located above the gate insulating layer; a first insulating layer located on the second conductive layer and the interlayer dielectric layer, wherein the photoelectric conversion structure is connected to the bottom electrode through the opening in the first insulating layer; a second insulating layer located on the first insulating layer and the photoelectric conversion structure, wherein the photoelectric conversion structure is located between the second insulating layer and the bottom electrode, and the flat layer is located on the second insulating layer; A third insulating layer is located on the planar layer, wherein a first contact hole, a second contact hole and a third contact hole pass through the first insulating layer, the second insulating layer, the planar layer and the third contact hole. Three insulating layers, in which the connection lines are electrically connected to the second source/drain and the bottom electrode through the first contact hole and the second contact hole respectively, and the data line passes through the third contact hole. Electrically connected to the first source/drain. The semiconductor device as described in claim 2 further comprises: A top electrode located on the photoelectric conversion structure, wherein the third conductive layer further comprises a transfer electrode, the transfer electrode is electrically connected to the top electrode through a fourth contact hole, wherein the fourth contact hole passes through the second insulating layer, the planar layer and the third insulating layer. The semiconductor device as claimed in claim 3 further includes: a fourth insulating layer located on the third insulating layer and the third conductive layer; and A signal line is located on the fourth insulating layer and electrically connected to the transfer electrode. The semiconductor device of claim 1, wherein a first contact hole and a second contact hole pass through the planar layer, and wherein the connection lines are electrically connected through the first contact hole and the second contact hole respectively. The second source/drain electrode and the bottom electrode, the side surface of the photoelectric conversion structure include a groove, and the second contact hole is located in the groove. A method of manufacturing a semiconductor device, including: A semiconductor structure, a first conductive layer and a gate insulating layer are formed on a substrate, wherein the first conductive layer includes a gate, the gate overlaps the semiconductor structure, and the gate is connected to the semiconductor structure. The gate insulation layer is sandwiched between them; Forming a second conductive layer including a first source/drain, a second source/drain and a bottom electrode, wherein the first source/drain and the second source/drain are electrically Connected to the semiconductor structure, and the bottom electrode is separated from the first source/drain and the second source/drain; Form a photoelectric conversion structure on the bottom electrode; forming a flat layer on the second conductive layer; and Forming a third conductive layer including a connection line and a data line on the flat layer, wherein the data line is electrically connected to the first source/drain, and the connection line is electrically connected to the second source /Drain and the bottom electrode. The manufacturing method as described in claim 6, wherein after forming the third conductive layer, static electricity on the bottom electrode is reduced. The manufacturing method as described in claim 6 further includes: forming an interlayer dielectric layer on the gate insulating layer and the first conductive layer, and the second conductive layer is formed on the interlayer dielectric layer; forming a first insulating layer on the second conductive layer and the interlayer dielectric layer, wherein the photoelectric conversion structure is connected to the bottom electrode through the opening in the first insulating layer; forming a second insulating layer on the first insulating layer and the photoelectric conversion structure, wherein the photoelectric conversion structure is located between the second insulating layer and the bottom electrode; and forming the planar layer on the second insulating layer. The manufacturing method as described in claim 8 further includes: After forming the planarization layer, a first patterning process is performed to form a first opening exposing the second source/drain electrode, a second opening exposing the bottom electrode, and a first opening exposing the bottom electrode. a third opening of the source/drain; Forming a third insulating layer on the flat layer, and filling the first opening, the second opening and the third opening; A second patterning process is performed on the third insulating layer to form a first through hole exposing the second source/drain electrode, a second through hole exposing the bottom electrode, and a first through hole exposing the bottom electrode. A third through hole of the source/drain, wherein the first through hole, the second through hole and the third through hole overlap the first opening, the second opening and the third opening respectively , wherein the connecting line fills the first opening and the first through hole to form a first contact hole, and the connecting line fills the second opening and the second through hole to form a second contact hole, And the data line fills the third opening and the third through hole to form a third contact hole. The manufacturing method as described in claim 9 further includes: forming a top electrode on the photoelectric conversion structure; Perform the first patterning process to form a fourth opening exposing the top electrode; The third insulating layer is formed on the flat layer, and the third insulating layer fills the fourth opening; Perform the second patterning process on the third insulating layer to form a fourth through hole exposing the top electrode; The third conductive layer is formed on the third insulating layer, wherein the third conductive layer further includes a transfer electrode, and the transfer electrode fills the fourth opening and the fourth through hole to form a fourth contact hole; Forming a fourth insulating layer on the third insulating layer and the third conductive layer; and A signal line is formed on the fourth insulating layer and electrically connected to the transfer electrode.

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