TW202410392A - Semiconductor memory device - Google Patents

Abstract

Provided is a semiconductor memory device. The semiconductor memory device includes a substrate including an active region defined by a device isolation layer, a bit line which is disposed on the substrate and extends in a first direction, a bit line contact which is disposed between the bit line and the substrate and connects the bit line to the active region, a bit line spacer which extends along a sidewall of the bit line, and a bit line contact spacer which extends along a sidewall of the bit line contact and does not extend along the sidewall of the bit line.

Description

semiconductor memory device

The present disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a plurality of interconnected lines and buried contacts.

Cross-reference to related applications This application claims priority to Korean Patent Application No. 10-2022-0104243 filed on August 19, 2022 in the Korean Intellectual Property Office, the contents of which are hereby incorporated by reference in their entirety.

As semiconductor devices become more highly integrated, individual circuit patterns become more miniaturized to implement more semiconductor devices in the same area. For example, as the integration level of a semiconductor device increases, the design rules for the components of the semiconductor device decrease.

In highly scaled-down semiconductor devices, the process of forming multiple circuits and multiple embedded contacts and multiple direct contacts inserted between the multiple circuits has become increasingly complex and difficult. In highly scaled-down semiconductor devices where space between adjacent buried contacts and direct contacts is limited, short circuits may occur if adjacent buried contacts and direct contacts are not properly separated. Therefore, there is a need to develop robust structures and/or processes that can reliably separate adjacent contacts so that short circuits between adjacent contacts in highly scaled-down semiconductor devices can be prevented.

Embodiments of the present disclosure provide a semiconductor memory device with enhanced reliability and performance.

According to an embodiment of the present disclosure, a semiconductor memory device is provided, comprising: a substrate including an active region defined by a device isolation layer; a bit line disposed on the substrate and extending in a first direction; a bit line contact disposed between the bit line and the substrate and connecting the bit line to the active region; a bit line spacer extending along a sidewall of the bit line; and a bit line contact spacer extending along a sidewall of the bit line contact and not extending along the sidewall of the bit line.

According to an embodiment of the present disclosure, a semiconductor memory device is provided, including: a substrate including first to third active areas defined by a device isolation layer, and the second active area is disposed in the first active area and the third active area between; a bit line contact, disposed on the substrate and connected to the second active area; a first storage contact, disposed on the substrate and connected to the first active area; a second storage contact, disposed on the substrate and Connected to the third active area; the bit line contact spacer is disposed on the substrate and disposed between the bit line contact and the first storage contact and between the bit line contact and the second storage contact ; and a bit line, disposed on the bit line contact, extending in the first direction, and in contact with the upper surface of the bit line contact spacer.

According to an embodiment of the present disclosure, a semiconductor memory device is provided, including: a substrate including an active region defined by a device isolation layer and extending in a first direction; the active region includes a first region and is defined on an opposite side of the first region a second region on the substrate; a word line extending in a second direction in the substrate and the device isolation layer and spanning the first region of the active region and a second region of the active region; a bit line disposed on the substrate and the device isolation layer on, extending in a third direction orthogonal to the second direction, and connected to the first area of the active area; the bit line contact is arranged between the bit line and the substrate and connected to the bit line, the bit line The width of the upper surface of the contact in the second direction is smaller than the width of the bottom surface of the bit line in the second direction; the storage contact is disposed on the substrate and connected to the second active area adjacent to the active area. a region; a storage pad disposed on and connected to the storage contact; and a capacitor disposed on the storage pad and connected to the storage pad.

It should be noted that the effects of the present disclosure are not limited to the effects described above, and other effects of the present disclosure will be apparent from the following description.

It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, a first element, a first component, or a first section discussed below may be referred to as a second element, a second component, or a second section without departing from the teachings of the present disclosure. Similarly, a second element, a second component, or a second section may also be referred to as a first element, a first component, or a first section.

FIG. 1 is a schematic layout diagram of a semiconductor memory device according to an embodiment of the present disclosure. FIG. 2 is a layout diagram of only word lines and active regions of FIG. 1 . FIG. 3 is a cross-sectional view taken along line A-A of FIG. 1 . FIG. 4 is a cross-sectional view taken along line B-B of FIG. 1 . FIG. 5 is an enlarged view of portion P of FIG. 3 .

In the diagrams of semiconductor devices according to embodiments of the present disclosure, a dynamic random access memory (DRAM) is shown by way of example.

1 and 2 , a semiconductor memory device according to an embodiment of the present disclosure may include a plurality of cell active areas ACT.

The cell active area ACT may be defined by a cell device isolation layer 105 formed in a substrate 100 (see FIG. 3 ). When viewed in a plan view, the cell active area ACT may correspond to a portion of the substrate 100 surrounded by the cell device isolation layer 105 (see FIG. 2 ). As the design rules of semiconductor devices decrease, the cell active area ACT may be arranged in the form of diagonal lines or miter strips, as illustrated in the drawings. For example, the cell active area ACT may extend in a third direction DR3. The cell active areas ACT may be arranged in parallel to each other, so that one of the cell active areas ACT may have an end portion adjacent to a central portion of a neighbor in the cell active area ACT.

The plurality of gate electrodes may extend across the cell active area ACT in the first direction DR1. The gate electrodes may extend parallel to each other. The gate electrode may be, for example, a plurality of word lines WL. The word lines WL may be arranged at equal intervals in the first direction DR1. The width of each word line WL or the spacing between adjacent word lines WL can be determined according to design rules. For example, the word line WL may extend across the cell active region ACT and may be disposed in a groove (the cell gate trench of FIG. 4 ) formed in the cell device isolation layer 105 (see FIG. 4 ) and the cell active region ACT. slot 115).

Each of the cell active areas ACT may be divided into three parts by two word lines WL extending in the first direction DR1. Each of the cell active areas ACT may include a storage connection area 103b and a bit line connection area 103a. The bit line connection area 103a may be located in the middle part of each of the cell active areas ACT, and the storage connection areas 103b may be located at opposite ends of each of the cell active areas ACT.

The bit line connection area 103a may be an area connected to the bit line BL, and the storage connection area 103b may be an area connected to the information storage part 190 (see FIG. 3). In other words, the bit line connection region 103a can be a common drain region, and the storage connection region 103b can be a source region. Each of the word line WL, the bit line connection region 103a adjacent to the word line WL, and the storage connection region 103b adjacent to the word line WL may form a transistor.

A plurality of bit lines BL may be arranged on the word lines WL to extend in a second direction DR2 orthogonal to the word lines WL. For example, the second direction DR2 may be orthogonal to the first direction DR1. The bit lines BL may extend parallel to each other. The bit lines BL may be arranged at equal intervals in the first direction DR1. The width of each bit line BL or the interval between bit lines BL adjacent to each other may be determined according to a design rule.

The fourth direction DR4 may be orthogonal to the first direction DR1, the second direction DR2, and the third direction DR3. The fourth direction DR4 may be the thickness direction of the substrate 100 .

The semiconductor memory device according to the embodiment of the present disclosure may include various contact arrays formed on the cell active area ACT. The various contact arrays may include, for example, direct contacts DC, buried contacts BC, and landing pads LP.

Here, the direct contact DC may be a contact electrically connecting the cell active area ACT to the bit line BL. The buried contact BC may be a contact connecting the cell active area ACT to the lower electrode 191 of the capacitor (see Figure 3). The buried contacts BC may be respectively disposed between a pair of adjacent bit lines BL in plan view, and may be spaced apart from each other in the first direction DR1. In addition, the buried contacts BC may be respectively disposed between a pair of adjacent word lines WL in plan view, and may be spaced apart from each other in the second direction DR2. In the embodiment of the present disclosure, in plan view, two adjacent buried contacts BC may be disposed symmetrically relative to the bit line BL inserted therebetween, and the two adjacent buried contacts BC may not be disposed relative to the word line BL inserted therebetween. The element line WL is arranged symmetrically. Due to the configuration structure, the contact area between the embedded contact BC and the unit active area ACT may be small. Therefore, the conductive landing pad LP can be introduced to increase the contact area between the embedded contact BC and the cell active area ACT, and also increase the contact area between the embedded contact BC and the lower electrode 191 of the capacitor (see FIG. 3 ).

The landing pad LP may be disposed between the buried contact BC and the lower electrode 191 of the capacitor (see FIG. 3 ), and may be electrically connected to the buried contact BC and the lower electrode 191 of the capacitor. The increased contact area by introducing the landing pad LP may reduce the contact resistance between the cell active region ACT and the lower electrode 191 of the capacitor.

The direct contact DC may be connected to the bit line connection region 103a. The buried contact BC may be connected to the storage connection region 103b. Since the buried contact BC is disposed at opposite ends of each cell active region ACT, the landing pad LP may be disposed adjacent to the opposite ends of each cell active region ACT so as to partially overlap with the buried contact BC. For example, the buried contact BC (storage contact 120 of FIGS. 3 and 4 ) may be formed to overlap with the cell active region ACT and the cell device isolation layer 105 (see FIGS. 3 and 4 ), which is disposed between the adjacent word line WL (cell gate electrode 112 of FIG. 4 ) and between the adjacent bit line BL (cell conductive line 140 of FIG. 3 ).

The word line WL may be buried in the substrate 100. The word line WL may intersect the cell active area ACT located between the direct contact DC or the buried contact BC. As shown, two word lines WL may intersect one cell active area ACT. Since the cell active area ACT extends in the third direction DR3, the word line WL may form an angle less than 90 degrees with the cell active area ACT. For example, the bit line BL extending in the second direction DR2 may be orthogonal to the word line WL extending in the first direction DR1, and the active area ACT may have a strip shape extending in the third direction DR3, and therefore, as shown in FIG. 1, the third direction DR3 may be inclined at a predetermined angle relative to the first direction DR1 or the second direction DR2. The predetermined angle may vary to a certain extent. In the embodiment of the present disclosure, the predetermined angle may be in the range of about 10° to about 80°.

Two adjacent buried contacts BC may be positioned symmetrically with respect to one direct contact DC placed on one of the active areas ACT of the cell. For example, the direct contact DC and the embedded contact BC may be spaced apart from each other in the first direction DR1. The landing pad LP may be disposed on the cell active area ACT in a Z-shaped manner in the second direction DR2 in which the bit line BL extends. In addition, the landing pad LP may overlap with the same side of each bit line BL in the first direction DR1 in which the word line WL extends.

For example, each landing pad LP of the first line may overlap the left side of the corresponding bit line BL, and each landing pad LP of the second line may overlap the right side of the corresponding bit line BL.

1 to 5 , a semiconductor memory device according to an embodiment of the present disclosure may include a plurality of cell gate structures 110 , a plurality of bit line structures 140ST , a plurality of storage contacts 120 , a plurality of bit line contacts 146 , and an information storage portion 190 .

The substrate 100 may be a silicon substrate or a silicon-on-insulator (SOI). Alternatively, the substrate 100 may include, but is not limited to, silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimonide (InSb), lead telluride (PbTe), indium arsenide (InAs), indium phosphide (InP), gallium arsenide (GaAs), gallium phosphide (GaP), or gallium antimonide (GaSb). In addition, the substrate 100 may include one or more semiconductor layers or structures, and may include an active or operable portion of a semiconductor device.

The cell device isolation layer 105 may be formed in the substrate 100. The cell device isolation layer 105 may have a shallow trench isolation (STI) structure having excellent device isolation characteristics. The cell device isolation layer 105 may define a cell active area ACT in the memory cell area.

The cell active region ACT defined by the cell device isolation layer 105 may be shaped as a long island shape, each of which includes a short axis and a long axis as shown in FIGS. 1 and 2 . The cell active region ACT may be shaped as a diagonal line that forms an angle of less than 90 degrees with the word line WL formed in the cell device isolation layer 105. In addition, the cell active region ACT may be shaped as a diagonal line that forms an angle of less than 90 degrees with the bit line BL formed on the cell device isolation layer 105. By arranging a plurality of cell active regions ACT in the direction of a diagonal line or a tilted line, the maximum possible distance between contacts may be provided for a semiconductor memory device.

The unit device isolation layer 105 may include, but is not limited to, at least one of a silicon oxide (SiO ₂ ) layer, a silicon nitride (Si ₃ N ₄ ) layer, or a silicon oxynitride (SiON) layer.

Although the cell device isolation layer 105 is formed as a single insulating layer in the figure, this is only for ease of description and the present disclosure is not limited thereto. The cell device isolation layer 105 may be formed of a single insulating layer or a plurality of insulating layers depending on the distance from the adjacent cell active region ACT.

In FIGS. 3 and 5 , the upper surface of the unit device isolation layer 105 and the upper surface 100US of the substrate are coplanar with each other. However, this is only for ease of description, and the present disclosure is not limited thereto.

The cell gate structure 110 may be formed in the substrate 100 and the cell device isolation layer 105. The cell gate structure 110 may be formed across the cell device isolation layer 105 and the cell active region ACT defined by the cell device isolation layer 105.

Each of the cell gate structures 110 may include a cell gate trench 115 , a cell gate insulating layer 111 , a cell gate electrode 112 , a cell gate capping pattern 113 , and a cell gate capping conductive layer 114 .

Here, the cell gate electrode 112 may correspond to the word line WL. For example, the cell gate electrode 112 may be the word line WL of FIG. 1 . Different from the figures, in the embodiment of the present disclosure, the cell gate structure 110 may not include the cell gate capping conductive layer 114 .

The cell gate trench 115 may be relatively deep in the cell device isolation layer 105 and relatively shallow in the cell active area ACT. The bottom surface of the word line WL may be curved. That is, the depth of the cell gate trench 115 in the cell device isolation layer 105 may be greater than the depth of the cell gate trench 115 in the cell active area ACT.

The cell gate insulating layer 111 may extend along the sidewall and bottom surface of the cell gate trench 115. The cell gate insulating layer 111 may extend along the outline of at least a portion of the cell gate trench 115.

The cell gate insulating layer 111 may include, for example, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or a dielectric constant having a higher dielectric constant than silicon oxide (SiO ₂ ). At least one of high dielectric constant (high-k) materials. High-k materials may include, for example, hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), hafnium tantalum oxide (Hf ₂ Ta ₂ O ₉ ), hafnium aluminum oxide (HfAlO ₃ ), oxide Lanthanum (La ₂ O ₃ ), lanthanum aluminum oxide (LaAlO ₃ ), zirconium oxide (ZrO ₂ ), zirconium silicon oxide (ZrSiO ₄ ), tantalum oxide (Ta ₂ O ₅ ), titanium oxide (TiO ₂ ), barium strontium oxide Titanium (BaSrTi ₂ O ₆ ), barium titanium oxide (BaTiO ₃ ), strontium titanium oxide (SrTiO ₃ ), yttrium oxide (Y ₂ O ₃ ), lithium oxide (Li ₂ O), aluminum oxide (Al ₂ O ₃ ), At least one of lead scandium tantalum oxide (Pb(Sc,Ta)O ₃ ), zinc lead niobate [Pb(Zn _1/3 Nb _2/3 )O ₃ ] or a combination thereof.

The cell gate electrode 112 may be formed on the cell gate insulating layer 111 . Cell gate electrode 112 may fill a portion of cell gate trench 115 . The cell gate capping conductive layer 114 may extend along an upper surface of the cell gate electrode 112 .

The cell gate electrode 112 may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride, or a conductive metal oxide. The cell gate electrode 112 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TIC), tantalum carbonitride (TaCN), tungsten (W) 、Aluminum (Al), Copper (Cu), Cobalt (Co), Titanium (Ti), Tantalum (Ta), Nickel (Ni), Platinum (Pt), Nickel platinum (NiPt), Niobium (Nb), Niobium nitride (NbN), Niobium carbide (NbC), Molybdenum (Mo), Molybdenum nitride (MoN), Molybdenum carbide (MoC), Tungsten carbide (WC), Rhodium (Rh), Palladium (Pd), Ir, Niobium (Os), Silver (Ag), Gold (Au), Zinc (Zn), Vanadium (V), Ruthenium titanium nitride (RuTiN), Titanium silicide (TiSi ₂ ), tantalum silicide (TaSi ₂ ), nickel silicide (NiSi ₂ ), cobalt silicide (CoSi ₂ ), iridium oxide (IrO _x ), ruthenium oxide (RuO _x ), or a combination thereof.

The cell gate capping conductive layer 114 may include, but is not limited to, at least one of polycrystalline silicon (p-Si), polycrystalline silicon germanium (p-SiGe), amorphous silicon (a-Si), or amorphous silicon germanium (a-SiGe).

The cell gate capping pattern 113 may be disposed on the cell gate electrode 112 and the cell gate capping conductive layer 114 . The cell gate capping pattern 113 may fill another portion of the cell gate trench 115 that does not include the portion where the cell gate electrode 112 and the cell gate capping conductive layer 114 are formed. Although the cell gate insulating layer 111 is shown extending along the sidewalls of the cell gate capping pattern 113, the present disclosure is not limited thereto. For example, in the embodiment of the present disclosure, the cell gate insulating layer 111 may extend along the sidewalls of the cell gate electrode 112 and the cell gate capping conductive layer 114, but may not extend along the cell gate capping pattern 113 The side walls extend. For example, the top surface of the cell gate insulating layer 111 may be covered by the cell gate capping pattern 113 .

The cell gate capping pattern 113 may include, for example, silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), silicon oxide (SiO ₂ ), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or at least one of its combinations.

Although the upper surface of the cell gate capping pattern 113 is coplanar with the upper surface of the cell device isolation layer 105 in FIG. 4 , the present disclosure is not limited thereto.

An impurity doped region may be formed on at least one side of each unit gate structure 110 . The impurity doped region may be the source/drain region of the transistor. Impurity doped regions may be formed on each storage connection region 103b and each bit line connection region 103a in FIG. 2 .

In FIG. 2 , when the transistors including each word line WL, the bit line connection area 103 a adjacent to the word line WL, and the storage connection area 103 b adjacent to the word line WL are NMOS transistors, the storage connection area 103b and the bit line connection region 103a may each be doped with n-type impurities. The n-type impurity may include, for example, at least one of phosphorus (P), arsenic (As), antimony (Sb), or bismuth (Bi). When the transistors including each word line WL, the bit line connection area 103a adjacent to the word line WL, and the storage connection area 103b adjacent to the word line WL are PMOS transistors, the storage connection area 103b and the bit line The connection regions 103a may each be doped with p-type impurities, such as boron (B), aluminum (Al), or gallium (Ga).

The bit line contact 146 and the storage contact 120 may be disposed in the contact recess 120R. The contact recess 120R may be formed in the substrate 100 and the cell device isolation layer 105.

In the cross-sectional view, each contact groove 120R may be formed above one bit line connection area 103a and two storage connection areas 103b. For example, in FIG. 5 , the bit line connection area 103a may be disposed between the first storage connection area 103b_1 and the second storage connection area 103b_2. The bit line connection area 103a, the first storage connection area 103b_1 and the second storage connection area 103b_2 may be included in different cell active areas ACT in FIG. 1 respectively. That is, the bit line connection area 103a, the first storage connection area 103b_1 and the second storage connection area 103b_2 exposed by one contact groove 120R can be respectively included in the first cell active area ACT divided by the unit device isolation layer 105 Go to the active area ACT of the third unit. For example, the contact groove 120R can be in the first storage connection area 103b_1 of the first cell active area ACT, the bit line connection area 103a of the second cell active area ACT, and the second storage connection area of the third cell active area. Widely open on 103b_2. In other words, one contact groove 120R can be widely opened above three adjacent cell active areas ACT to accommodate one bit line contact 146 and two storage contacts 120 .

The bit line contact 146 is disposed on the substrate 100. The bit line contact 146 may be formed between the cell conductive line 140 and the substrate 100.

The bit line contact 146 may be formed between the bit line connection region 103a of the cell active region ACT and each cell conductive line 140. The bit line contact 146 connects the cell conductive line 140 to the substrate 100. The bit line contact 146 may be connected to the bit line connection region 103a. For example, the bit line contact 146 may connect the cell conductive line 140 to the bit line connection region 103a of the cell active region ACT.

Bit line contact 146 may include an upper surface 146US of the bit line contact connected to cell conductive line 140 . Although the width of the bit line contact 146 in the first direction DR1 may be equal to the width of the unit conductive line 140 in the first direction DR1 , the present disclosure is not limited thereto. In the cross-sectional view, the upper surface 146US of the bit line contact is shown as a flat surface, but the present disclosure is not limited thereto.

The bit line contact 146 includes a bottom surface 146BS connected to the substrate 100. In the cross-sectional view, the bottom surface 146BS of the bit line contact is shown as a flat surface, but the present disclosure is not limited thereto. The bit line contact 146 may correspond to the direct contact DC of FIG. 1 .

The storage contacts 120 may be disposed on the substrate 100 . Storage contact 120 may be disposed on an opposite side of bit line contact 146 in contact recess 120R.

The storage contact 120 can be connected to the storage connection area 103b. Here, the storage contact 120 may correspond to the embedded contact BC of FIG. 1 .

The storage contact 120 may include a first storage contact 120_1 and a second storage contact 120_2 disposed in the contact recess 120R. The bit line contact 146 may be disposed between the first storage contact 120_1 and the second storage contact 120_2. The first storage contact 120_1 may be connected to the first storage connection area 103b_1. The second storage contact 120_2 may be connected to the second storage connection area 103b_2. For example, the first storage contact 120_1, the second storage contact 120_2, and the bit line contact 146 may all be disposed in the contact recess 120R.

In the cross-sectional views shown in FIG3 and FIG5 , the upper surface 120US of the storage contact may include a flat portion and a concave portion. The bit line spacer 150 described below may cover the flat portion of the upper surface 120US of the storage contact. The storage pad 160 described below may cover the concave portion of the upper surface 120US of the storage contact.

Unlike in the figures, the bit line spacer 150 may not cover at least a portion of the upper surface 120US of the storage contact. In this case, the entire upper surface 120US of the storage contact may be concave in cross-sectional view. Alternatively, the upper surface 120US of the storage contacts may include only a flat portion, and in this case, the storage liner 160 may cover part or all of a flat portion of the upper surface 120US of the storage contacts.

The bit line contact 146 may include the same material as the storage contact 120. The bit line contact 146 and the storage contact 120 are formed at the same level. Here, the expression "same level" means that the bit line contact 146 and the storage contact 120 are formed by the same manufacturing process.

Bit line contacts 146 and storage contacts 120 may include conductive materials, such as metals. Conductive materials may include, but are not limited to, metals, metal alloys, metal nitrides, metal carbonitrides, or the like, for example.

3 and 5 , the storage contact silicide layer 120_MS may be disposed between the storage contact 120 and the substrate 100. The bit line contact silicide layer 146_MS may be disposed between the bit line contact 146 and the substrate 100.

The storage contact silicide layer 120_MS and the bit line contact silicide layer 146_MS include the same material. The storage contact silicide layer 120_MS and the bit line contact silicide layer 146_MS include a metal silicide material. For example, when the bit line contact 146 and the storage contact 120 include a conductive material that is a metal, the metal silicide material of the storage contact silicide layer 120_MS and the bit line contact silicide layer 146_MS can provide a reliable metal semiconductor contact between the substrate 100 and the storage contact 120 and the bit line contact 146.

Bit line contact spacers 147 are disposed in contact recesses 120R. Bit line contact spacers 147 are disposed between bit line contacts 146 and storage contacts 120 . For example, the bit line contact spacer 147 is disposed between the bit line contact 146 and the first storage contact 120_1 and between the bit line contact 146 and the second storage contact 120_2. In the case where two bit line contact spacers 147 are formed in the contact groove 120R, the bit line contact 146 and the storage contact 120 can be reliably separated. Furthermore, with this structural configuration, reliable electrical separation between bit line contacts 146 and storage contacts 120 may be possible even as scaling proceeds further.

The bit line contact spacer 147 may extend along the sidewall 146SW of the bit line contact. The bit line contact spacer 147 extends along the second direction DR2. The bit line contact spacer 147 may contact the bit line contact 146 and the storage contact 120.

Bit line contact spacers 147 electrically isolate bit line contacts 146 from storage contacts 120 . Bit line contact spacers 147 include insulating material. The bit line contact spacer 147 may include, for example, silicon oxycarbonate (SiOC), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), silicon oxide (SiO ₂ ), silicon carbonitride (SiCN), At least one of silicon oxycarbonitride (SiOCN). The bit line contact spacer 147 may be formed as a single layer.

In the cross-sectional views shown in FIGS. 3 and 5 , based on the bottom surface 146BS of the bit line contact, the upper surface 146US of the bit line contact may be flush with or higher than the upper surface 120US of the storage contact. on the upper surface of the storage contact. The height H11 from the bottom surface 146BS of the bit line contact to the upper surface 146US of the bit line contact may be equal to or greater than the height from the bottom surface 146BS of the bit line contact to the upper surface 120US of the storage contact. For example, the height H11 of the bit line contact 146 may be equal to or greater than the height H12 of the storage contact 120 .

When the entire upper surface 120US of the storage contacts is concave when the storage pad 160 is formed, the entire surface 120US of the storage contacts may be concave, unlike in the drawings. In this case, the upper surface 146US of the bitline contact may be higher than the upper surface 120US of the storage contact relative to the bottom surface 146BS of the bitline contact.

The height H11 from the bottom surface 146BS of the bit line contact to the upper surface 146US of the bit line contact may be equal to the height from the bottom surface 146BS of the bit line contact to the upper surface 147US of the bit line contact spacer. The height from the bottom surface 146BS of the bit line contact to the upper surface 120US of the storage contact may be equal to or less than the height from the bottom surface 146BS of the bit line contact to the upper surface 147US of the bit line contact spacer.

The height H13 of the bit line contact spacer 147 may be equal to the height H11 of the bit line contact 146 . The height H13 of the bit line contact spacer 147 may be equal to the height H12 of the storage contact 120 . Alternatively, the height H13 of the bit line contact spacer 147 may be greater than the height H12 of the storage contact 120 .

At the upper surface 100US of the substrate, the width W22 of the first storage contact 120_1 in the first direction DR1 may be equal to the width W23 of the second storage contact 120_2 in the first direction DR1. In the embodiment of the present disclosure, at the upper surface 100US of the substrate, the width W22 of the first storage contact 120_1 in the first direction DR1 may be equal to the width W21 of the bit line contact 146 in the first direction DR1. In the embodiment of the present disclosure, at the upper surface 100US of the substrate, the width W22 of the first storage contact 120_1 in the first direction DR1 may be greater than the width W21 of the bit line contact 146 in the first direction DR1.

The width W22 of the storage contact 120_1 is compared with the width W21 of the bit line contact 146 on the upper surface 100US of the substrate, but the present disclosure is not limited thereto. The width W22 of the first storage contact 120_1 can be compared with the width W21 of the bit line contact 146 on the upper surface 130US of the cell insulation layer (to be described below).

In the cross-sectional view, at least one of the opposite side walls of the first storage contact 120_1 in the first direction DR1 may not extend to the upper surface 130US of the cell insulating layer. In this case, the width W22 of the first storage contact 120_1 may be measured by virtually extending the side wall of the first storage contact 120_1 to the upper surface 130US of the cell insulating layer.

Each bit line structure 140ST may include unit conductive lines 140, unit line capping layers 144, and bit line spacers 150.

The cell conductive line 140 may be disposed on the substrate 100 and the cell device isolation layer 105 in which the cell gate structure 110 is formed. The cell conductive line 140 may extend in the second direction DR2. The cell conductive line 140 is disposed on the bit line contact 146. The bottom surface 140BS of the cell conductive line and the upper surface 146US of the bit line contact.

The cell conductive line 140 may intersect the cell device isolation layer 105 and the cell active region ACT defined by the cell device isolation layer 105. For example, the cell conductive line 140 may intersect the cell active region ACT at the bit line connection region 103a. The bit line contact 146 may be formed between the bit line connection region 103a of the cell active region ACT and the cell conductive line 140. The cell conductive line 140 may be formed to intersect the cell gate structure 110. Here, the cell conductive line 140 may correspond to the bit line BL. For example, the cell conductive line 140 may be the bit line BL of FIG. 1 .

The unit conductive line 140 may include, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a two-dimensional (2D) material, a metal, or a metal alloy. In the semiconductor memory device according to embodiments of the present disclosure, the 2D material may be a metal material and/or a semiconductor material. 2D materials may include 2D allotropes or 2D compounds, and may include, but are not limited to, graphene, molybdenum disulfide (MoS ₂ ), molybdenum diselenide (MoSe ₂ ), tungsten diselenide (WSe ₂ ), or 2D compounds. At least one of tungsten sulfide (WS ₂ ). That is, since the above-mentioned 2D materials are listed by way of examples only, the 2D materials that may be included in the semiconductor memory device of the present disclosure are not limited by the above-mentioned materials.

Unit conductive line 140 is shown as a single layer. However, this is only for ease of description, and the present disclosure is not limited thereto. For example, unlike in the figures, the unit conductive line 140 may include multiple conductive layers in which conductive materials are stacked.

In the semiconductor memory device according to the embodiment of the present disclosure, the width W11 of the bottom surface 140BS of the cell conductive line in the first direction DR1 may be equal to the width W12 of the upper surface 146US of the bit line contact in the first direction DR1.

The unit conductive line 140 may include a width center line 140_WCL. The bit line contact 146 may include a width center line 146_WCL. For example, in the unit conductive line 140, the width center line 140_WCL of the unit conductive line may be a virtual line extending from the center of the bottom surface 140BS of the unit conductive line in the fourth direction DR4. The center of the bottom surface 140BS of the unit conductive line may be a point that equally divides the width W11 of the bottom surface 140BS of the unit conductive line in the first direction DR1.

In the semiconductor memory device according to the embodiment of the present disclosure, the width center line 140_WCL of the cell conductive line may be aligned with the width center line 146_WCL of the bit line contact in the fourth direction DR4. In other words, the width center line 146_WCL of the bit line contact may pass through the center of the bottom surface 140BS of the cell conductive line.

In the cross-sectional views illustrated in FIGS. 3 and 5 , the entire bottom surface 140BS of the cell conductive line may be in contact with the entire upper surface 146US of the bit line contact. The bottom surface 140BS of the cell conductive line may not be in contact with the upper surface 147US of the bit line contact spacer.

The cell line capping layer 144 may be disposed on the cell conductive line 140 . The unit line capping layer 144 may extend along the upper surface of the unit conductive line 140 in the second direction DR2. The unit line capping layer 144 may include, for example, at least one of silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), silicon carbonitride (SiCN), or silicon oxycarbonitride (SiOCN).

In the semiconductor memory device according to the embodiment of the present disclosure, the cell line capping layer 144 may include a silicon nitride (Si ₃ N ₄ ) layer. The cell line capping layer 144 is shown as a single layer, but the present disclosure is not limited thereto.

The bit line spacers 150 may be disposed on the side walls 140SW of the cell conductive lines and the side walls of the cell line capping layer 144 . The bit line spacers 150 may extend in the second direction DR2.

The bit line spacers 150 extend along the side walls 140SW of the cell conductive lines and the side walls of the cell line capping layer 144 . The bit line spacer 150 may contact the sidewalls 140SW of the cell conductive lines and the sidewalls of the cell line capping layer 144 .

The bit line spacers 150 are disposed on the upper surface 147US of the bit line contact spacers. At least one of a pair of bit line spacers 150 disposed on the sidewall 140SW of the cell conductive line may contact the upper surface 147US of the bit line contact spacers. For example, some of the bit line spacers 150 may contact the cell insulating layer 130 and may not contact the bit line contact spacers 147.

The bit line spacer 150 does not extend along the side wall 146SW of the bit line contact. The bit line spacer 150 does not contact the side wall 146SW of the bit line contact. For example, the bit line contact spacer 147 does not extend along the side wall 140SW of the cell conductive line.

The bit line spacer 150 may have a multi-layer structure. The bit line spacer 150 includes multiple layers. For example, the bit line spacer 150 may have a three-layer structure and may include a first spacer 151, a second spacer 152, and a third spacer 153, but the present disclosure is not limited thereto. For example, the bit line spacer 150 may be a double-layer structure, or include four or more layers.

The first spacer 151 contacts the sidewall 140SW of the cell conductive line but does not contact the sidewall 146SW of the bit line contact. Each of the layers included in the bit line spacer 150 may include, but is not limited to, at least one of a silicon oxide (SiO ₂ ) layer, a silicon nitride (Si ₃ N ₄ ) layer, a silicon oxynitride (SiON) layer, a silicon oxycarbon nitride (SiOCN) layer, or air.

The cell insulation layer 130 may be formed on the substrate 100 and the cell device isolation layer 105 . For example, the cell insulation layer 130 may be formed on the substrate 100 in which the bit line contacts 146 and the storage contacts 120 are not formed, and formed on the upper surface of the cell device isolation layer 105 . The unit insulation layer 130 may be formed between the substrate 100 and the unit conductive lines 140 and between the unit device isolation layer 105 and the unit conductive lines 140 . Bit line spacers 150 are disposed on the upper surface 130US of the cell insulation layer.

The unit insulation layer 130 may be a single layer. However, as shown, the unit insulating layer 130 may be a multi-layer including a first unit insulating layer 131 , a second unit insulating layer 132 , and a third unit insulating layer 133 . For example, the first unit insulating layer 131 may include a silicon oxide (SiO ₂ ) layer, the second unit insulating layer 132 may include a silicon nitride (Si ₃ N ₄ ) layer, and the third unit insulating layer 133 may include silicon oxide (SiO ₂ ) layer. However, the disclosure is not limited thereto. Different from the figures, the unit insulating layer 130 may be a double layer including a silicon oxide (SiO ₂ ) layer and a silicon nitride (Si ₃ N ₄ ) layer, but the disclosure is not limited thereto.

In the cross-sectional views shown in FIGS. 3 and 5 , the upper surface 130US of the cell insulating layer may be coplanar with the upper surface 147US of the bit line contact spacer. The height from the bottom surface 146BS of the bit line contact to the upper surface 130US of the cell insulating layer may be equal to the height from the bottom surface 146BS of the bit line contact to the upper surface 146US of the bit line contact. The height from the bottom surface 146BS of the bit line contact to the upper surface 130US of the cell insulating layer may be equal to or greater than the height from the bottom surface 146BS of the bit line contact to the upper surface 120US of the storage contact.

In the cross-sectional views shown in FIGS. 3 and 5 , the unit conductive lines 140 may include first unit conductive lines 140_1 on the bit line contacts and second unit conductive lines 140_2 on the cell insulating layer 130 . For example, based on the bottom surface 146BS of the bit line contact, the bottom surface of the first unit conductive line 140_1 may be located at the same height as the bottom surface of the second unit conductive line 140_2. The height from the bottom surface 146BS of the bit line contact to the bottom surface of the first unit conductive line 140_1 may be equal to the height from the bottom surface 146BS of the bit line contact to the bottom surface of the second unit conductive line 140_2.

The gate pattern 170 may be disposed on the substrate 100 and the cell device isolation layer 105. The gate pattern 170 may be formed to overlap with the cell gate structure 110 formed in the substrate 100 and the cell device isolation layer 105. The gate pattern 170 may be formed on the upper surface 130US of the cell insulation layer above the cell gate structure 110.

The gate pattern 170 may be disposed between the bit line structures 140ST extending in the second direction DR2. The gate pattern 170 may include, for example, at least one of silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or a combination thereof.

Storage pads 160 are formed on storage contacts 120 . Storage pad 160 may be electrically connected to storage contacts 120 . The storage pad 160 is connected to the storage connection area 103b of the cell active area ACT via the storage contact 120. Here, the storage pad 160 may correspond to the landing pad LP of FIG. 1 .

The storage pad 160 may extend down along the bit line spacer 150 to the storage contact 120. The bit line spacer 150 is disposed between the storage pad 160 and the cell conductive line 140. For example, the storage pad 160 may be electrically insulated from the cell conductive line 140 by the bit line spacer 150.

A height H14 from the bottom surface 146BS of the bit line contact to the lowest portion of the storage pad 160 may be smaller than a height H11 from the bottom surface 146BS of the bit line contact to the bottom surface 140BS of the cell conductive line. Based on the bottom surface 146BS of the bit line contact, the lowest portion of the storage pad 160 may be lower than the upper surface 147US of the bit line contact spacer.

The storage pad 160 may partially overlap an upper surface of the bit line structure 140ST. The storage pad 160 may include a pad barrier layer 160a and a pad filling layer 160b. The pad barrier layer 160a and the pad filling layer 160b may each include a conductive material including metal.

The pad separation insulating layer 180 may be formed on the storage pad 160 and the bit line structure 140ST. For example, the pad separation insulation layer 180 may be disposed on the unit line capping layer 144 . Pad separation insulation layer 180 may define each of storage pads 160 that are spaced apart from each other. The liner separation insulation layer 180 may not cover the upper surface 160US of the storage liner. For example, the height of the upper surface of the storage pad 160US relative to the upper surface of the substrate 100US may be equal to the height of the upper surface of the pad separation insulating layer 180 .

The pad separation insulating layer 180 may include an insulating material that electrically isolates the storage pads 160 from each other. For example, the pad separation insulating layer 180 may include at least one of a silicon oxide (SiO ₂ ) layer, a silicon nitride (Si ₃ N ₄ ) layer, a silicon oxynitride (SiON) layer, or a silicon oxycarbon nitride (SiOCN) layer.

The etch stop layer 165 may be formed on the upper surface 160US of the storage pad and the upper surface of the pad separation insulating layer 180. The etch stop layer 185 may include, for example, at least one of silicon _nitride ( _Si3N4 ), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), or silicon boron nitride (SiBN).

The information storage portion 190 may be disposed on the storage pad 160 . Information storage portion 190 may be connected to storage pad 160 . The information storage portion 190 may be in contact with the storage pad 160. A portion of the information storage portion 190 may be disposed in the etch stop layer 165 .

The information storage portion 190 may include, for example, a capacitor, but the present disclosure is not limited thereto. The information storage portion 190 includes a lower electrode 191, a capacitor dielectric layer 192, and an upper electrode 193. For example, the upper electrode 193 may be a plate upper electrode having a plate form. The information storage portion 190 may store charge in the capacitor dielectric layer 192 using a potential difference generated between the lower electrode 191 and the upper electrode 193.

The lower electrode 191 may be disposed on the storage pad 160 . Each of the lower electrodes 191 may have a columnar shape, for example. However, the disclosure is not limited thereto. For example, the lower electrode 210 may have a cylindrical shape or other suitable shape.

The capacitor dielectric layer 192 is disposed on the lower electrode 191. The capacitor dielectric layer 192 may be formed along the contour of the lower electrode 191. For example, the capacitor dielectric layer 192 may be formed along the upper side and a portion of the side surface of the lower electrode 191, and may be formed along the upper side of the etch stop layer 165. The upper electrode 193 is disposed on the capacitor dielectric layer 192. The upper electrode 193 may cover the outer sidewall of the lower electrode 191. The upper electrode 193 is shown as a single layer. However, this is only for ease of description, and the present disclosure is not limited thereto.

The lower electrode 191 and the upper electrode 193 may each include, but are not limited to, doped semiconductor materials, conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), tungsten nitride (WN). ) or the like), metals (such as ruthenium (Ru), iridium (Ir), titanium (Ti), tantalum (Ta), or the like) or conductive metal oxides (such as iridium oxide (IrO _x ), niobium oxide ( NbO _x ) or similar).

The capacitor dielectric layer 192 may include, but is not limited to, one of silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), a high-k material, or a combination thereof. According to the semiconductor memory device of the embodiment of the present disclosure, the capacitor dielectric layer 192 may have a stacked film structure in which zirconium oxide (ZrO ₂ ), aluminum oxide (Al ₂ O ₃ ) and zirconium oxide (ZrO ₂ ) are stacked in sequence. In the semiconductor memory device of the embodiment of the present disclosure, the capacitor dielectric layer 192 may include a dielectric layer containing halogen (Hf). In the semiconductor memory device according to the embodiment of the present disclosure, the capacitor dielectric layer 192 may have a stacked film structure of a ferroelectric material layer and a paraelectric material layer.

6 and 7 are views for describing a semiconductor memory device according to an embodiment of the present disclosure. For ease of description, the differences from the embodiment of FIGS. 1 to 5 will be mainly described. For reference, FIG. 7 is an enlarged view of a portion P of FIG. 6 .

Referring to FIGS. 6 and 7 , in the semiconductor memory device according to the embodiment of the present disclosure, the width W12 of the upper surface 146US of the bit line contact in the first direction DR1 is smaller than the width W12 of the bottom surface 140BS of the unit conductive line in the first direction DR1 . Width W11 in direction DR1.

Since the width center line 140_WCL of the cell conductive line is aligned with the width center line 146_WCL of the bit line contact in the fourth direction DR4, the entire upper surface 146US of the bit line contact can contact the bottom surface 140BS of the cell conductive line. On the contrary, a portion of the bottom surface 140BS of the cell conductive line does not contact the upper surface 146US of the bit line contact.

The upper surface 147US of the bit line contact spacer contacts the bottom surface 140BS of the cell conductive line. The upper surface 147US of the bit line contact spacer contacts the portion of the bottom surface 140BS of the cell conductive line that is not in contact with the upper surface 146US of the bit line contact.

At the upper surface 100US of the substrate, the width W22 of the first storage contact 120_1 in the first direction DR1 is greater than or equal to the width W21 of the bit line contact 146 in the first direction DR1. The width W23 of the second storage contact 120_2 in the first direction DR1 may be greater than or equal to the width W21 of the bit line contact 146 in the first direction DR1.

8 and 9 are views for describing a semiconductor memory device according to embodiments of the present disclosure. For ease of description, differences from the embodiment of FIGS. 1 to 5 will be mainly described. For reference, FIG. 9 is an enlarged view of part P of FIG. 8 .

Referring to FIGS. 8 and 9 , in the semiconductor memory device according to the embodiment of the present disclosure, the width center line 140_WCL of the cell conductive line is not aligned with the width center line 146_WCL of the bit line contact in the fourth direction DR4.

Since the width center line 140_WCL of the unit conductive line is not aligned with the width center line 146_WCL of the bit line contact in the fourth direction DR4, the bottom surface 140BS of the unit conductive line may be aligned with the upper surface of the bit line contact spacer 147US contact.

Different from the figure, the width W12 of the upper surface 146US of the bit line contact in the first direction DR1 may be smaller than the width W11 of the bottom surface 140BS of the cell conductive line in the first direction DR1.

At the upper surface 100US of the substrate, the width W22 of the first storage contact 120_1 is greater than the width W23 of the second storage contact 120_2. At the upper surface 100US of the substrate, the width W22 of the first storage contact 120_1 is greater than the width W21 of the bit line contact 146. In the embodiment of the present disclosure, the width W23 of the second storage contact 120_2 may be greater than the width W21 of the bit line contact 146 at the upper surface 100US of the substrate. In the embodiment of the present disclosure, the width W23 of the second storage contact 120_2 may be equal to the width W21 of the bit line contact 146. In the embodiment of the present disclosure, the width W23 of the second storage contact 120_2 may be smaller than the width W21 of the bit line contact 146.

10 to 14 are views each used to describe a semiconductor memory device according to an embodiment of the present disclosure. FIG. 15 is a view used to describe a semiconductor memory device according to an embodiment of the present disclosure. For ease of description, the difference from the embodiment of FIGS. 1 to 5 will be mainly described. For reference purposes, FIGS. 10 to 14 are enlarged views of a portion P of FIG. 3 .

10 and 11 , in the semiconductor memory device according to the embodiment of the present disclosure, the height H13 of the bit line contact spacer 147 may be smaller than the height H12 of the storage contact 120 .

In the cross-sectional view, the lowermost portion of the storage contact 120 is lower than the bottom surface of the bit line contact spacer 147 relative to the upper surface 130US of the cell insulation layer.

In FIG10 , the storage contact 120 may include a first portion 120_A overlapping the storage connection region 103b in the fourth direction DR4 and a second portion 120_B overlapping the cell device isolation layer 105 in the fourth direction DR4. The height H12 of the storage contact 120 may be the height of the second portion 120_B of the storage contact. The height of the second portion 120_B of the storage contact is greater than the height of the first portion 120_A of the storage contact.

At the boundary between the first portion 120_A of the storage contact and the second portion 120_B of the storage contact, the bottom surface of the storage contact 120 may change discontinuously.

11, the bottom surface 146BS of the bit line contact may have a convex shape. The bottom surface of the storage contact 120 may have a convex shape similar to the bottom surface 146BS of the bit line contact.

At the boundary between the substrate 100 and the cell device isolation layer 105, the bottom surface of the storage contact 120 may continuously change.

12 and 13 , in the semiconductor memory device according to the embodiment of the present disclosure, the storage contact silicide layer 120_MS (see FIG. 5 ) is not disposed between the storage contact 120 and the substrate 100. The bit line contact silicide layer 146_MS (see FIG. 5 ) is not disposed between the bit line contact 146 and the substrate 100.

The bit line contact 146 and the storage contact 120 may include, for example, a semiconductor material doped with impurities. In other words, since the bit line contact 146 and the storage contact 120 may include a semiconductor material doped with impurities that do not contain metal, it is not necessary to have a metal silicide material in the interface to provide a reliable metal semiconductor contact between the substrate 100 and the storage contact 120 and the bit line contact 146.

In FIG. 12 , the storage pad 160 may include a pad barrier layer 160 a and a pad filling layer 160 b each including a conductive material including metal.

In Fig. 13, the storage pad 160 may include, for example, a semiconductor material doped with impurities. For example, in Fig. 13, the storage pad 160 may be formed as a single layer and does not include the pad barrier layer 160a and the pad filling layer 160b.

14 , in the semiconductor memory device according to an embodiment of the present disclosure, the upper surface 120US of the storage contact may be flat.

The upper surface 120US of the storage contact may be coplanar with the upper surface 130US of the cell insulation layer.

15 , in the semiconductor memory device according to an embodiment of the present disclosure, the lower electrodes 191 may each have a cylindrical shape.

The lower electrode 191 may include a bottom portion extending along the upper surface 160US of the storage pad and a sidewall portion extending from the bottom portion in the fourth direction DR4.

16 to 40 are views illustrating intermediate stages of fabrication provided to explain a method of fabricating a semiconductor memory device according to embodiments of the present disclosure. In the description of the manufacturing method, repeated contents of the contents explained using FIGS. 1 to 15 are briefly explained or omitted.

For reference, Figures 17 and 18 are cross-sectional views taken along line A-A and line B-B, respectively.

16 to 18 , a cell device isolation layer 105 may be formed in a substrate 100 .

The substrate 100 may include a cell active area ACT defined by a cell device isolation layer 105. The cell active area ACT may have a strip shape extending in the third direction DR3, and the strip shape may be inclined at a predetermined angle relative to the first direction DR1 or the second direction DR2. In the embodiment of the present disclosure, the predetermined angle may be in the range of about 10° to about 80°.

Referring to FIGS. 19 and 21 , the cell gate electrode 112 is formed in the substrate 100 and the cell device isolation layer 105 .

The cell gate electrodes 112 may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2.

The cell gate structures 110 extending in the first direction DR1 are formed in the substrate 100 and the cell device isolation layer 105. Each of the cell gate structures 110 may include a cell gate trench 115, a cell gate insulating layer 111, a cell gate electrode 112, a cell gate capping pattern 113, and a cell gate capping conductive layer 114.

The cell gate electrode 112 intersects the cell active region. The cell active area ACT can be divided into a bit line connection area 103a and a storage connection area 103b by the cell gate electrode 112.

The cell active area ACT may include a bit line connection area 103a located in a middle portion of the cell active area ACT and storage connection areas 103b located at opposite ends of the cell active area ACT.

Referring to FIGS. 22 to 24 , the unit insulation layer 130 may be formed on the substrate 100 and the unit device isolation layer 105 . The unit insulating layer 130 may be a multi-layer including a first unit insulating layer 131, a second unit insulating layer 132, and a third unit insulating layer 133 stacked in sequence.

The pre-mask layer 50 is formed on the cell insulating layer 130. The pre-mask layer 50 may include, but is not limited to, polycrystalline silicon (p-Si), amorphous silicon (a-Si), polycrystalline silicon germanium (p-SiGe), or amorphous silicon germanium (a-SiGe).

The first mask patterns 50_MASK are formed on the pre-mask layer 50. Each of the first mask patterns 50_MASK may be in a linear shape extending in the first direction DR1. The first mask patterns 50_MASK may overlap with the cell gate structure 110 in the fourth direction DR4. The first mask patterns 50_MASK may each include, but are not limited to, for example, an amorphous carbon layer (ACL).

Referring to FIGS. 22 to 27 , the pre-mask layer 50 may be partially removed using the first mask pattern 50_MASK as a mask.

The first contact mask pattern 55 may be formed on the unit insulation layer 130 via the patterned pre-mask layer 50 . Each first contact pattern 55 may have a line shape extending in the first direction DR1. The first contact mask pattern 55 may overlap with the cell gate structure 110 in the fourth direction DR4.

After the first contact mask pattern 55 is formed, the first mask pattern 50_MASK is removed.

Thereafter, a filling mask pattern 56 may be formed between each pair of first contact mask patterns 55 adjacent to each other in the second direction DR2. The filling mask pattern 56 may be formed on the cell insulation layer 130. The filling mask pattern 56 may be formed between each pair of cell gate structures 110 adjacent to each other in the second direction DR2. The filling mask pattern 56 may include, but is not limited to, for example, silicon oxide (SiO ₂ ).

Referring to FIGS. 28 and 29 , the second mask pattern 60_MASK is formed on the first contact mask pattern 55 and the filling mask pattern 56 .

Each second mask pattern 60_MASK may have a line shape extending in the fifth direction. The fifth direction may be located between the first direction DR1 and the third direction DR3. The second mask pattern 60_MASK may cover the bit line connection area 103a. The second mask pattern 60_MASK may overlap with the bit line connection area 103a of the cell active area ACT in the fourth direction DR4.

The second mask pattern 60_MASK may include but is not limited to a spin-on-hard mask (SOH).

Different from the drawings, the second mask pattern 60_MASK may extend in the third direction DR3 in which the cell active area ACT extends.

Referring to FIGS. 28 to 31 , the fill mask pattern 56 may be partially removed using the second mask pattern 60_MASK as a mask.

The mask filling pattern 56P may be formed on the cell insulating layer 130 by partially removing the filling mask pattern 56. The cell insulating layer 130 may be exposed when the mask filling pattern 56P is formed. When the mask filling pattern 56P is formed, the first contact mask pattern 55 remains without being removed.

The mask fill pattern 56P covers the bit line connection area 103a. In addition, the mask fill pattern 56P may partially cover the storage connection region 103b located at the opposite side of the bit line connection region 103a.

After the mask filling pattern 56P is formed, the second mask pattern 60_MASK is removed.

32 and 33 , the second contact mask pattern 60 is formed on the exposed cell insulating layer 130.

The second contact mask pattern 60 is formed between the first contact mask patterns 55 adjacent to each other in the second direction DR2. The second contact mask pattern 60 is formed between the mask filling patterns 56P adjacent to each other in the first direction DR1.

The second contact mask pattern 60 may include, but is not limited to, polycrystalline silicon (p-Si), amorphous silicon (a-Si), polycrystalline silicon germanium (p-SiGe), or amorphous silicon germanium (a-SiGe).

When the second contact mask pattern 60 is formed, the contact mask pattern 70 is formed on the substrate 100. The contact mask pattern 70 may be formed on the cell insulating layer 130. The contact mask pattern 70 may include the first contact mask pattern 55 and the second contact mask pattern 60.

The contact mask pattern 70 may surround the mask filling pattern 56P arranged in an island shape. In other words, the mask filling pattern 56P may be arranged in the contact mask pattern 70.

Referring to FIGS. 32 to 34 , contact grooves 120R are masked and formed in the substrate 100 and the unit device isolation layer 105 using the contact mask pattern 70 .

The contact grooves 120R may be formed above the bit line connection region 103a and the storage connection region 103b. In the cross-sectional view shown in FIG34, each contact groove 120R may be formed above one bit line connection region 103a and two storage connection regions 103b.

When forming the contact groove 120R, the contact mask pattern 70 and the mask filling pattern 56P may be removed, but the present disclosure is not limited thereto. In addition, when forming the contact groove 120R, the third cell insulation layer 133 of the cell insulation layer 130 may be partially removed, but the present disclosure is not limited thereto. Different from the figure, when forming the contact groove 120R, the third cell insulation layer 133 of the cell insulation layer 130 may be removed.

Referring to FIGS. 35 and 36 , a spacer layer 147L may be formed on the substrate 100 .

Spacer layer 147L may fill contact grooves 120R and may cover cell insulation layer 130.

The spacer layer 147L may include, for example, at least one of silicon oxycarbide (SiOC), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), silicon oxide (SiO ₂ ), silicon carbonitride (SiCN), and silicon oxycarbonitride (SiOCN).

The spacer mask pattern 147_MASK is formed on the spacer layer 147L. The spacer mask pattern 147_MASK may be in a line shape extending in the second direction DR2. A plurality of bit line connection areas 103a may be located between a pair of spacer mask patterns 147_MASK.

The spacer mask patterns 147_MASK may each include, but are not limited to, for example, an amorphous carbon layer (ACL).

35 to 37 , the spacer layer 147L may be patterned using a spacer mask pattern 147_MASK as a mask.

The bit line contact spacers 147 may be formed by patterning the spacer layer 147L. Some of the bit line contact spacers 147 may be formed in the contact grooves 120R. The bit line contact spacers 147 may extend in the second direction DR2.

The bit line contact spacer 147 can divide the contact groove 120R into a first area 120R_1 and a second area 120R_2. The first area 120R_1 of the contact groove may be defined on the bit line connection area 103a. The second area 120R_2 of the contact groove may be defined on the storage connection area 103b.

In the embodiment of the present disclosure, the storage contact silicide layer 120_MS and the bit line contact silicide layer 146_MS may be formed before forming the spacer layer 147L.

In the embodiment of the present disclosure, after the bit line contact spacers 147 are formed, the storage contact silicon layer 120_MS and the bit line contact silicon layer 146_MS may be formed.

Referring to FIGS. 37 and 38 , a contact conductive layer 146L may be formed on the substrate 100 .

The contact conductive layer 146L may fill the first region 120R_1 and the second region 120R_2 of the contact groove. The contact conductive layer 146L may be formed on the upper surface of the cell insulating layer 130. The contact conductive layer 146L may cover the bit line contact spacer 147.

The contact conductive layer 146L may be formed using, for example, chemical vapor deposition (CVD), but the present disclosure is not limited thereto.

Referring to FIG. 39 , bit line contacts 146 and storage contacts 120 are formed in contact grooves 120R.

The bit line contact 146 may fill the first region 120R_1 of the contact cavity. The storage contact 120 may fill the second region 120R_2 of the contact cavity.

Bit line contacts 146 and storage contacts 120 may be formed by partially removing contact conductive layer 146L. Therefore, bit line contact 146 and storage contact 120 may include the same material. In addition, the bit line contacts 146 and the storage contacts 120 may be formed at the same level. Since the bit line contacts 146 and the storage contacts 120 are formed simultaneously, the present disclosure can use fewer etching steps and/or processes than are typically used to form the bit line contacts and storage contacts sequentially and separately. Or more simplified etching steps. When the bit line contact 146 and the storage contact 120 are formed, the bit line contact spacer 147 protrudes upwardly from the upper surface of the cell insulation layer 130 . That is, since the bit line contact spacer 147 protruding upwardly from the upper surface of the cell insulation layer 130 is removed, the bit line contact spacer 147 may be disposed within the contact groove 120R. By first forming the bit line contact spacers 147 in the contact recess 120R and then forming the self-aligned bit line contacts 146 via the bit line contact spacers 147 in the contact recess 120R and The storage contact 120, the bit line contact 146 and the storage contact 120 can be reliably separated in the contact groove 120R.

Referring to FIG. 40 , unit conductive lines 140 and unit line capping layers 144 may be formed on bit line contacts 146 . The unit conductive line 140 extends in the second direction DR2.

Thereafter, the bit line spacers 150 are formed on the side walls of the cell conductive lines 140 and the side walls of the cell line capping layer 144 . The bit line spacers 150 may include first spacers 151, second spacers 152, and third spacers 153. The third spacer 153 may cover the upper surface of the storage contact 120 .

3 , the storage pad 160 is formed on the storage contact 120. When the storage pad 160 is formed, the third spacer 153 covering the upper surface of the storage contact 120 is removed. The information storage portion 190 is formed on the bit line spacer 150. The information storage portion 190 is formed on the storage pad 160 and is connected to the storage contact 120 via the storage pad 160.

41 to 44 are views each for describing a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure. For reference, FIGS. 41 to 44 are views for describing the contact mask pattern 70 as shown in FIG. 32 .

In FIG. 41, the space surrounded by the contact mask pattern 70 may have a parallelogram shape with rounded corners. The space enclosed by contact mask pattern 70 may correspond to mask fill pattern 56P of FIG. 32 .

In FIG. 42 , the space enclosed by the contact mask pattern 70 may have an elliptical shape.

In Fig. 43, the space enclosed by the joint mask pattern 70 may have a rectangular shape. Different from the figure, the space enclosed by the joint mask pattern 70 may have a rectangular shape with rounded corners.

44, a space surrounded by the joint mask pattern 70 may have a parallelogram shape. A portion of the joint mask pattern 70 corresponding to the second joint mask pattern 60 of FIG. 32 may be tilted in a sixth direction different from the direction of the second joint mask pattern 60 of FIG.

In summary, those skilled in the art will appreciate that many changes and modifications may be made to the preferred embodiments without departing from the spirit and scope of the present disclosure as defined in the appended claims. Therefore, the disclosed preferred embodiments of the present disclosure are used in a general and descriptive sense only and not for limiting purposes.

50: Pre-mask layer 50_MASK: first mask pattern 55: First contact mask pattern 56: Fill mask pattern 56P: Mask fill pattern 60: Second contact mask pattern 60_MASK: Second mask pattern 70: Contact mask pattern 100:Base 100US, 120US, 130US, 146US, 147US, 160US: upper surface 103a: Bit line connection area 103b: Storage connection area 103b_1: First storage connection area 103b_2: Second storage connection area 105:Unit device isolation layer 110: Unit gate structure 111: Unit gate insulation layer 112:Unit gate electrode 113: Unit gate capping pattern 114: Unit gate capping conductive layer 115:Unit gate trench 120:Storage contacts 120R: Contact groove 120_1: First storage contact 120_2: Second storage contact 120_A:Part 1 120_B:Part 2 120_MS: Storage contact silicon layer 120R_1:The first area 120R_2:Second area 130:Unit insulation layer 131: First unit insulation layer 132: Second unit insulation layer 133:Third unit insulation layer 140:Unit conductive wire 140BS, 146BS: bottom surface 140ST: Bit line structure 140SW, 146SW: side wall 140_1: First unit conductive wire 140_2: Second unit conductive wire 140_WCL, 146_WCL: width center line 144:Unit line capping layer 146:Bit line contact 146L:Contact conductive layer 146_MS: Bit line contact silicon layer 147:Bit line contact spacer 147L: Spacer layer 147_MASK: Spacer mask pattern 150:Bit line spacer 151: First spacer 152:Second spacer 153:Third spacer 160:Storage liner 160a: Liner barrier layer 160b: Pad filling layer 165: Etch stop layer 170: Fence Pattern 180: Pad separation insulation layer 185: Etch stop layer 190: Information storage part 191:Lower electrode 192: Capacitor dielectric layer 193: Upper electrode A-A, B-B: line ACT: unit active area BC: Buried contact BL: bit line DC: direct contact DR1: first direction DR2: Second direction DR3: Third direction DR4: The fourth direction H11, H12, H13, H14: height LP: Landing Pad P:part W11, W12, W21, W22, W23: Width WL: word line

The above and other aspects and features of the present disclosure will become more apparent by describing in detail illustrative embodiments thereof with reference to the accompanying drawings, in which: FIG. 1 is a schematic layout diagram of a semiconductor memory device according to an embodiment of the present disclosure. Figure 2 is a layout diagram of only the word lines and active areas of Figure 1. 3 is a cross-sectional view taken along line A-A of FIG. 1 . 4 is a cross-sectional view taken along line B-B of FIG. 1 . FIG. 5 is an enlarged view of part P of FIG. 3 . 6 and 7 are views for describing a semiconductor memory device according to embodiments of the present disclosure. 8 and 9 are views for describing a semiconductor memory device according to embodiments of the present disclosure. 10 to 14 are views each for describing a semiconductor memory device according to embodiments of the present disclosure. FIG. 15 is a view for describing a semiconductor memory device according to an embodiment of the present disclosure. 16 to 40 are views illustrating intermediate stages of fabrication provided to explain a method of fabricating a semiconductor memory device according to embodiments of the present disclosure. 41 to 44 are views each for describing a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure. Because the drawings in FIGS. 1-44 are intended for illustrative purposes, elements in the drawings are not necessarily drawn to scale. For example, some of the elements may be exaggerated or exaggerated for clarity.

100:Base

103a: Bit line connection area

103b: Storage connection area

105:Unit device isolation layer

120: Storage contacts

120R: Contact groove

130:Unit insulation layer

130US, 160US: upper surface

131: First unit insulation layer

132: Second unit insulation layer

133:Third unit insulation layer

140:Unit conductive wire

140ST: Bit line structure

144:Unit line capping layer

146:Bit line contact

147: Bit line contact spacer

150:Bit line spacer

151: First spacer

152: Second spacer

153:Third spacer

160: Storage pad

165: Etch stop layer

180: Pad separation insulation layer

190: Information storage part

191: Lower electrode

192: Capacitor dielectric layer

193: Upper electrode

A-A: Line

DR1: first direction

DR2: Second direction

DR4: The fourth direction

P: Part

Claims (10)

A semiconductor memory device including: a substrate including an active region defined by a device isolation layer; Bit lines are disposed on the substrate and extend in the first direction; A bit line contact disposed between the bit line and the substrate and connecting the bit line to the active region; Bit line spacers extending along the sidewalls of the bit lines; and Bit line contact spacers extend along the side walls of the bit line contacts and do not extend along the side walls of the bit lines. The semiconductor memory device as described in claim 1 further includes: a storage contact disposed on the substrate; and a storage pad disposed on the storage contact, wherein the bit line contact spacer is disposed between the bit line contact and the storage contact. A semiconductor memory device as described in claim 2, wherein based on the bottom surface of the bit line contact, the upper surface of the bit line contact is at the same level as or higher than the level of the upper surface of the storage contact. The semiconductor memory device of claim 2, wherein the height of the bit line contact spacer is less than or equal to the height of the storage contact. The semiconductor memory device of claim 1, wherein the width of the upper surface of the bit line contact in the second direction orthogonal to the first direction is less than or equal to the bottom surface of the bit line. width in the second direction. The semiconductor memory device of claim 1, wherein a height from a bottom surface of the bit line contact to an upper surface of the bit line contact is equal to a height from the bottom of the bit line contact surface to the height of the upper surface of the bit line contact spacer. A semiconductor memory device as described in claim 1, wherein the bit line contact spacer is a single layer, and the bit line spacer is a multi-layer. A semiconductor memory device comprises: a substrate including a first active region, a second active region and a third active region defined by a device isolation layer, wherein the second active region is disposed between the first active region and the third active region; a bit line contact disposed on the substrate and connected to the second active region; a first storage contact disposed on the substrate and connected to the first active region; a second storage contact disposed on the substrate and connected to the third active region; a bit line contact spacer disposed on the substrate and disposed between the bit line contact and the first storage contact and between the bit line contact and the second storage contact; and a bit line disposed on the bit line contact, extending in a first direction and contacting an upper surface of the bit line contact spacer. The semiconductor memory device as described in claim 8 further includes a bit line spacer extending along the side wall of the bit line, wherein the bit line spacer contacts the side wall of the bit line and does not contact the side wall of the bit line contact. A semiconductor memory device including: A substrate including an active region defined by a device isolation layer and extending in a first direction, the active region including a first region and a second region defined at an opposite side of the first region; A word line extending in the substrate and the device isolation layer in a second direction and spanning the first region of the active region and the second region of the active region; A bit line is disposed on the substrate and the device isolation layer, extends in a third direction orthogonal to the second direction, and is connected to the first region of the active region; A bit line contact is disposed between the bit line and the substrate and connected to the bit line, and the upper surface of the bit line contact has a width in the second direction that is smaller than the The width of the bottom surface of the bit line in the second direction; a storage contact disposed on the substrate and connected to a second region of another active region adjacent to the active region; a storage pad positioned over and connected to the storage contact; and A capacitor is disposed on and connected to the storage pad.

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