KR20230014794A - Method for fabricating the semiconductor memory device - Google Patents

Abstract

The present invention is to provide a manufacturing method of a semiconductor memory device capable of improving reliability and performance. The manufacturing method of the semiconductor memory device comprises: forming a trench in a substrate; forming a first free cell gate insulating layer including silicon oxide, along a sidewall and bottom surface of the trench; forming a second free cell gate insulating layer by implanting silicon (Si) ions into the first free cell gate insulating layer; and forming a cell gate insulating layer by performing a curing process on the second free cell gate insulating layer.

Description

Method for fabricating the semiconductor memory device {Method for fabricating the semiconductor memory device}

The present invention relates to a method of manufacturing a semiconductor memory device.

As semiconductor devices become increasingly highly integrated, individual circuit patterns are becoming more miniaturized in order to implement more semiconductor devices in the same area. That is, as the degree of integration of semiconductor devices increases, design rules for components of semiconductor devices are decreasing.

In a highly-scaling semiconductor device, a process of forming a plurality of word lines and a process of forming a plurality of wiring lines and a plurality of buried contacts (BC) interposed therebetween is becoming increasingly complicated and difficult. .

An object to be solved by the present invention is to provide a method of manufacturing a semiconductor memory device capable of improving reliability and performance.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In one aspect of a method of manufacturing a semiconductor memory device of the present invention for solving the above problems, a trench is formed in a substrate, and a first pre-cell gate insulating layer including silicon oxide is formed along sidewalls and bottom surfaces of the trench. forming a second free-cell gate insulating layer by implanting silicon (Si) ions into the first free-cell gate insulating layer, and performing a curing process on the second free-cell gate insulating layer to form a cell gate Including forming an insulating layer.

Another aspect of the method of manufacturing a semiconductor memory device of the present invention for solving the above problems is to provide a substrate including an active region defined by a device isolation film, form a trench extending in a first direction in the substrate and the device isolation film, , A first free-cell gate insulating layer including silicon oxide is formed along sidewalls and a bottom surface of the trench using an atomic layer deposition process (ALD), and silicon (Si) ions are applied to the first free-cell gate insulating layer. A second pre-cell gate insulating layer is formed by injection, a curing process is performed on the second pre-cell gate insulating layer, and a cell gate electrode, a cell gate capping conductive layer and a cell gate capping layer are formed on the second pre-cell gate insulating layer. A cell gate structure is formed by sequentially forming cell gate capping patterns, an active region is divided into a first part of the active region and a second part of the active region by a cell gate electrode, and on a substrate, in a first direction and Forming a bit line structure in another second direction, forming a storage contact on the second portion of the active region, forming a storage pad on the storage contact, and forming a capacitor on the storage pad.

Other specific details of the invention are included in the detailed description and drawings.

1 is a schematic layout for describing a semiconductor memory device according to some embodiments.
2 to 6 are intermediate diagrams for explaining a manufacturing method of the semiconductor memory device of FIG. 1 .
7 is a diagram for describing a semiconductor memory device according to some embodiments.
8 and 9 are schematic layouts of a semiconductor memory device according to some embodiments.
10 is a cross-sectional view taken along line BB of FIG. 9 .
11 is a cross-sectional view taken along line CC of FIG. 9 .
12 is a cross-sectional view taken along line DD of FIG. 9 .

1 is a schematic layout for describing a semiconductor memory device according to some embodiments. 2 to 6 are intermediate diagrams for explaining a manufacturing method of the semiconductor memory device of FIG. 1 . For reference, FIGS. 2 to 6 are cross-sectional views taken along line A-A of FIG. 1 .

Referring to FIG. 1 , a semiconductor memory device according to some embodiments may include a cell device isolation layer 105 . The cell device isolation layer 105 may be formed in the substrate 100 . The cell device isolation layer 105 may have a shallow trench isolation (STI) structure having excellent device isolation characteristics. The cell element isolation layer 105 may define the cell active region ACT within the memory cell region.

The cell element isolation layer 105 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer, but is not limited thereto.

Although the cell element isolation layer 105 is illustrated as being formed of one insulating layer, it is only for convenience of explanation, and is not limited thereto. The cell element isolation layer 105 may be formed of one insulating layer or a plurality of insulating layers.

Referring to FIGS. 1 and 2 , the cell gate trench 115 may be formed in the substrate 100 and the cell device isolation layer 105 . For example, after forming a mask pattern M on the substrate 100 , the substrate 100 may be etched using the mask pattern M as an etching mask to form the cell gate trench 115 . The cell gate trench 115 may extend in the first direction DR1 . The cell gate trench 115 may be formed across the cell device isolation layer 105 and the cell active region ACT defined by the cell device isolation layer 105 .

Referring to FIG. 3 , a first free cell gate insulating layer 111_P1 may be formed on the substrate 100 and the cell device isolation layer 105 . The first free cell gate insulating layer 111_P1 may have a first thickness T1. The first free cell gate insulating layer 111_P1 may be formed using an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. The first free cell gate insulating layer 111_P1 may cover the top surface of the substrate 100 and the sidewall and bottom surface of the cell gate trench 115 . The first free cell gate insulating layer 111_P1 may include silicon oxide.

Referring to FIG. 4 , a second free cell gate insulating layer 111_P2 may be formed by implanting silicon (Si) into the first free cell gate insulating layer 111_P1 using an ion implantation process. Silicon (Si) ions may be implanted into the first free cell gate insulating layer 111_P1 disposed on the cell gate trench 115 . For example, first silicon Si_1 may be injected in a direction perpendicular to the substrate 100 and injected into the first free cell gate insulating layer 111_P1 contacting the bottom surface of the cell gate trench 115 . The second silicon Si_2 may be implanted in a direction oblique to the substrate 100 and implanted into the first pre-cell gate insulating layer 111_P1 contacting the side surface of the cell gate trench 115 . A lattice of silicon oxide in the second free cell gate insulating layer 111_P2 may be distorted by the silicon implantation process. For example, some silicon (Si) atoms may not have electrons to share with oxygen (O) atoms.

Referring to FIG. 5 , the cell gate insulating layer 111 is formed on the second free cell gate insulating layer 111_P2 by using a curing process, and the cell gate electrode 112 and the cell gate capping conductive layer ( 114) can be formed. For example, the curing process may supply radical oxygen and heat to the second free cell gate insulating layer 111_P2. Through the curing process, silicon oxide in the second free cell gate insulating layer 111_P2 may be rearranged. For example, a silicon atom having no electrons shared with an oxygen atom may share electrons with an oxygen atom through the curing process.

The cell gate insulating layer 111 may have a second thickness T2. The second thickness T2 may be greater than the first thickness T1 of the first free cell gate insulating layer 111_P1.

A cell gate electrode 112 may be formed on the cell gate insulating layer 111 . The cell gate electrode 112 may be formed below the cell gate trench 115 to which the cell gate insulating layer 111 is applied.

Although not shown, for example, a conductive material may be deposited on the substrate 100 on which the cell gate insulating layer 111 is formed. In this case, the cell gate trench 115 may be filled with a conductive material. Deposition of the conductive material may be performed using a chemical vapor deposition (CVD) process or the like. The conductive material may include a metal such as tungsten (W), titanium (Ti), or tantalum (Ta). Thereafter, the cell gate electrode 112 may be formed by etching the deposited conductive material. For example, the conductive material may be etched through an etch-back process.

Subsequently, a cell gate capping conductive layer 114 may be formed on the cell gate electrode 112 . Although not shown, for example, polysilicon may be formed on the cell gate electrode 112 and fill the cell gate trench 115 . The polysilicon may be formed using a chemical vapor deposition (CVD) process or the like. The cell gate capping conductive layer 114 may be formed by etching the polysilicon through an etch-back process. In some embodiments, N-type impurities may be doped into the polysilicon.

Referring to FIG. 6 , a cell gate capping pattern 113 may be formed on the cell gate capping conductive layer 114 . The cell gate capping pattern 113 may be formed on the cell gate trench 115 on which the cell gate insulating layer 111 is applied. For example, the cell gate capping pattern 113 may be formed by forming a capping layer on the entire surface of the substrate 100 and then performing a planarization process or the like. The capping pattern 113 may include any one of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer. In this case, a portion of the cell gate insulating layer 111 covering the upper surface of the substrate 100 may be removed together.

Through the planarization process, a cell gate structure 110 may be formed. The cell gate structure 110 may include a cell gate trench 115 , a cell gate insulating layer 111 , a cell gate electrode 112 , a cell gate capping conductive layer 114 , and a cell gate capping pattern 113 . . The cell gate electrode 112 may correspond to the word line WL of FIGS. 8 and 9 .

Unlike in some embodiments, the cell gate insulating layer 111 may remain on the substrate 100 even during the planarization process of the cell gate capping pattern 113 . For example, the planarization process of the cell gate capping pattern 113 may be performed to the height of the cell gate insulating layer 111 covering the upper surface of the substrate 100 .

7 is a diagram for describing a semiconductor memory device according to some embodiments. For reference, FIG. 7 is a graph showing experimental values for explaining an etch rate of a silicon oxide film.

Referring to FIG. 7 , the Y-axis is the etching amount E/A of the silicon oxide film etched by the etching solution, and the X-axis is the depth at the surface. The uppermost graph, Si IIP, is a result value obtained by performing a silicon ion implantation process on a silicon oxide film. The next graph, REF (UHQ), is the experimental result of the reference silicon oxide film. For example, it may be a silicon oxide film deposited through an atomic layer deposition process (ALD). The next graph, PRO, is the result of an experiment after performing a curing process on the reference silicon oxide film. The curing process may be the curing process described in FIG. 5 . The last graph, the Si IIP + PRO graph, is an experimental result after a silicon ion implantation process and a curing process are performed on the reference silicon oxide film. Si IIP + PRO may correspond to the cell gate insulating layer 111 described in FIGS. 5 and 6 .

]이다. PRO 그래프를 보면, 첫번째 점은 약 50 E/A[

]이다. 즉, PRO가 Si IIP + PRO에 비해 동일 시간대비 더 많이 식각된 것을 알 수 있다. 즉, 실리콘 산화막에 큐어링 공정을 진행한 것 보다, 실리콘 주입 공정 및 큐어링 공정을 진행한 경우, 실리콘 산화막의 식각률(etch rate)이 향상될 수 있다.A point in each graph is a point at which an etching amount is recorded after being exposed to an etching solution for a certain period of time. For example, the etching solution may be hydrogen fluoride (HF), and the predetermined time may be 30 seconds. Looking at the Si IIP + PRO graph, the first point is about 30E/A[

]to be. Looking at the PRO graph, the first point is about 50 E/A[

]to be. That is, it can be seen that PRO is etched more than Si IIP + PRO compared to the same time. That is, when the silicon implantation process and the curing process are performed, the etch rate of the silicon oxide film may be improved rather than the curing process performed on the silicon oxide film.

8 and 9 are schematic layouts for describing a method of manufacturing a semiconductor memory device according to some embodiments. 10 is a cross-sectional view taken along line B-B of FIG. 9 . 11 is a cross-sectional view taken along line C-C of FIG. 9 . 12 is a cross-sectional view taken along line D-D of FIG. 9 .

For reference, FIG. 8 is a layout in which active regions and word lines of a semiconductor memory device are formed, and FIG. 9 is a layout of a semiconductor memory device including a configuration formed after FIG. 8 . Hereinafter, points overlapping with those described in FIGS. 1 to 6 will be briefly described or omitted.

In the drawing of the semiconductor device according to some embodiments, a dynamic random access memory (DRAM) is shown as an example, but is not limited thereto.

Referring to FIG. 8 , a cell device isolation layer 105 , a word line WL, and a plurality of cell active regions ACT may be formed on the substrate 100 . A description of a method of manufacturing the cell device isolation layer 105 and the word line WL may be the same as that of FIGS. 1 to 6 . The word line WL may correspond to the cell gate structure 110 of FIG. 6 .

The cell active region ACT may be defined by the cell device isolation layer 105 formed in the substrate ( 100 in FIG. 10 ). As the design rule of the semiconductor memory device decreases, as illustrated, the cell active area ACT may be arranged in a bar shape of a diagonal line or an oblique line. For example, the cell active region ACT may extend in the third direction DR3.

A plurality of gate electrodes extending in the first direction DR1 across the cell active region ACT may be disposed. A plurality of gate electrodes may extend parallel to each other. The plurality of gate electrodes may be, for example, a plurality of word lines (WL). The word lines WL may be arranged at regular intervals. The width of the word lines WL or the spacing between the word lines WL may be determined according to design rules.

Each cell active region ACT may be divided into three parts by the two word lines WL extending in the first direction D1 . The cell active area ACT may include a storage connection area 103b and a bit line connection area 103a. The bit line connection area 103a may be positioned at the center of the cell active area ACT, and the storage connection area 103b may be positioned at an end of the cell active area ACT.

Each cell active region ACT may be divided into three parts by the two word lines WL extending in the first direction DR1. The cell active area ACT may include a storage connection part 103b and a bit line connection part 103a. The bit line connection part 103a may be positioned in the center of the cell active area ACT, and the storage connection part 103b may be positioned at an end of the cell active area ACT.

For example, the bit line connection portion 103a may be an area connected to the bit line BL, and the storage connection portion 103b may be an area connected to the information storage unit ( 190 in FIG. 3 ). In other words, the bit line connection portion 103a may correspond to a common drain region, and the storage connection portion 103b may correspond to a source region. Each word line WL and the adjacent bit line connection portion 103a and storage connection portion 103b may constitute a transistor.

A plurality of bit lines (BL) extending in the second direction D2 perpendicular to the word line WL may be formed on the word line WL. A plurality of bit lines BL may extend parallel to each other. The bit lines BL may be arranged at regular intervals. The width of the bit lines BL or the interval between the bit lines BL may be determined according to design rules.

The fourth direction DR4 may be orthogonal to the first direction DR1 , the second direction DR2 , and the third direction DR3 . The fourth direction DR4 may be a thickness direction of the substrate 100 .

In the semiconductor device according to some embodiments, various contact arrangements may be formed on the cell active region ACT. Various contact arrangements may include, for example, direct contacts (DC), buried contacts (BC), and landing pads (LP).

Here, the direct contact DC may refer to a contact electrically connecting the cell active region ACT to the bit line BL. The buried contact BC may refer to a contact connecting the cell active region ACT to the lower electrode ( 191 of FIG. 4 ) of the capacitor. Due to the layout structure, a contact area between the buried contact BC and the cell active region ACT may be small. Accordingly, the conductive landing pad LP may be introduced to increase the contact area with the cell active region ACT and the lower electrode ( 191 of FIG. 4 ) of the capacitor.

The landing pad LP may be disposed between the cell active region ACT and the buried contact BC, or may be disposed between the buried contact BC and the lower electrode ( 191 of FIG. 4 ) of the capacitor. In the semiconductor device according to some embodiments, the landing pad LP may be disposed between the buried contact BC and the lower electrode of the capacitor. Contact resistance between the cell active region ACT and the lower electrode of the capacitor may be reduced by increasing the contact area through introduction of the landing pad LP.

The direct contact DC may be connected to the bit line connection region 103a. The buried contact BC may be connected to the storage connection area 103b. As the buried contact BC is disposed at both ends of the cell active area ACT, the landing pad LP is disposed adjacent to both ends of the cell active area ACT and partially overlaps the buried contact BC. can In other words, the buried contact BC is formed to overlap the cell active region ACT and the cell element isolation layer ( 105 in FIG. 4 ) between adjacent word lines WL and adjacent bit lines BL. It can be.

The word line WL may be formed in a structure buried in the substrate 100 . The word line WL may be disposed across the cell active region ACT between the direct contact DC or the buried contact BC. As shown, two word lines WL may be arranged to cross one cell active region ACT. As the cell active region ACT extends along the third direction D3 , the word line WL may have an angle of less than 90 degrees with the cell active region ACT.

The direct contact (DC) and the buried contact (BC) may be symmetrically disposed. Due to this, the direct contact DC and the buried contact BC may be disposed on a straight line along the first and second directions D1 and D2. Meanwhile, unlike the direct contact DC and the buried contact BC, the landing pad LP may be arranged in a zigzag shape in the second direction D2 in which the bit line BL extends. Also, the landing pad LP may be disposed to overlap the same lateral portion of each bit line BL in the first direction D1 in which the word line WL extends. For example, each of the landing pads LP of the first line overlaps the left side of the corresponding bit line BL, and each of the landing pads LP of the second line overlaps the right side of the corresponding bit line BL. may overlap with

8 to 12 , a semiconductor device according to some embodiments includes a plurality of cell gate structures 110, a plurality of bit line structures 140ST, a plurality of storage contacts 120, and a plurality of bits. A line contact 146 and an information storage unit 190 may be included.

The substrate 100 may be a silicon substrate or a silicon-on-insulator (SOI). Alternatively, the substrate 100 may include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto. .

The cell device isolation layer 105 may be formed in the substrate 100 . The cell device isolation layer 105 may have a shallow trench isolation (STI) structure having excellent device isolation characteristics. The cell element isolation layer 105 may define the cell active region ACT within the memory cell region.

As shown in FIGS. 8 and 9 , the cell active region ACT defined by the cell element isolation layer 105 may have a long island including a short axis and a long axis. The cell active region ACT may have an oblique shape to have an angle of less than 90 degrees with respect to the word line WL formed in the cell device isolation layer 105 . In addition, the cell active region ACT may have an oblique shape to have an angle of less than 90 degrees with respect to the bit line BL formed on the cell device isolation layer 105 .

The cell gate structure 110 may be formed in the substrate 100 and the cell device isolation layer 105 . The cell gate structure 110 may be formed across the cell device isolation layer 105 and the cell active region ACT defined by the cell device isolation layer 105 .

The cell gate structure 110 is formed within the substrate 100 and the cell device isolation layer 105 . The cell gate structure 110 includes a cell gate trench 115, a cell gate insulating layer 111, a cell gate electrode 112, a cell gate capping pattern 113, and a cell gate capping conductive layer 114. can include

Here, the cell gate electrode 112 may correspond to the word line WL. For example, the cell gate electrode 112 may be the word line WL of FIG. 1 . Unlike shown, the cell gate structure 110 may not include the cell gate capping conductive layer 114 .

Although not shown, the cell gate trench 115 may be relatively deep within the cell device isolation layer 105 and relatively shallow within the cell active regions ACT. A bottom surface of the word line WL may be curved. That is, the depth of the cell gate trench 115 in the cell device isolation layer 105 may be greater than the depth of the cell gate trench 115 in the cell active region ACT.

The cell gate insulating layer 111 may extend along sidewalls and bottom surfaces of the cell gate trench 115 . The cell gate insulating layer 111 may extend along the profile of at least a portion of the cell gate trench 115 .

The cell gate insulating layer 111 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k material having a higher dielectric constant than silicon oxide. The high dielectric constant material is, for example, boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide (lanthanum aluminum oxide), zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide (barium titanium oxide), strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate and At least one of these combinations may be included.

The cell gate electrode 112 may be disposed on the cell gate insulating layer 111 . The cell gate electrode 112 may partially fill the cell gate trench 115 . The cell gate capping conductive layer 114 may extend along the upper surface of the cell gate electrode 112 .

The cell gate electrode 112 may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride, and a conductive metal oxide. The cell gate electrode 112 may be, for example, TiN, TaC, TaN, TiSiN, TaSiN, TaTiN, TiAlN, TaAlN, WN, Ru, TiAl, TiAlC-N, TiAlC, TiC, TaCN, W, Al, Cu, Co , Ti, Ta, Ni, Pt, Ni-Pt, Nb, NbN, NbC, Mo, MoN, MoC, WC, Rh, Pd, Ir, Ag, Au, Zn, V, RuTiN, TiSi, TaSi, NiSi, CoSi , IrOx, RuOx, and combinations thereof, but is not limited thereto.

The cell gate capping conductive layer 114 may include, for example, one of polysilicon, polysilicon-germanium, amorphous silicon, and amorphous silicon-germanium, but is not limited thereto.

The cell gate capping pattern 113 may be disposed on the cell gate electrode 112 and the cell gate capping conductive layer 114 . The cell gate capping pattern 113 may fill the cell gate trench 115 remaining after the cell gate electrode 112 and the cell gate capping conductive layer 114 are formed. The cell gate insulating layer 111 is illustrated as extending along the sidewall of the cell gate capping pattern 113, but is not limited thereto.

The cell gate capping pattern 113 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO ₂ ), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof. may contain at least one.

In FIG. 12 , the upper surface of the cell gate capping pattern 113 is shown to be on the same plane as the upper surface of the cell device isolation layer 105 , but is not limited thereto.

An impurity doped region may be formed on at least one side of the cell gate structure 110 . The impurity doped region may be a source/drain region of the transistor. An impurity doped region may be formed in the storage connection part 103b and the bit line connection part 103a of FIG. 8 .

In FIG. 8 , when the transistor including each word line WL and the adjacent bit line connection part 103a and storage connection part 103b is NMOS, the storage connection part 103b and the bit line connection part 103a ) may include at least one of doped n-type impurities, for example, phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). When the transistor including each word line WL and the adjacent bit line connection part 103a and storage connection part 103b is a PMOS, the storage connection part 103b and the bit line connection part 103a are doped It may contain a p-type impurity, for example, boron (B).

The bit line structure 140ST may be formed in the second direction DR2 . The bit line structure 140ST may include a cell conductive line 140 , a cell line capping layer 144 , and a bit line spacer 150 .

The cell conductive line 140 may be disposed on the substrate 100 on which the cell gate structure 110 is formed and the cell device isolation layer 105 . The cell conductive line 140 may cross the cell device isolation layer 105 and the cell active region ACT defined by the cell device isolation layer 105 . The cell conductive line 140 may be formed to cross the cell gate structure 110 . Here, the cell conductive line 140 may correspond to the bit line BL. For example, the cell conductive line 140 may be the bit line BL of FIG. 1 .

The cell conductive line 140 may include, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a two-dimensional (2D) material, a metal, and a metal alloy. there is. In a semiconductor memory device according to some embodiments, the 2D material may be a metallic material and/or a semiconductor material. The 2D material may include a 2D allotrope or a 2D compound, for example, graphene, molybdenum disulfide (MoS2), and molybdenum diselenide (MoSe). ₂ ), tungsten diselenide (WSe ₂ ), tungsten disulfide (WS ₂ ), but may include at least one of, but is not limited thereto. That is, since the above two-dimensional materials are only listed as examples, the two-dimensional materials that may be included in the semiconductor memory device of the present invention are not limited by the above materials.

Although the cell conductive line 140 is illustrated as a single layer, it is only for convenience of explanation, and is not limited thereto. That is, unlike shown, the cell conductive line 140 may include a plurality of conductive layers in which conductive materials are stacked.

The cell line capping layer 144 may be disposed on the cell conductive line 140 . The cell line capping layer 144 may extend in the second direction DR2 along the upper surface of the cell conductive line 140 . The cell line capping layer 144 may include, for example, at least one of a silicon nitride layer, silicon oxynitride, silicon carbonitride, and silicon oxycarbonitride.

In a semiconductor memory device according to some embodiments, the cell line capping layer 144 may include a silicon nitride layer. Although the cell line capping layer 144 is illustrated as a single layer, it is not limited thereto.

The bit line spacer 150 may be disposed on sidewalls of the cell conductive line 140 and the cell line capping layer 144 . The bit line spacer 150 extends long in the second direction DR2 .

Although the bit line spacer 150 is illustrated as being a single layer, it is only for convenience of description and is not limited thereto. That is, unlike the drawing, the bit line spacer 150 may have a multilayer structure. The bit line spacer 150 may include, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer (SiON), a silicon oxycarbonitride layer (SiOCN), air, or a combination thereof, but is limited thereto. It is not.

The cell insulating film 130 may be formed on the substrate 100 and the cell device isolation film 105 . More specifically, the cell insulating layer 130 may be formed on the upper surface 105US of the cell device isolation layer and the substrate 100 on which the bit line contact 146 and the storage contact 120 are not formed. The cell insulating film 130 may be formed between the substrate 100 and the cell conductive line 140 and between the cell element isolation film 105 and the cell conductive line 140 .

The cell insulating film 130 may be a single film, but as shown, the cell insulating film 130 may be a multi-layer including a first cell insulating film 131 and a second cell insulating film 132 . For example, the first cell insulating layer 131 may include a silicon oxide layer, and the second cell insulating layer 132 may include a silicon nitride layer, but is not limited thereto. Unlike the drawing, the cell insulating layer 130 may be a triple layer including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, but is not limited thereto.

The bit line contact 146 may be formed between the cell conductive line 140 and the substrate 100 . Cell conductive line 140 may be disposed on bit line contact 146 .

The bit line contact 146 may be formed between the bit line connection portion 103a of the cell active region ACT and the cell conductive line 140 . The bit line contact 146 may electrically connect the cell conductive line 140 and the substrate 100 . The bit line contact 146 may be connected to the bit line connection portion 103a.

The bit line contact 146 may include a top surface connected to the cell conductive line 140 . Although it is illustrated that the width of the bit line contact 146 in the first direction DR1 is constant as it moves away from the upper surface of the bit line contact 146, this is only for convenience of explanation, but is not limited thereto.

The bit line contact 146 may correspond to the direct contact (DC). The bit line contact 146 may include, for example, at least one of a semiconductor material doped with impurities, a conductive metal silicide, a conductive metal nitride, a conductive metal oxide, a metal, and a metal alloy.

In a portion of the cell conductive line 140 where the bit line contact 146 is formed, the bit line spacer 150 may be formed on the substrate 100 and the cell device isolation layer 105 . The bit line spacer 150 may be disposed on sidewalls of the cell conductive line 140 , the cell line capping layer 144 , and the bit line contact 146 .

In the remaining portion of the cell conductive line 140 where the bit line contact 146 is not formed, the bit line spacer 150 may be disposed on the cell insulating layer 130 . The bit line spacer 150 may be disposed on sidewalls of the cell conductive line 140 and the cell line capping layer 144 .

The fence pattern 170 may be formed on the substrate 100 and the cell device isolation layer 105 . The fence pattern 170 may be formed to overlap the cell gate structure 110 formed in the substrate 100 and the cell device isolation layer 105 .

The fence pattern 170 may be disposed between the bit line structures 140ST extending in the second direction D2 . The fence pattern 170 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

The storage contact 120 may be formed on the second portion 103b of the cell active region ACR. The storage contact 120 may be disposed between adjacent cell conductive lines 140 in the first direction D1 . The storage contact 120 may be disposed on both sides of the cell conductive line 140 . More specifically, the storage contact 120 may be disposed between the bit line structures 140ST. The storage contact 120 may be disposed between adjacent fence patterns 170 in the second direction D2 .

The storage contact 120 may overlap the substrate 100 and the cell device isolation layer 105 between adjacent cell conductive lines 140 . The storage contact 120 may be connected to the cell active area ACT. More specifically, the storage contact 120 may be connected to the storage connection part 103b. Here, the storage contact 120 may correspond to the buried contact BC of FIG. 1 .

The storage contact 120 may include, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, and a metal.

The storage pad 160 may be formed on the storage contact 120 . The storage pad 160 may be electrically connected to the storage contact 120 . It may be connected to the storage connection portion 103b of the cell active area ACT. Here, the storage pad 160 may correspond to the landing pad LP.

The storage pad 160 may overlap a portion of the upper surface of the bit line structure 140ST. The storage pad 160 may include, for example, at least one of a conductive metal nitride, a conductive metal carbide, a metal, and a metal alloy.

The pad isolation insulating layer 180 may be formed on the storage pad 160 and the bit line structure 140ST. For example, the pad isolation insulating layer 180 may be disposed on the cell line capping layer 144 . The pad isolation insulating layer 180 may define storage pads 160 forming a plurality of isolation regions. The pad separation insulating layer 180 may not cover the upper surface 160US of the storage pad. For example, with respect to the top surface of the substrate 100 , the height of the top surface 160US of the storage pad may be the same as the height of the top surface of the pad isolation insulating layer 180 .

The pad separation insulating layer 180 may include an insulating material and electrically separate the plurality of storage pads 160 from each other. For example, the pad isolation insulating layer 180 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxycarbonitride layer, and a silicon carbonitride layer.

The etch stop layer 165 may be disposed on the upper surface 160US of the storage pad and the upper surface of the pad isolation insulating layer 180 . The etch stop layer 165 may include, for example, at least one of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), and silicon boron nitride (SiBN). can

The information storage unit 190 may be formed on the storage pad 160 . The information storage unit 190 is connected to the storage pad 160 . A portion of the information storage unit 190 may be disposed within the etch stop layer 165 .

The information storage unit 190 may include, for example, a capacitor, but is not limited thereto. The information storage unit 190 includes a lower electrode 191 , a capacitor dielectric layer 192 , and an upper electrode 193 . For example, the upper electrode 193 may be a plate upper electrode having a plate shape.

The lower electrode 191 may be disposed on the storage pad 160 . The lower electrode 191 may have, for example, a pillar shape.

A capacitor dielectric layer 192 is formed on the lower electrode 191 . The capacitor dielectric layer 192 may be formed along the profile of the lower electrode 191 . The upper electrode 193 is formed on the capacitor dielectric layer 192 . The upper electrode 193 may cover an outer wall of the lower electrode 191 . Although the upper electrode 193 is shown as a single layer, it is only for convenience of explanation, and is not limited thereto.

The lower electrode 191 and the upper electrode 193 may each be formed of, for example, a doped semiconductor material, a conductive metal nitride (eg, titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), or a metal (eg, titanium nitride, tantalum nitride, or tungsten nitride). , ruthenium, iridium, titanium or tantalum, etc.), and conductive metal oxides (eg, iridium oxide or niobium oxide, etc.), but are not limited thereto.

The capacitor dielectric layer 192 may include, for example, one of silicon oxide, silicon nitride, silicon oxynitride, high-k materials, and combinations thereof, but is not limited thereto. In the semiconductor memory device according to some embodiments, the capacitor dielectric layer 192 may include a multilayer structure in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially stacked. . In a semiconductor memory device according to some embodiments, the capacitor dielectric layer 192 may include a dielectric layer containing hafnium (Hf). In a semiconductor memory device according to some embodiments, the capacitor dielectric layer 192 may have a stacked structure of a ferroelectric material layer and a paraelectric material layer.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art can realize that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. you will be able to understand Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting.

110: cell gate structure 111: cell gate insulating layer
112 cell gate electrode 113 cell gate capping pattern
114: cell gate capping conductive film 115: cell gate trench
120: storage contact 140ST: bit line structure
160: storage pad 190: information storage unit

Claims (10)

forming a trench in the substrate;
forming a first free-cell gate insulating layer including silicon oxide along sidewalls and a bottom surface of the trench;
forming a second free cell gate insulating layer by implanting silicon (Si) ions into the first free cell gate insulating layer;
and forming a cell gate insulating layer by performing a curing process on the second free cell gate insulating layer. According to claim 1,
Forming the first free cell gate insulating layer,
A method of manufacturing a semiconductor memory device formed using an atomic layer deposition process (ALD). According to claim 1,
Wherein the curing process supplies radical oxygen and heat. According to claim 1,
The method of claim 1 , wherein an etch rate of the first free cell gate insulating layer is greater than that of the cell gate insulating layer. According to claim 1,
The method of claim 1 , wherein a thickness of the first free cell gate insulating layer is smaller than a thickness of the cell gate insulating layer. According to claim 1,
The method of claim 1 , wherein a density of silicon oxide in the cell gate insulating layer is greater than a density of silicon oxide in the first free cell gate insulating layer. According to claim 1,
After forming the second free cell gate insulating layer,
and sequentially forming a cell gate electrode, a cell gate capping conductive layer, and a cell gate capping pattern on the second pre-cell gate insulating layer. Providing a substrate including an active region defined by a device isolation film;
forming a trench extending in a first direction in the substrate and the device isolation film;
Forming a first free cell gate insulating layer including silicon oxide along sidewalls and a bottom surface of the trench using an atomic layer deposition process (ALD);
forming a second free cell gate insulating layer by implanting silicon (Si) ions into the first free cell gate insulating layer;
performing a curing process on the second free cell gate insulating layer;
forming a cell gate structure by sequentially forming a cell gate electrode, a cell gate capping conductive layer, and a cell gate capping pattern on the second free cell gate insulating layer;
The active region is divided into a first part of the active region and a second part of the active region by the cell gate electrode;
Forming a bit line structure on the substrate in a second direction different from the first direction;
forming a storage contact on a second portion of the active region;
forming a storage pad on the storage contact;
A method of manufacturing a semiconductor memory device comprising forming a capacitor on the storage pad. According to claim 8,
The method of claim 1 , wherein an etch rate of the first free cell gate insulating layer is greater than that of the cell gate insulating layer. According to claim 8,
The method of claim 1 , wherein a density of silicon oxide in the cell gate insulating layer is greater than a density of silicon oxide in the first free cell gate insulating layer.

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