TW202408107A - Process method for modulating series resistance of a high-speed VCSEL structure to improve ohmic contact and structure manufactured by the same capable of precisely controlling the setting position of the ohmic contact layer - Google Patents
Process method for modulating series resistance of a high-speed VCSEL structure to improve ohmic contact and structure manufactured by the same capable of precisely controlling the setting position of the ohmic contact layer Download PDFInfo
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Abstract
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本發明涉及一種VCSEL（Vertical Cavity Surface Emitting Laser,面射型雷射）元件之製程技術領域，特別涉及一種調變高速面射型雷射結構串聯阻值以改善歐姆接觸之製程方法及其製成結構。The present invention relates to the field of process technology for VCSEL (Vertical Cavity Surface Emitting Laser, surface-emitting laser) components, and in particular to a process method for modulating the series resistance of a high-speed surface-emitting laser structure to improve ohmic contact and its manufacture. structure.
VCSEL元件泛屬LD（Laser Diode, 半導體雷射）元件的一種，其結構由下而上一般係依序包含有一基板、一下DBR（Distributed Bragg Reflector, 分佈式布拉格反射鏡）層、一共振腔體、一上DBR層及一組正負極歐姆接觸層，以利用高反射率之DBR產生共振腔而使雷射光由晶粒表面垂直發射出來。只是，高反射率之DBR是用兩種不同折射率的材料交互堆疊而成，除有反射率分布曲線尖銳的問題外，亦有因晶體介面上明顯能隙差異而造成串聯電阻過大的情況存在。而，為因應高速數據傳輸的市場需求，習知製程技術係相應調整該組正負極歐姆接觸層的設置結構，以使該負極歐姆接觸層設置於該基板上方鄰接處或該下DBR層上方鄰接處等兩種位置，而實現調整整體元件電流路徑所對應之元件串聯電阻阻值的效果。VCSEL elements are generally a type of LD (Laser Diode, semiconductor laser) element. Its structure generally includes a substrate, a DBR (Distributed Bragg Reflector, distributed Bragg reflector) layer, and a resonant cavity in sequence from bottom to top. , an upper DBR layer and a set of positive and negative ohmic contact layers to use the high reflectivity DBR to generate a resonant cavity to emit laser light vertically from the surface of the crystal grain. However, high-reflectivity DBR is made of two materials with different refractive indexes stacked alternately. In addition to the problem of sharp reflectivity distribution curves, there are also situations where the series resistance is too large due to the obvious energy gap difference on the crystal interface. . However, in order to meet the market demand for high-speed data transmission, the conventional process technology adjusts the arrangement structure of the set of positive and negative ohmic contact layers accordingly, so that the negative ohmic contact layer is arranged adjacent above the substrate or adjacent above the lower DBR layer. There are two positions to achieve the effect of adjusting the resistance value of the series resistor of the component corresponding to the current path of the overall component.
由此可知，習知製程技術中，為設置該負極歐姆接觸層係需先蝕刻掉該上DBR層、該共振腔體及甚至該下DBR層，但於蝕刻製程中卻常有蝕刻深度無法精準控制及批次蝕刻時深度差異無法再現的問題存在，即使使用監控系統來控制蝕刻停止時點，也會因反應腔內存留有蝕刻氣體或蝕刻溶液而造成過蝕的情況，進而致使元件串聯阻值存在有高誤差值的詬病。如此，對於現今不斷追求高速及高流量傳輸的互聯網運作模式而言，不穩定的元件品質將可能造成整體互聯網系統的訊息調制效率及傳輸速度受限制，實不利於產業發展的進程。It can be seen from this that in conventional process technology, in order to set up the negative ohmic contact layer, the upper DBR layer, the resonant cavity and even the lower DBR layer need to be etched away first. However, in the etching process, the etching depth is often not accurate. There is a problem that the depth difference cannot be reproduced during control and batch etching. Even if a monitoring system is used to control the etching stop time, over-etching will occur due to the etching gas or etching solution remaining in the reaction chamber, which will lead to the series resistance of the components. There are criticisms of high error values. In this way, for today's Internet operation model that constantly pursues high-speed and high-traffic transmission, unstable component quality may cause the information modulation efficiency and transmission speed of the overall Internet system to be limited, which is really detrimental to the process of industrial development.
有感於此，如何改善製程方法來降低VCSEL元件的串聯電阻誤差問題，藉以改善上述習知技術之缺失的同時，更進一步得以依據元件規格需求任意調整該負極歐姆接觸層之設置位置而實現客製化調控串聯阻值大小的效果，即為本發明所欲探究之課題。In view of this, how to improve the process method to reduce the series resistance error problem of VCSEL components, so as to improve the deficiencies of the above-mentioned conventional technology, and further adjust the position of the negative ohmic contact layer according to the requirements of component specifications to achieve customer goals. The effect of customizing the size of the series resistance is the subject that the present invention intends to explore.
本發明之主要目的在於提供一種改善VCSEL元件歐姆接觸穩定性之製程方法，以透過蝕刻停止層的應用而改善蝕刻製程中過蝕問題，據此達精確掌控負極歐姆接觸層於元件中設置位置而實現高穩定元件品質的效益。The main purpose of the present invention is to provide a process method for improving the ohmic contact stability of VCSEL components, so as to improve the over-etching problem in the etching process through the application of an etching stop layer, thereby accurately controlling the position of the negative ohmic contact layer in the component. Achieve the benefits of high stable component quality.
為實現上述目的，本發明係揭露一種調變高速面射型雷射結構串聯阻值以改善歐姆接觸之製程方法，其包含下列步驟：磊晶形成一半導體結構，其由下而上堆疊有一基板、一下DBR層、一共振腔體及一上DBR層，且該下DBR層設有32～40個雙層堆疊對；設置n型重摻雜之一停止層，並依據一預設阻值選定該停止層之一設置位置，其中該設置位置位於該下DBR層上方鄰接處或該下DBR層區域中擇一位置穿插或取代該下DBR層之部分，以透過該停止層之該設置位置而調控該串聯阻值大小；於該半導體結構一側設置一歐姆接觸區，並對應該歐姆接觸區位置由上而下蝕刻至該停止層；及設置一歐姆接觸層於該停止層上。In order to achieve the above object, the present invention discloses a process method for modulating the series resistance of a high-speed surface-emitting laser structure to improve ohmic contact, which includes the following steps: epitaxially forming a semiconductor structure, which is stacked with a substrate from bottom to top. , a lower DBR layer, a resonant cavity and an upper DBR layer, and the lower DBR layer is provided with 32 to 40 double-layer stacking pairs; an n-type heavily doped stop layer is set and selected according to a preset resistance value A setting position of the stop layer, wherein the setting position is located above the lower DBR layer or at a position in the area of the lower DBR layer that intersperses or replaces a portion of the lower DBR layer, so as to pass through the setting position of the stop layer The series resistance is controlled; an ohmic contact area is provided on one side of the semiconductor structure, and the ohmic contact area is etched from top to bottom to the stop layer; and an ohmic contact layer is provided on the stop layer.
其中，該停止層係採用InP、InGaP、GaAsP或AlGaAsP之含磷材料，以降低蝕刻速率而提升該歐姆接觸層的設置位置精準性，進而確保該串聯阻值大小的精確性。各該雙層堆疊對係分別為Al (0.9)Ga (0.1)As/Al (0.1)Ga (0.9)As堆疊結構，而設置該停止層時，該等雙層堆疊對之其中一對係由In (x)Ga (1-x)P/Al (0.1)Ga (0.9)As結構所取代，且X為0.56～0.71。於該半導體結構一側設置一歐姆接觸區，並對應該歐姆接觸區位置由上而下蝕刻該上DBR層及該共振腔體至該停止層步驟中，係先利用乾蝕刻法蝕刻該上DBR層及該共振腔體至鄰近該停止層上方處後，再利用濕蝕刻法蝕刻剩餘部位至該停止層。利用濕蝕刻法蝕刻至該停止層時係使用NH 4OH：H 2O 2蝕刻液。利用濕蝕刻法蝕刻至該停止層時係使用配方比例1：10的NH 4OH：H 2O 2蝕刻液。利用濕蝕刻法蝕刻採用InGaAsP材料之該停止層時，係使用HCL：H 3PO 4蝕刻液。利用濕蝕刻法蝕刻採用InP或InGaP材料之該停止層時，係使用H 3PO 4：H 2O 2：H 2O蝕刻液。利用濕蝕刻法蝕刻採用InP材料之該停止層時，係使用H 2SO 4：H 2O 2：H 2O蝕刻液或C 6H 8O 7：H 2O 2蝕刻液。 The stop layer is made of phosphorus-containing materials such as InP, InGaP, GaAsP or AlGaAsP to reduce the etching rate and improve the placement accuracy of the ohmic contact layer, thereby ensuring the accuracy of the series resistance. Each of the double-layer stacked pairs is an Al (0.9) Ga (0.1) As/Al (0.1) Ga (0.9) As stacked structure, and when the stop layer is provided, one of the double-layer stacked pairs is composed of In (x) Ga (1-x) P/Al (0.1) Ga (0.9) As structure is substituted, and X is 0.56~0.71. An ohmic contact area is provided on one side of the semiconductor structure, and the upper DBR layer and the resonant cavity are etched from top to bottom at the position of the ohmic contact area to the stop layer. The upper DBR is first etched by dry etching. After the layer and the resonant cavity are positioned adjacent to the stop layer, wet etching is used to etch the remaining portions to the stop layer. When etching to the stop layer by wet etching, NH 4 OH: H 2 O 2 etching solution is used. When etching to the stop layer by wet etching, a NH 4 OH: H 2 O 2 etching solution with a formula ratio of 1:10 is used. When wet etching is used to etch the stop layer made of InGaAsP material, HCL:H 3 PO 4 etching liquid is used. When wet etching is used to etch the stop layer made of InP or InGaP material, H 3 PO 4 :H 2 O 2 :H 2 O etching liquid is used. When the stop layer using InP material is etched by wet etching, H 2 SO 4 :H 2 O 2 :H 2 O etching liquid or C 6 H 8 O 7 :H 2 O 2 etching liquid is used.
並且，本發明之次一目的係揭示一種利用上述製程方法製作而成的高速面射型雷射（VCSEL）結構。Moreover, a second object of the present invention is to disclose a high-speed surface-emitting laser (VCSEL) structure produced by the above-mentioned process method.
綜上所述，本發明係利用含磷材料之該停止層搭配相應的蝕刻溶液來實現減緩磊晶層的蝕刻速率，而解決該上DBR層、該共振腔體及甚或該下DBR層於蝕刻製程中過蝕的問題，據此以精確掌控該歐姆接觸層之該設置位置而達提升整體VCSEL結構品質穩定性的功效。並且，本發明係依據該預設阻值選定該停止層之該設置位置，係可使該VCSEL結構具客製化的串聯阻值而便利後續應用系統的配置，進而提升產品實用效益而滿足市場應用需求。順帶一提的是，該停止層置入該下DBR層時，若使用In (x)Ga (1-x)P/Al (0.1)Ga (0.9)As結構取代原先Al (0.9)Ga (0.1)As/Al (0.1)Ga (0.9)As結構之一該雙層堆疊對時，可能有載子濃度差 變小而影響此層堆疊對反射率的疑慮，然，因本發明係使該下DBR設置有32～40個雙層堆疊對，故對整體該下DBR層而言仍可維持＞99%的反射率，亦即不影響整體元件的發光效率。 To sum up, the present invention uses the stop layer of phosphorus-containing material and the corresponding etching solution to slow down the etching rate of the epitaxial layer, thereby solving the problem of etching of the upper DBR layer, the resonant cavity and even the lower DBR layer. To solve the problem of over-etching during the manufacturing process, the position of the ohmic contact layer can be precisely controlled to improve the quality stability of the overall VCSEL structure. Moreover, the present invention selects the setting position of the stop layer based on the preset resistance value, which allows the VCSEL structure to have a customized series resistance value to facilitate the configuration of subsequent application systems, thereby improving the practical benefits of the product and satisfying the market application requirements. By the way, when the stop layer is placed in the lower DBR layer, if the In (x) Ga (1-x) P/Al (0.1) Ga (0.9) As structure is used to replace the original Al (0.9) Ga (0.1 ) As/Al (0.1) Ga (0.9) One of the As structures, when the double layer stack is paired, there may be a carrier concentration difference. However, since the lower DBR is provided with 32 to 40 double-layer stack pairs, the lower DBR layer as a whole can still maintain >99% of the reflectivity. Reflectivity, that is, it does not affect the luminous efficiency of the overall component.
為使本領域具有通常知識者能清楚了解本新型之內容，謹以下列說明搭配圖式，敬請參閱。In order to enable those with ordinary knowledge in the field to clearly understand the contents of the present invention, the following description is accompanied by the drawings, please refer to them.
請參閱第1、2圖，其係分別為本發明一較佳實施例之流程圖及結構示意圖。如圖所示，該調變高速面射型雷射結構串聯阻值以改善歐姆接觸之製程方法係包含下列步驟：步驟S10，磊晶形成一半導體結構，其由下而上至少堆疊有一基板100、一下DBR層101、一共振腔體102及一上DBR層103，且該下DBR層101設有32～40個雙層堆疊1010；步驟S11，設置n型重摻雜之一停止層104，並依據一預設阻值選定該停止層104之一設置位置，其中該設置位置位於該下DBR層101上方鄰接處或該下DBR層101區域中擇一位置穿插或取代該下DBR層101之部分，以透過該停止層104之該設置位置而調控該串聯阻值大小；步驟S12，於該半導體結構一側設置一歐姆接觸區，並對應該歐姆接觸區位置由上而下蝕刻至該停止層104；及步驟S13，設置一歐姆接觸層105於該停止層104上。Please refer to Figures 1 and 2, which are respectively a flow chart and a schematic structural diagram of a preferred embodiment of the present invention. As shown in the figure, the process method for modulating the series resistance of a high-speed surface-emitting laser structure to improve ohmic contact includes the following steps: Step S10, epitaxially forming a semiconductor structure, which is stacked with at least one substrate 100 from bottom to top. , a lower DBR layer 101, a resonant cavity 102 and an upper DBR layer 103, and the lower DBR layer 101 is provided with 32 to 40 double-layer stacks 1010; step S11, setting an n-type heavily doped stop layer 104, And select a setting position of the stop layer 104 according to a preset resistance value, wherein the setting position is located adjacent to the lower DBR layer 101 or in the area of the lower DBR layer 101 to intersperse or replace the lower DBR layer 101 part to control the series resistance value through the setting position of the stop layer 104; step S12, set an ohmic contact area on one side of the semiconductor structure, and etch the ohmic contact area position from top to bottom to the stop layer 104; and step S13, disposing an ohmic contact layer 105 on the stop layer 104.
由此可知，利用該製程方法製作而成之一高速面射型雷射結構1由下而上至少設有該基板100、該下DBR層101、該停止層104、該共振腔體102及該上DBR層103，且於該高速面射型雷射結構1一側之該停止層104上方係設有該歐姆接觸層105。其中，該停止層104可置於該下DBR層101上方鄰接處或置於該下DBR層101區域中任一深度位置處，將可提升該歐姆接觸層105設置位置之寬廣度及精準度，進而使該串聯阻值隨之呈現穩定可調變的阻值狀態，以提升該高速面射型雷射結構1的整體元件應用適應性。It can be seen from this that a high-speed surface-emitting laser structure 1 produced by this process method is provided with at least the substrate 100, the lower DBR layer 101, the stop layer 104, the resonant cavity 102 and the The DBR layer 103 is on, and the ohmic contact layer 105 is provided above the stop layer 104 on one side of the high-speed surface-emitting laser structure 1 . Among them, the stop layer 104 can be placed adjacent to the upper part of the lower DBR layer 101 or placed at any depth position in the area of the lower DBR layer 101, which will improve the breadth and accuracy of the placement position of the ohmic contact layer 105. Then, the series resistance becomes a stable and adjustable resistance state, thereby improving the overall component application adaptability of the high-speed surface-emitting laser structure 1 .
請參閱第3、4圖，其係分別為本發明二較佳實施例之流程圖及流程示意圖。如圖所示，該高速面射型雷射結構1之一半導體結構10一般係包含有一基板100、一下DBR層101、一共振腔體102及一上DBR層103，據此，為調變該高速面射型雷射結構1串聯阻值以改善歐姆接觸之該製程方法可包含下列步驟：步驟S20，依據一預設阻值，選定n型重摻雜之一停止層104於該半導體結構10中之一設置位置而形成一設計結構，且該設置位置可位於該下DBR層101上方鄰接處或該下DBR層101區域中擇一位置穿插或取代該下DBR層101之部分，以供決定後續製程中一歐姆接觸層105之設置位置；及步驟S21，依據上述設計結構，磊晶形成該半導體結構10，其由下而上至少堆疊有該基板100、該下DBR層101、該停止層104、該共振腔體102及該上DBR層103，且該共振腔體102一般由下而上可至少設有一下批覆層、一主動層、一上批覆層、一氧化層及一上隔離層。該下DBR層101設有32～40個雙層堆疊1010，各該雙層堆疊對1010可分別為Al (0.9)Ga (0.1)As/Al (0.1)Ga (0.9)As堆疊結構，而該停止層104係採用InP、InGaP、GaAsP或AlGaAsP之含磷材料製成，故設置該停止層104時，該等雙層堆疊對1010之其中一對可由In (x)Ga (1-x)P/Al (0.1)Ga (0.9)As結構所取代，以於不明顯影響該下DBR層101整體反射率的前提下減緩後續蝕刻製程中蝕刻速率，其中，X為0.56～0.71。 Please refer to Figures 3 and 4, which are respectively a flow chart and a schematic flow diagram of two preferred embodiments of the present invention. As shown in the figure, the semiconductor structure 10 of the high-speed surface-emitting laser structure 1 generally includes a substrate 100, a lower DBR layer 101, a resonant cavity 102 and an upper DBR layer 103. Accordingly, in order to modulate the The process method of connecting resistance values in series with the high-speed surface-emitting laser structure 1 to improve ohmic contact may include the following steps: Step S20, according to a preset resistance value, select an n-type heavily doped stop layer 104 in the semiconductor structure 10 One of the installation locations forms a design structure, and the installation location can be located adjacent to the upper part of the lower DBR layer 101 or interspersed with or replaces a part of the lower DBR layer 101 in the area of the lower DBR layer 101 for decision The placement position of an ohmic contact layer 105 in the subsequent process; and step S21, based on the above design structure, the semiconductor structure 10 is epitaxially formed, which is stacked with at least the substrate 100, the lower DBR layer 101, and the stop layer from bottom to top. 104. The resonant cavity 102 and the upper DBR layer 103, and the resonant cavity 102 can generally be provided with at least a lower cladding layer, an active layer, an upper cladding layer, an oxide layer and an upper isolation layer from bottom to top. . The lower DBR layer 101 is provided with 32 to 40 double-layer stacks 1010, and each double-layer stack pair 1010 can be an Al (0.9) Ga (0.1) As/Al (0.1) Ga (0.9) As stack structure. The stop layer 104 is made of a phosphorus-containing material of InP, InGaP, GaAsP or AlGaAsP. Therefore, when the stop layer 104 is provided, one of the double-layer stack pairs 1010 can be made of In (x) Ga (1-x) P /Al (0.1) Ga (0.9) As structure to slow down the etching rate in the subsequent etching process without significantly affecting the overall reflectivity of the lower DBR layer 101, where X is 0.56 to 0.71.
步驟S22，於該半導體結構10一側設置一歐姆接觸區11，並對應該歐姆接觸區位置11利用乾蝕刻法由上而下蝕刻該上DBR層103及該共振腔體102至鄰近該停止層104上方處後，步驟S23，利用如配方比例1：10的NH 4OH：H 2O 2之蝕刻液濕蝕刻剩餘的垂直結構部位至該停止層104。於本實施例中，當該停止層104採用InGaAsP材料時，更可使用HCL：H 3PO 4蝕刻液進行濕蝕刻；該停止層104採用InP或InGaP材料時，更可使用H 3PO 4：H 2O 2：H 2O蝕刻液進行濕蝕刻；該停止層104採用InP材料時，更可使用H 2SO 4：H 2O 2：H 2O蝕刻液或C 6H 8O 7：H 2O 2蝕刻液進行濕蝕刻。 Step S22 , an ohmic contact region 11 is provided on one side of the semiconductor structure 10 , and the upper DBR layer 103 and the resonant cavity 102 are etched from top to bottom using a dry etching method at the ohmic contact region 11 to be adjacent to the stop layer. After being above 104, in step S23, the remaining vertical structure parts are wet-etched to the stop layer 104 using an etching solution of NH 4 OH: H 2 O 2 with a formula ratio of 1:10. In this embodiment, when the stop layer 104 is made of InGaAsP material, HCL:H 3 PO 4 etchant can be used for wet etching; when the stop layer 104 is made of InP or InGaP material, H 3 PO 4 can be used: H 2 O 2 :H 2 O etchant is used for wet etching; when the stop layer 104 is made of InP material, H 2 SO 4 :H 2 O 2 :H 2 O etchant or C 6 H 8 O 7 :H can be used. 2 O 2 etching solution for wet etching.
接著，設置一正極金屬接觸層106於該上DBR層103上的同時，步驟S24，設置一歐姆接觸層105於該停止層104上，據此，因採用含磷材料之該停止層104減緩了蝕刻速率，故可避免蝕刻製程中該下DBR層101的過蝕問題而提升該歐姆接觸層105的設置位置精準性，進而達確保由該正極金屬接觸層106至該歐姆接觸層105之元件電流路徑所對應之該串聯阻值之精確性的功效。承上所述，利用該製程方法製作而成之該高速面射型雷射結構1之元件串聯電阻阻值（R）在不計電容值的前提下，可如圖5中(a)、(b)、(c)三種結構態樣所示分別為R=R1+R2、R=R1+R3+R2或R=R1+R4+R2等，其中R4＞R3，因此(c)態樣中串聯電阻阻值＞(b)＞(a)。據此，透過該停止層104之該設置位置的深度調整，係隨之調控該串聯阻值大小，故使該高速面射型雷射結構1可具有調變串聯阻值的特色而適應市場需求。Next, while a positive metal contact layer 106 is disposed on the upper DBR layer 103, in step S24, an ohmic contact layer 105 is disposed on the stop layer 104. Accordingly, the stop layer 104 using a phosphorus-containing material slows down the The etching rate can avoid the over-etching problem of the lower DBR layer 101 during the etching process and improve the placement accuracy of the ohmic contact layer 105, thereby ensuring the component current from the positive metal contact layer 106 to the ohmic contact layer 105. The effect of the accuracy of the series resistance corresponding to the path. Following the above, the series resistance (R) of the component of the high-speed surface-emitting laser structure 1 produced by this process method, excluding the capacitance value, can be as shown in Figure 5 (a) and (b) ), (c) The three structural aspects are shown as R=R1+R2, R=R1+R3+R2 or R=R1+R4+R2, etc., among which R4>R3, so the series resistor in (c) Resistance value＞(b)＞(a). Accordingly, by adjusting the depth of the setting position of the stop layer 104, the series resistance is adjusted accordingly, so that the high-speed surface-emitting laser structure 1 can have the characteristic of modulating the series resistance to adapt to market demand. .
惟，以上所述者，僅為本發明之較佳實施例而已，並非用以限定本發明實施之範圍；故在不脫離本發明之精神與範圍下所作之均等變化與修飾，皆應涵蓋於本發明之專利範圍內。However, the above are only preferred embodiments of the present invention and are not intended to limit the scope of the present invention; therefore, equal changes and modifications made without departing from the spirit and scope of the present invention should be included in within the patent scope of this invention.
S10～S13:步驟 S20～S24:步驟 1:高速面射型雷射結構 10:半導體結構 100:基板 101:下DBR層 1010:雙層堆疊對 102:共振腔體 1020:下批覆層 1021:主動層 1022:上批覆層 1023:氧化層 1024:上隔離層 103:上DBR層 104:停止層 105:歐姆接觸層 106:正極金屬接觸層 11:歐姆接觸區 S10～S13: steps S20～S24: steps 1: High-speed surface-emitting laser structure 10: Semiconductor structure 100:Substrate 101: Lower DBR layer 1010:Double stacked pair 102: Resonance cavity 1020: Next batch of cladding layer 1021:Active layer 1022: Previous batch of cladding 1023:Oxide layer 1024: Upper isolation layer 103: Go to DBR layer 104: Stop layer 105: Ohmic contact layer 106: Positive metal contact layer 11: Ohmic contact area
第1圖，為本發明一較佳實施例之流程圖。 第2圖，為本發明一較佳實施例之結構示意圖。 第3圖，為本發明二較佳實施例之流程圖。 第4圖，為本發明二較佳實施例之流程示意圖。 第5圖，為本發明二較佳實施例之結構態樣示意圖。 Figure 1 is a flow chart of a preferred embodiment of the present invention. Figure 2 is a schematic structural diagram of a preferred embodiment of the present invention. Figure 3 is a flow chart of the second preferred embodiment of the present invention. Figure 4 is a schematic flow chart of the second preferred embodiment of the present invention. Figure 5 is a schematic diagram of the structure of the second preferred embodiment of the present invention.
S10~S13:步驟 S10~S13: Steps
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