TW202408109A - Process method and manufacturing structure of high-power vertical cavity surface emitting laser with low series resistance structure for improving the series resistance structure of a VCSEL structure with a multi-layer resonance cavity - Google Patents

Abstract

The present invention provides a process method and manufacturing structure of a high-power vertical cavity surface emitting laser (VCSEL) with a low series resistance structure, which can improve the series resistance structure of a VCSEL structure with a multi-layer resonance cavity. The multi-layer resonance cavity has 2 to 9 active layers. Through the technical means of respectively arranging the n/p heavily-doped first stop layer and second stop layer at the upper and lower adjacent parts of the multi-layer resonance cavity, the present invention adjusts the position of the positive and negative metal contact layers to optimally reduce the current path length of devices and avoid over-etching problems during the manufacturing process, so that the positive and negative metal contact layers can be accurately disposed at the required locations, thereby effectively reducing the series resistance of devices. Further, by utilizing the low resistance characteristics of the heavily-doped first and second stop layers, it is able to further achieve the effect of reducing the value of the series resistance.

Description

Process method and fabrication structure of high-power surface-emitting laser with low series resistance structure

The present invention relates to the technical field of manufacturing VCSEL (Vertical Cavity Surface Emitting Laser, surface-emitting laser) components, and in particular to a manufacturing method and manufacturing structure of a high-power surface-emitting laser with a low series resistance structure.

VCSEL elements are generally a type of LD (Laser Diode, semiconductor laser) element. Its structure generally includes a substrate, a DBR (Distributed Bragg Reflector, distributed Bragg reflector) layer, and a resonant cavity in sequence from bottom to top. , an upper DBR layer and a set of positive and negative metal contact layers to use the high reflectivity DBR to generate a resonance effect to emit laser light vertically from the surface of the crystal grain. However, high-reflectivity DBR is made of two materials with different refractive indexes stacked alternately. In addition to the problem of sharp reflectivity distribution curves, there are also situations where the series resistance is too large due to the obvious energy gap difference on the crystal interface. . Moreover, in response to the market demand for high-speed data transmission, the market has introduced a VCSEL device with a resonant cavity with multiple active layers to enhance the resonance effect and increase the emitted laser light power by stacking these active layers. However, A person with ordinary knowledge can know that the total resistance generated by the resonant cavity will be formed by the resistance of the active layers in series, causing the device to have a more intensified series resistance and a high threshold voltage, which in turn will lead to high power of the device. consumption problem.

To this end, the conventional process technology adjusts the arrangement structure of the set of positive and negative metal contact layers accordingly. For example, the negative metal contact layer can be arranged at two locations, adjacent above the substrate or adjacent above the lower DBR layer. Accordingly, the resistance value of the series resistor of the component corresponding to the current path of the overall component is adjusted. However, in order to set up the negative metal contact layer, the upper DBR layer, the resonant cavity and even the lower DBR layer need to be etched out first. However, in the etching process, the etching depth often cannot be accurately controlled and the depth varies between batches of etching. Problems that cannot be reproduced exist. Even if a monitoring system is used to control the etching stop time, over-etching will occur due to the etching gas or etching solution remaining in the reaction chamber, which will lead to high error values in the series resistance of the components and affect the performance. Criticism of component quality. Furthermore, in response to today's Internet operation model that constantly pursues high-speed and high-traffic transmission, VCSEL components with high power consumption and unstable quality may cause the information modulation efficiency and transmission speed of the overall Internet system to be limited, which is not conducive to The process of industrial development.

In view of this, how to make good use of the chemical characteristics of each epitaxial layer to improve the process technology to provide a lowest series resistance structure design for VCSEL devices with multi-layer active layer resonant cavities, thereby significantly reducing the cost of high-power VCSEL devices. The subject of the present invention is to connect resistors in series and improve the stability of the resistance, so as to improve the deficiencies of the above-mentioned conventional technologies.

The main purpose of the present invention is to provide a method for manufacturing a high-power surface-emitting laser with a low series resistance structure and its manufacturing structure, so as to reduce the series resistance through the application of an etching stop layer and improve the etching process. The effect of ensuring constant resistance value is to eliminate corrosion problems.

In order to achieve the above object, the present invention discloses a process method for high-power surface-emitting laser with a low series resistance structure, which includes the following steps: building a design structure in which a substrate and a DBR layer are stacked from bottom to top. , a multi-layer resonant cavity and an upper DBR layer, wherein the multi-layer resonant cavity is provided with 2 to 9 resonant chambers, each resonant chamber is provided with an active layer, and the upper DBR layer is provided with 22 to 30 resonant chambers. The lower DBR layer is provided with 32 to 40 lower double-layer stack pairs; a heavily doped first stop layer and a second stop layer are provided adjacent to the upper and lower parts of the multi-layer resonant cavity, The first stop layer is located at an adjacent point below the upper DBR layer, and the second stop layer is located at an adjacent point above the lower DBR layer. Accordingly, through the arrangement position of the first stop layer and the third The position of the two stop layers effectively reduces the resistance of the series resistor; according to the design structure, epitaxy forms a semiconductor structure; a negative metal contact area is set on the ring side of the semiconductor structure, corresponding to the position of the negative metal contact area Etch from top to bottom to the second stop layer to form a first high platform in the center of the semiconductor structure; a positive metal contact area is provided on one side of the first high platform, and the position of the positive metal contact area is aligned from top to bottom. Etch down to the first stop layer to form a second high platform on the first high platform, and the second high platform area is smaller than the first high platform; and respectively provide a positive metal contact layer on the first stop layer, and disposing a negative metal contact layer on the second stop layer.

Among them, the first stop layer and the second stop layer are made of phosphorus-containing materials of InP, InGaP, GaAsP or AlGaAsP and are heavily doped with n/p type to reduce the etching rate and improve the positive electrode metal contact layer and the negative electrode. The precise location of the metal contact layer ensures the accuracy of the resistance value of the series resistor. Each of the upper double-layer stack pairs is an Al _(0.9) Ga _(0.1) As/Al _(0.1) Ga _(0.9) As stack structure, and when the first stop layer is provided, the upper double-layer stacked pair is adjacent to one of the multi-layer resonant cavities. The double-layer stacking pair is replaced by the In _(x) Ga _(1-x) P/Al _(0.1) Ga _(0.9) As structure; the lower double-layer stacking pairs are Al _(0.9) Ga _(0.1) As/ Al _(0.1) Ga _(0.9) As stack structure, and when the second stop layer is provided, the lower double-layer stack pair adjacent to one of the multi-layer resonance cavities is composed of In _(x) Ga _(1-x) P/Al _(0.1) Ga _(0.9) As structure substituted, and X is 0.56~0.71. The negative metal contact area is provided on the ring side of the semiconductor structure, and the upper DBR layer, the first stop layer and the multi-layer resonant cavity are etched from top to bottom using a dry etching method to adjacent to the negative metal contact area. After the second stop layer is above the second stop layer, wet etching is used to etch the remaining portion above the second stop layer to the second stop layer, so that the first platform is formed in the center of the semiconductor structure; then, the multi-layer resonant cavity is side-mounted. While oxidizing, an oxide layer provided on the active layer in each resonance chamber is formed with an oxidation hole respectively, and the positive metal contact area is provided on one side of the first platform, corresponding to the position of the positive metal contact area Use a dry etching method to etch the upper DBR layer from top to bottom to a position adjacent to the first stop layer, and then use a wet etching method to etch the remaining portion to the first stop layer, so that the second portion of the first plateau is formed. high tower. When etching to the stop layer by wet etching, NH ₄ OH: H ₂ O ₂ etching solution is used. When etching to the stop layer by wet etching, a NH ₄ OH: H ₂ O ₂ etching solution with a formula ratio of 1:10 is used. When using the wet etching method to etch the first stop layer and the second stop layer made of InGaAsP material, use HCL: H ₃ PO ₄ etching liquid; use the wet etching method to etch the first stop layer made of InP or InGaP material and For this second stop layer, H ₃ PO ₄ :H ₂ O ₂ :H ₂ O etching liquid is used. When using the wet etching method to etch the first stop layer and the second stop layer using InP material, use H ₂ SO ₄ : H ₂ O ₂ : H ₂ O etching solution or C ₆ H ₈ O ₇ : H ₂ O ₂ etching liquid.

In addition, to achieve the second object, the present invention further discloses a high-power surface-emitting laser structure manufactured by the above-mentioned manufacturing method. When epitaxially forming the semiconductor structure, the substrate is etched from top to bottom in the center of the semiconductor structure for subsequent processes to form two high-power surface-emitting laser structures that share the substrate, and each The positive metal contact layers of the high-power surface-emitting laser structures are wired and connected to each other; the negative metal contact layers of each high-power surface-emitting laser structure are wired and connected to each other, so that the two high-power surface-emitting laser structures are connected in parallel. connection.

To sum up, the present invention considers the high resistance problem caused by the superposition of multiple resonant cavities in the multi-layer resonant cavity, so that the first stop layer and the second stop layer are respectively disposed adjacent to each other above and below the multi-layer resonant cavity. , thereby reducing the current path length of the component and reducing its corresponding series resistor resistance. Moreover, the first and second stop layers are respectively n/p-type heavily doped epitaxial layers and have low resistance characteristics, which can further reduce the resistance between the positive and negative metal contact layers and the multi-layer resonant cavity. size, and optimize the configuration of the low series resistance structure. Furthermore, the present invention uses the first and second stop layers of phosphorus-containing materials with corresponding etching solutions to slow down the etching rate of the epitaxial layer, which can solve the problem of over-etching of the upper DBR layer and the multi-layer resonant cavity during the etching process. problem, and can accurately control the placement positions of the positive and negative metal contact layers and achieve the effect of improving the quality and stability of the overall VCSEL structure.

By the way, when the first stop layer is placed in the upper DBR layer and the second stop layer is placed in the lower DBR layer, if In _(x) Ga _(1-x) P/Al _(0.1) Ga is used _(0.9) As structure replaces the original Al _(0.9) Ga _(0.1) As/Al _(0.1) Ga _(0.9) As structure double-layer stacking pair, there may be a carrier concentration difference However, the present invention makes the upper DBR layer provided with 22 to 30 upper double-layer stack pairs, and the lower DBR layer is provided with 32 to 40 lower double-layer stack pairs. Yes, so the overall reflectivity of >99% can still be maintained for the upper and lower DBR layers, which means it does not affect the luminous efficiency of the overall device.

In order to enable those with ordinary knowledge in the field to clearly understand the contents of the present invention, the following description is accompanied by the drawings, please refer to them.

Please refer to Figures 1 and 2, which are respectively a flow chart and a schematic structural diagram of a preferred embodiment of the present invention. As shown in the figure, the manufacturing method of the high-power surface-emitting laser with a low series resistance structure includes the following steps: Step S10, build a design structure, which stacks at least one substrate 100 and a DBR layer from bottom to top. 101. A multi-layer resonant cavity 103 and an upper DBR layer 105, wherein the multi-layer resonant cavity 103 is provided with 2 to 9 resonant chambers, each resonant chamber is provided with an active layer 1031, and the upper DBR layer 105 is provided with 22 to 30 upper double-layer stack pairs 1050, and the lower DBR layer 101 is provided with 32 to 40 lower double-layer stack pairs 1010; Step S11, set a heavily doped first stop layer 104 and a second The stop layer 102 is adjacent to the upper and lower parts of the multi-layer resonant cavity 103. The first stop layer 104 is located adjacent to the lower part of the upper DBR layer 105, and the second stop layer 102 is located at the lower DBR layer 101. The upper adjacent position is accordingly used to reduce the length of the current path through the position of the first stop layer 104 and the position of the second stop layer 102, thereby effectively reducing the resistance of the series resistor; step S12, according to the design structure, Epitaxy forms a semiconductor structure; step S13, a negative metal contact area is provided on the ring side of the semiconductor structure, and the position of the negative metal contact area is etched from top to bottom to the second stop layer 102 to make the semiconductor structure 10 A first high platform 11 is formed in the central part; step S14, a positive metal contact area is provided on one side of the first high platform 11, and the position of the positive metal contact area is etched from top to bottom to the first stop layer 104. A second elevated platform 12 is formed on the first elevated platform 11, and the area of the second elevated platform 12 is smaller than that of the first elevated platform 11; and step S15, a positive metal contact layer 106 is respectively provided on the first stop layer 104, and A negative metal contact layer 107 is disposed on the second stop layer 102 .

It can be seen from this that a high-power surface-emitting laser structure 1 produced by this process method is provided with at least the substrate 100, the lower DBR layer 101, the second stop layer 102, and the multi-layer resonant cavity from bottom to top. The body 103, the first stop layer 104 and the upper DBR layer 105, the high-power surface-emitting laser structure 1 has the first platform 11 formed in the center above the second stop layer 102, and the first The second high platform 12 with a relatively small area is formed on the high platform 11, and the negative metal contact layer 107 is provided on the second stop layer 102 on one side of the first high platform 11. Next to the second high platform 12 The positive metal contact layer 106 is disposed on the first stop layer 104 . Wherein, the first stop layer 104 is located at the adjacent point below the upper DBR layer 105, that is, between the upper DBR layer 105 and the multi-layer resonant cavity 103; the second stop layer 102 is located at the adjacent point. The upper adjoining part of the lower DBR layer 101 is between the lower DBR layer 101 and the multi-layer resonant cavity 103. Accordingly, through the position of the first stop layer 104 provided at the upper and lower adjacent parts of the multi-layer resonant cavity 103 and The position of the second stop layer 102 greatly shortens the distance between the positive metal connection layer 106 and the negative metal contact layer 107. In other words, it greatly shortens the resistance value of the series resistor corresponding to the component current path to effectively reduce the resistance. The effect of value size.

Please refer to Figures 3A, 3B, and 4A to 4E, which are respectively flow charts and flow schematic diagrams of two preferred embodiments of the present invention. As shown in the figure, the high-power surface-emitting laser structure 1 can increase the optical resonance intensity through a multi-layer resonant cavity 103 to increase the output laser optical power, thereby meeting the application needs of the current high-end market, and the multi-layer resonance The cavity 103 is composed of a plurality of resonant cavities stacked on top of each other. Therefore, it has a higher resistance value than the conventional resonant cavity that only contains a single active layer, causing the device to have the disadvantage of high power consumption. for industrial applications. Therefore, in order to improve the ohmic contact to achieve optimized low series resistance, the manufacturing method of the high-power surface-emitting laser structure 1 may include the following steps: Step S20, build a design structure, which is at least A substrate 100, a lower DBR layer 101, a multi-layer resonant cavity 103 and an upper DBR layer 105 are stacked. The multi-layer resonant cavity 103 can be provided with 2 to 9 resonant cavities, and each resonant cavity is arranged from bottom to top. The top layer may at least include a lower cladding layer 1030, an active layer 1031, an upper cladding layer 1032, an oxide layer 1033 and an upper isolation layer 1034. The upper DBR layer 105 is provided with 22-30 upper double-layer stacking pairs 1050, and the lower DBR layer 101 is provided with 32-40 lower double-layer stacking pairs 1010.

Step S21: Set an n/p-type heavily doped first stop layer 104 and a second stop layer 102 at a position adjacent to the upper and lower parts of the multi-layer resonant cavity 103, that is, the first stop layer The disposed position of 104 is located adjacent to the lower part of the upper DBR layer 105; the disposed position of the second stop layer 102 is located to the adjacent position of the upper part of the lower DBR layer 101 for passing through the first stop layer 104 and the second stop layer 102. The arrangement position further determines the arrangement position of a positive metal contact layer 106 and a negative metal contact layer 107 in subsequent processes, thereby effectively reducing the resistance of the series resistor. In this embodiment, each of the upper double-layer stack pairs 1050 is an Al _(0.9) Ga _(0.1) As/Al _(0.1) Ga _(0.9) As stack structure, and the first stop layer 104 is made of InP, InGaP, It is made of phosphorus-containing materials such as GaAsP or AlGaAsP. Therefore, when the first stop layer 104 is provided, one of the upper double-layer stack pairs 1050 adjacent to the multi-layer resonant cavity 103 is made of In _(x) Ga _(1-x) P/Al. _{(0.1) Ga ( 0.9 )} As structure is replaced, _and And the second stop layer 102 is also made of phosphorus-containing materials such as InP, InGaP, GaAsP or AlGaAsP. Therefore, when the second stop layer 102 is provided, the lower double-layer stack pair 1010 adjacent to the multi-layer resonant cavity 103 is composed of Replaced by In _(x) Ga _(1-x) P/Al _(0.1) Ga _(0.9) As structure, X is 0.56~0.71. In step S22, a semiconductor structure 10 is formed by epitaxy according to the designed structure.

Next, in step S23, a negative metal contact area 13 is provided on the ring side of the semiconductor structure 10, and the upper DBR layer 105 and the first stop layer 104 are etched from top to bottom using a dry etching method at the position of the negative metal contact area 13. After the multi-layer resonant cavity 103 is adjacent to the top of the second stop layer 102, in step S230, the top of the second stop layer 102 is wet-etched using an etching solution of NH ₄ OH: H ₂ O ₂ with a formula ratio of 1:10. The remaining vertical structure portion reaches the second stop layer 102 so that a first platform 11 is formed in the central portion of the semiconductor structure 10 . Step S24 , perform side oxidation on the multi-layer resonance cavity 103 in the first platform 11 , so that each oxide layer 1033 in each resonance cavity forms an oxidation hole 10330 .

Step S25, set a positive metal contact area 14 on one side of the first platform 11, and use dry etching to etch the upper DBR layer 105 from top to bottom at the position of the positive metal contact area 14 to adjacent to the first stop layer. Above the first stop layer 104, in step S250, the remaining vertical structural parts above the first stop layer 104 are wet-etched to the first stop layer 104 using an etching solution of NH ₄ OH: H ₂ O ₂ with a formula ratio of 1:10. , so that the upper part of the first high platform 11 forms a second high platform 12 with an area smaller than that of the first high platform 11 . In this embodiment, when the first stop layer 104 and the second stop layer 102 are made of InGaAsP material, HCL: H ₃ PO ₄ etchant can be used for wet etching; When the stop layer 102 is made of InP or InGaP material, H ₃ PO ₄ :H ₂ O ₂ :H ₂ O etching solution can be used for wet etching; when the first stop layer 104 and the second stop layer 102 are made of InP material, Wet etching can also be carried out using H ₂ SO ₄ : H ₂ O ₂ : H ₂ O etching solution or C ₆ H ₈ O ₇ : H ₂ O ₂ etching solution.

Step S26: While the positive metal contact layer 106 is disposed on the first stop layer 104 by sputtering, the negative metal contact layer 107 is disposed on the second stop layer 102 by sputtering. Accordingly, through the chemical interaction between the first stop layer 104 and the second stop layer 102 using phosphorus-containing materials and the etching liquid, the etching rate is slowed down and resonance of the upper DBR layer 105 and the multi-layer can be avoided during the etching process. The over-etching problem of the cavity 103 further improves the placement accuracy of the positive metal contact layer 106 and the negative metal contact layer 107, thereby ensuring the component current path from the positive metal contact layer 106 to the negative metal contact layer 107. The corresponding series resistor has a constant resistance value. Following the above, the series resistor resistance (R) of the element of the high-power surface-emitting laser structure 1 produced by this process method, excluding the capacitance value, can be shown in Figure 5 as R=R1 +Ra+R2, and R1 and R2 have extremely low resistance values because the first stop layer 104 and the second stop layer 102 are n/p-type heavily doped, which is beneficial to reducing the overall resistance value of the series resistor.

Furthermore, in order to solve the problem of high resistance of the multi-layer resonant cavity 103, the present invention further proposes a device structure that shares the substrate and is connected in parallel. This is continued in step S22: after the semiconductor structure 10 is epitaxially formed, the following steps are performed: S27: Etch the substrate 100 from top to bottom in the center of the semiconductor structure 10, and remove the lower DBR layer 101, the first stop layer 102, the multi-layer resonant cavity 103, and the second stop layer above the base 100. The epitaxial layer such as layer 102 and the upper DBR layer 105 is divided into two parts. Then, the two parts of the semiconductor structure 10 are processed through subsequent steps S23 to S26 to form two high-power surface-emitting laser structures 1 that share the substrate 100. In step S28, wiring is performed to connect the high-power surface-emitting laser structures 1 to each other. The positive metal contact layers 106 of the surface-emitting laser structure 1 are wired and connected to each other; the negative metal contact layers 107 of each high-power surface-emitting laser structure 1 are wired and connected to each other, so that the two high-power surface-emitting laser structures 1 It is connected in parallel as shown in Figure 6. In this way, through this parallel structure, when each of the multi-layer resonant cavities 103 of the high-power surface-emitting laser structure 1 has three layers of resonant cavities, the overall device will be able to obtain the equivalent of six layers of resonant cavities connected in series. The optical power of the structural components can be maintained at a relatively low component voltage, which is beneficial to reducing component energy consumption and meeting market application needs.

However, the above are only preferred embodiments of the present invention and are not intended to limit the scope of the present invention; therefore, equal changes and modifications made without departing from the spirit and scope of the present invention should be included in within the patent scope of this invention.

S10～S15: steps S20～S28: steps 1: High-power surface-emitting laser structure 10: Semiconductor structure 100:Substrate 101: Lower DBR layer 1010: Lower double layer stacking pair 102: Second stop layer 103:Multilayer resonance cavity 1030: Next batch of cladding layer 1031:Active layer 1032: Previous batch of cladding 1033:Oxide layer 10330: Oxidized holes 1034: Upper isolation layer 104: First stop layer 105: Go to DBR layer 1050: Upper double layer stacking pair 106: Positive metal contact layer 107: Negative metal contact layer 11:The first high platform 12:The second high platform 13: Negative metal contact area 14: Positive metal contact area

Figure 1 is a flow chart of a preferred embodiment of the present invention. Figure 2 is a schematic structural diagram of a preferred embodiment of the present invention. Figures 3A and 3B are flow charts of two preferred embodiments of the present invention. Figures 4A, 4B, 4C, 4D, and 4E are flow diagrams of the second preferred embodiment of the present invention. Figure 5 is a schematic diagram of the resistance state of the series resistor in the second preferred embodiment of the present invention. Figure 6 is a schematic diagram of a top view corresponding to a cross-section of a single-substrate dual-structure parallel-connected component according to two preferred embodiments of the present invention.

S10~S15: Steps

Claims (10)

A method for manufacturing a high-power surface-emitting laser with a low series resistance structure includes the following steps: Construct a design structure, which stacks a substrate, a lower DBR layer, a multi-layer resonant cavity and an upper DBR layer from bottom to top, wherein the multi-layer resonant cavity is provided with 2 to 9 resonant chambers, each of which resonates Each chamber is provided with an active layer, and the upper DBR layer is provided with 22-30 upper double-layer stacking pairs, and the lower DBR layer is provided with 32-40 lower double-layer stacking pairs; A heavily doped first stop layer and a second stop layer are arranged adjacent to the upper and lower parts of the multi-layer resonant cavity, wherein the first stop layer is located at the adjacent part below the upper DBR layer, and the second stop layer The setting position is located adjacent to the upper part of the lower DBR layer, thereby effectively reducing the resistance of the series resistor through the setting position of the first stop layer and the setting position of the second stop layer; According to the design structure, epitaxy forms a semiconductor structure; A negative metal contact area is provided on the ring side of the semiconductor structure, and the negative metal contact area is etched from top to bottom to the second stop layer to form a first platform in the center of the semiconductor structure; A positive metal contact area is provided on one side of the first high platform, and the positive metal contact area is etched from top to bottom to the first stop layer to form a second high platform on the first high platform, and the The area of the second raised platform is smaller than that of the first raised platform; and A positive metal contact layer is disposed on the first stop layer, and a negative metal contact layer is disposed on the second stop layer. The process method according to claim 1, wherein the first stop layer and the second stop layer are made of phosphorus-containing materials of InP, InGaP, GaAsP or AlGaAsP and are n/p type heavily doped to reduce the etching rate. The position accuracy of the positive metal contact layer and the negative metal contact layer is improved, thereby ensuring the accuracy of the resistance value of the series resistor. The process method as described in claim 2, wherein each upper double-layer stack pair is an Al _(0.9) Ga _(0.1) As/Al _(0.1) Ga _(0.9) As stack structure, and the first stop layer is provided When , the upper double-layer stacked pair adjacent to one of the multi-layer resonant cavities is replaced by an In _(x) Ga _(1-x) P/Al _(0.1) Ga _(0.9) As structure; each lower double-layer stacked pair They are Al _(0.9) Ga _(0.1) As/Al _(0.1) Ga _(0.9) As stack structures, and when the second stop layer is provided, the lower double-layer stack pair adjacent to one of the multi-layer resonance cavities is composed of In _(x) Ga _(1-x) P/Al _(0.1) Ga _(0.9) As structure is substituted, and X is 0.56~0.71. The manufacturing method as described in claim 3, wherein the negative metal contact region is provided on the ring side of the semiconductor structure, and the upper DBR layer and the third DBR layer and the third DBR layer are etched from top to bottom using a dry etching method at the position of the negative metal contact region. After a stop layer and the multi-layer resonant cavity are positioned adjacent to the second stop layer, wet etching is used to etch the remaining portion above the second stop layer to the second stop layer, so that the first stop layer is formed in the central portion of the semiconductor structure. a high platform; then, perform side oxidation on the multi-layer resonant cavity to form an oxidation hole in the oxide layer provided on the active layer in each resonant cavity, and set the positive electrode on one side of the first high platform For the metal contact area, use dry etching to etch the upper DBR layer from top to bottom to the position adjacent to the first stop layer, and then use wet etching to etch the remaining parts to the first stop layer. The second high platform is formed on the first high platform. The process method as claimed in claim 4, wherein an NH ₄ OH: H ₂ O ₂ etching liquid is used when etching to the stop layer using a wet etching method. The process method as described in claim 5, wherein when etching to the stop layer by wet etching, a NH ₄ OH: H ₂ O ₂ etching liquid with a formula ratio of 1:10 is used. The process method as described in claim 4, wherein when the first stop layer and the second stop layer made of InGaAsP material are etched using a wet etching method, an HCL:H ₃ PO ₄ etching liquid is used; When the first stop layer and the second stop layer are made of InP or InGaP material, H ₃ PO ₄ :H ₂ O ₂ :H ₂ O etching liquid is used. The process method as described in claim 4, wherein when the first stop layer and the second stop layer made of InP material are etched by wet etching, H ₂ SO ₄ : H ₂ O ₂ : H ₂ O is used to etch. liquid or C ₆ H ₈ O ₇ :H ₂ O ₂ etching liquid. A high-power surface-emitting laser structure manufactured using the process method described in claims 1 to 8. The high-power surface-emitting laser structure as claimed in claim 9, wherein when the semiconductor structure is epitaxially formed, the center of the semiconductor structure is etched from top to bottom onto the substrate, so that the shared structure can be made through subsequent processes. There are two high-power surface-emitting laser structures on the substrate, and the positive metal contact layers of each high-power surface-emitting laser structure are wired to each other; the negative metal contact layers of each high-power surface-emitting laser structure are wired to each other. Connect so that the two high-power surface-emitting laser structures are connected in parallel.