TW202407815A - 為了增加的訊號佈線容量採用焊盤金屬化層的封裝襯底、以及相關的積體電路（ｉｃ）封裝和製造方法 - Google Patents

為了增加的訊號佈線容量採用焊盤金屬化層的封裝襯底、以及相關的積體電路（ｉｃ）封裝和製造方法 Download PDF

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Publication number
TW202407815A
TW202407815A TW112108075A TW112108075A TW202407815A TW 202407815 A TW202407815 A TW 202407815A TW 112108075 A TW112108075 A TW 112108075A TW 112108075 A TW112108075 A TW 112108075A TW 202407815 A TW202407815 A TW 202407815A
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TW
Taiwan
Prior art keywords
metal
layer
pad
metallization layer
thickness
Prior art date
Application number
TW112108075A
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English (en)
Chinese (zh)
Inventor
瓊雷伊維拉爾巴 比奧
志杰 王
安尼奇 佩托
弘博 魏
Original Assignee
美商高通公司
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Application filed by 美商高通公司 filed Critical 美商高通公司
Publication of TW202407815A publication Critical patent/TW202407815A/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
TW112108075A 2022-03-25 2023-03-06 為了增加的訊號佈線容量採用焊盤金屬化層的封裝襯底、以及相關的積體電路（ｉｃ）封裝和製造方法 TW202407815A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/656,477 2022-03-25
US17/656,477 US20230307336A1 (en) 2022-03-25 2022-03-25 Package substrates employing pad metallization layer for increased signal routing capacity, and related integrated circuit (ic) packages and fabrication methods

Publications (1)

Publication Number Publication Date
TW202407815A true TW202407815A (zh) 2024-02-16

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW112108075A TW202407815A (zh) 2022-03-25 2023-03-06 為了增加的訊號佈線容量採用焊盤金屬化層的封裝襯底、以及相關的積體電路（ｉｃ）封裝和製造方法

Country Status (7)

Country Link
US (1) US20230307336A1 (cg-RX-API-DMAC10.html)
EP (1) EP4500590A1 (cg-RX-API-DMAC10.html)
JP (1) JP2025509901A (cg-RX-API-DMAC10.html)
KR (1) KR20240161103A (cg-RX-API-DMAC10.html)
CN (1) CN118786524A (cg-RX-API-DMAC10.html)
TW (1) TW202407815A (cg-RX-API-DMAC10.html)
WO (1) WO2023183692A1 (cg-RX-API-DMAC10.html)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20250309168A1 (en) * 2024-03-29 2025-10-02 Micron Technology, Inc. Semiconductor package having an array of multi-sized interconnect structures

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5150518B2 (ja) * 2008-03-25 2013-02-20 パナソニック株式会社 半導体装置および多層配線基板ならびにそれらの製造方法
US9603247B2 (en) * 2014-08-11 2017-03-21 Intel Corporation Electronic package with narrow-factor via including finish layer
US9431351B2 (en) * 2014-10-17 2016-08-30 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US9420695B2 (en) * 2014-11-19 2016-08-16 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor process
KR102065943B1 (ko) * 2015-04-17 2020-01-14 삼성전자주식회사 팬-아웃 반도체 패키지 및 그 제조 방법
US10475736B2 (en) * 2017-09-28 2019-11-12 Intel Corporation Via architecture for increased density interface
US11769719B2 (en) * 2018-06-25 2023-09-26 Intel Corporation Dual trace thickness for single layer routing
US20200027728A1 (en) * 2018-07-23 2020-01-23 Intel Corporation Substrate package with glass dielectric
US11488918B2 (en) * 2018-10-31 2022-11-01 Intel Corporation Surface finishes with low rBTV for fine and mixed bump pitch architectures
US11948877B2 (en) * 2020-03-31 2024-04-02 Qualcomm Incorporated Hybrid package apparatus and method of fabricating
US11605595B2 (en) * 2020-08-14 2023-03-14 Qualcomm Incorporated Packages with local high-density routing region embedded within an insulating layer

Also Published As

Publication number Publication date
CN118786524A (zh) 2024-10-15
WO2023183692A1 (en) 2023-09-28
US20230307336A1 (en) 2023-09-28
JP2025509901A (ja) 2025-04-11
EP4500590A1 (en) 2025-02-05
KR20240161103A (ko) 2024-11-12

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