TW202406068A - 半導體封裝裝置與半導體封裝裝置製造方法 - Google Patents
半導體封裝裝置與半導體封裝裝置製造方法 Download PDFInfo
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Abstract
一種半導體封裝裝置與半導體封裝裝置製造方法,包括線路重佈層、電子裝置、封膠層以及導電端子。線路重佈層具有第一面、相對於第一面的第二面、以及線路層。線路重佈層於第一面具有第一溝槽。電子裝置設置於第一溝槽並電性連接線路層。封膠層形成於線路重佈層的第一面以覆蓋電子裝置以及線路重佈層的第一面。多個導電端子設置於第二面,且與線路層電性連接。
Description
本申請有關於一種半導體封裝裝置和其製造方法,尤指一種在線路重佈層形成溝槽(trench)以容置電子裝置的半導體封裝裝置和其製造方法。
由於現有儀器設備的小型化需求不斷增加,要求各種器件的封裝尺寸儘量減小,才能滿足使用要求。因此,需要一種小型化封裝結構,通過這種結構不僅能夠進一步減小相關封裝尺寸,還能整合更多的功能。
有鑑於此,在本申請一實施例中,提供一種半導體封裝裝置與半導體封裝裝置製造方法,利用在線路重佈層形成溝槽以容置電子裝置,達到提高集成密度的目的。
本申請一實施例揭露一種半導體封裝裝置與半導體封裝裝置製造方法,包括線路重佈層、電子裝置、封膠層以及導電端子。線路重佈層具有第一面、相對於第一面的第二面、以及線路層,線路重佈層於上述第一面具有第一溝槽。電子裝置設置於第一溝槽並電性連接線路層。封膠層形成於線路重佈層的第一面以覆蓋電子裝置以及線路重佈層的第一面。多個導電端子設置於第二面,且與線路層電性連接。
本申請一實施例揭露一種半導體封裝裝置製造方法,包括:提供線路重佈層,其中上述線路重佈層具有第一面、相對於上述第一面的第二面、以及線路層,上述線路重佈層於上述第一面具有第一溝槽;設置第一電子裝置於上述第一溝槽並電性連接上述線路層;形成第一封膠層於上述線路重佈層的上述第一面以覆蓋上述第一電子裝置以及上述線路重佈層的上述第一面;及設置多個導電端子於上述第二面且與上述線路層電性連接。
根據本申請一實施例,上述線路重佈層於上述第二面具有第二溝槽。
根據本申請一實施例,更包括第二電子裝置,設置於上述第二溝槽。
根據本申請一實施例,上述第二電子裝置設置於上述多個導電端子之間。
根據本申請一實施例,更包括第二封膠層,上述第二封膠層覆蓋上述第二電子裝置以及上述線路重佈層的上述第二面。
根據本申請實施例,利用在線路重佈層形成溝槽,使得電子裝置或其他功能元件能夠內藏在線路重佈層中,可減少半導體封裝裝置的厚度,有效提高半導體封裝裝置的集成密度,達到半導體封裝裝置小型化的目的。
為了便於本領域普通技術人員理解和實施本申請,下面結合附圖與實施例對本申請進一步的詳細描述,應當理解,本申請提供許多可供應用的發明概念,其可以多種特定型式實施。熟悉此技藝之人士可利用這些實施例或其他實施例所描述之細節及其他可以利用的結構,邏輯和電性變化,在沒有離開本申請之精神與範圍之下以實施發明。
本申請說明書提供不同的實施例來說明本申請不同實施方式的技術特徵。其中,實施例中的各元件之配置係為說明之用,並非用以限制本申請。且實施例中圖式標號之部分重複,係為了簡化說明,並非意指不同實施例之間的關聯性。其中,圖示和說明書中使用之相同的元件編號係表示相同或類似之元件。本說明書之圖示為簡化之形式且並未以精確比例繪製。爲清楚和方便說明起見,方向性用語(例如頂、底、上、下以及對角)係針對伴隨之圖示說明。而以下說明所使用之方向性用語在沒有明確使用在以下所附之申請專利範圍時,並非用來限制本申請之範圍。
再者,在說明本申請一些實施例中,說明書以特定步驟順序說明本申請之方法以及(或)程序。然而,由於方法以及程序並未必然根據所述之特定步驟順序實施,因此並未受限於所述之特定步驟順序。熟習此項技藝者可知其他順序也為可能之實施方式。因此,於說明書所述之特定步驟順序並未用來限定申請專利範圍。再者,本申請針對方法以及(或)程序之申請專利範圍並未受限於其撰寫之執行步驟順序,且熟習此項技藝者可瞭解調整執行步驟順序並未跳脫本申請之精神以及範圍。
圖1顯示根據本申請一實施例所述的半導體封裝裝置的側視剖面圖。根據本申請一實施例所述的半導體封裝裝置10,包括線路重佈層12,封膠層14A、14B、電子裝置16A、16B、電子元件18A、18B以及導電端子19。線路重佈層12具有頂面(第一面)11A、位於頂面11A對側的底面(第二面)11B、以及線路層12A。根據本申請一實施例,線路重佈層12可以先在載體上逐層形成,待完成線路重佈層12後,再移除全部或部份的載體。線路重佈層12的形成可以涉及多個沈積或塗佈製程、多個圖案化製程及多個平坦化製程。沈積或塗佈製程可用於形成絕緣層或線路層12A。沈積或塗佈製程可以包括旋轉塗佈製程、電鍍製程(electroplating process)、化學鍍製程(electroless process)、化學氣相沈積(chemical vapor deposition,CVD)製程、物理氣相沈積(physical vapor deposition,PVD)製程、原子層沈積(atomic layer deposition,ALD)製程、或其他適用的製程及其組合。圖案化製程可用於圖案化所形成的絕緣層及線路層。圖案化製程可以包括光微影製程、能量束鑽孔製程(例如,雷射束鑽孔製程、離子束鑽孔製程或電子束鑽孔製程)、蝕刻製程、機械鑽孔製程或其他適用的製程及其組合。平坦化製程可用於為所形成的絕緣層及線路層提供平坦的頂表面,以利於後續的製程。平坦化製程可以包括機械研磨製程、化學機械研磨(chemical mechanical polishing,CMP)製程或其他適用的製程及其組合。另外,根據本申請一實施例,可透過機械鑽孔、蝕刻或雷射鑽孔等方式在線路重佈層10的表面11A以及表面11B的絕緣層中形成溝槽。
線路重佈層12還可以採用加成堆積製程(additive buildup process)形成,加成堆積製程可以包含一個或多個介電層與相應的導電圖案或跡線(trace)的線路層交替堆迭,導電圖案或跡線可將電跡線扇出電子裝置的佔用空間外,或將電跡線扇入電子裝置的佔用空間內。導電圖案可以使用電鍍製程或化學鍍製程等鍍覆製程來形成。導電圖案可以包括導電材料,例如銅或其它可鍍覆金屬。線路重佈層12的介電層可以由例如聚醯亞胺(PI)、苯並環丁烯(BCB)或聚苯並惡唑(PBO)等可光定義(photo-definable)的有機介電材料製成。在其他實施例中,線路重佈層12的介電材料也可以是無機介電層。無機介電層可以包括氮化矽(Si
3N
4)、氧化矽(SiO
2)或氮氧化矽(SiON)。無機介電層可以通過使用氧化或氮化製程生長無機介電層來形成。
另外,線路重佈層12的底面11B具有封膠層14B,封膠層14B上具有穿過封膠層14B的多個通孔。多個導電端子19的數目與封膠層14B的通孔對應,分別設置於通孔內並與線路層12A電性連接,導電端子19可通過植球作業(Ball Implantation)植接在線路重佈層12的底面11B,根據本申請一實施例所述的半導體封裝裝置10可利用這些導電端子19與外部裝置(如印刷電路板)電性連接。導電端子19可包括導電球、導電柱、導電凸塊、其組合、或藉由植球製程、無電鍍製程或其他合適製程形成的其他形式和形狀。根據本申請實施例,可選擇性地執行焊接(soldering)製程和回焊(reflowing)製程,以增強導電端子19和線路重佈層12之間的黏著性。根據本申請一實施例,封膠層14B的材料可為環氧樹脂(Expoxyresin)、氰酸脂(Cyanate Ester)、雙馬來醯亞胺三嗪、玻璃纖維、聚苯並㗁唑(polybenzoxazole)、聚醯亞胺(polyimide)、氮化物(例如,氮化矽)、氧化物(例如、氧化矽)、氮氧化矽、或類似絕緣材料,或混合環氧樹脂與玻璃纖維等絕緣有機材料或陶瓷材料所構成。
如圖1所示,線路重佈層12的頂面(第一面) 11A設置了電子裝置16A與電子元件18A,而線路重佈層12的底面(第二面) 11B在導電端子19之間設置了電子裝置16B與電子元件18B。在圖1中,僅顯示電子裝置16A、16B以及二個電子元件18A、18B,然而,實際數量並不限於此,本領域技術人員可根據實際需要設置特定個數的電子裝置16A、16B與電子元件18A、18B於線路重佈層12的頂面11A與底面11B。電子裝置16A、16B可為半導體晶粒、半導體晶片或包括多個電子裝置的封裝。電子裝置16A、16B可經由例如金線、銅線或鋁線等導電線連接到線路重佈層12的線路層12A。電子裝置16A可為有關於光電裝置(optoelectronic devices)、微機電系統(Micro-electromechanical Systems,MEMS)、功率放大晶片、電源管理晶片、生物辨識裝置、微流體系統(microfluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package,WSP)製程的影像感測裝置、發光二極體(light-emitting diodes,LEDs)、太陽能電池(solar cells)、加速計(accelerators)、陀螺儀(gyroscopes)、指紋辨識器、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片。電子元件18A、18B可電性連接到線路重佈層12的線路層12A。根據本申請一實施例,電子元件18A、18B可為無源器件(被動元件),例如電阻器、電容器、電感器、濾波器、振盪器等。在其他實施例中,電子元件18A還可以是端子。
電子裝置16A、16B與電子元件18A、18B可以倒裝方式設置於線路重佈層12,並與線路重佈層12中的線路層12A電性連接,此外,電子裝置16A、16B與電子元件18A、18B也可通過膠黏劑設置在線路重佈層12,並通過打線方式(Wire bonding)電性連接至線路重佈層12中的線路層12A,也就是本申請可實施於倒裝式封裝,也可實施於打線式封裝,此為本領域技術人員所能推知的等效實施。
根據本申請實施例,膠黏劑可包括聚醯亞胺(Polyimide,PI)、聚乙烯對苯二甲酸酯(Polyethylene Terephthalate,PET)、鐵氟龍(Teflon)、液晶高分子(Liquid Crystal Polymer,LCP)、聚乙烯(Polyethylene,PE)、聚丙烯(Polypropylene,PP)、聚苯乙烯(Polystyrene,PS)、聚氯乙烯(Polyvinyl Chloride,PVC)、尼龍(Nylon or Polyamides)、聚甲基丙烯酸甲酯(Polymethylmethacrylate,PMMA)、ABS塑膠(Acrylonitrile-Butadiene-Styrene)、酚樹脂(Phenolic Resins)、環氧樹脂(Epoxy)、聚酯(Polyester)、矽膠(Silicone)、聚氨基甲酸乙酯(Polyurethane,PU)、聚醯胺-醯亞胺(polyamide-imide,PAI)或其組合,但不限於此,只要具有黏著特性的材料皆可應用於本申請。
封膠層14A形成於線路重佈層12的頂面(第一面) 11A上,並包覆電子裝置16A與電子元件18A。根據本申請一實施例,封膠層14A的材料可為環氧樹脂(Expoxyresin)、氰酸脂(Cyanate Ester)、雙馬來醯亞胺三嗪、玻璃纖維、聚苯並㗁唑(polybenzoxazole)、聚醯亞胺(polyimide)、氮化物(例如,氮化矽)、氧化物(例如、氧化矽)、氮氧化矽、或類似絕緣材料,或混合環氧樹脂與玻璃纖維等絕緣有機材料或陶瓷材料所構成。
圖2A-圖2J顯示根據本申請一實施例所述的半導體封裝裝置的製造方法的剖面圖。參閱圖2A,首先提供線路重佈層12。線路重佈層12具有頂面(第一面)11A、位於表面11A對側的底面(第二面)11B、以及線路層12A。根據本申請一實施例,線路重佈層12可以先在載體上逐層形成,待完成線路重佈層12後,再移除全部或部份的載體。線路重佈層12的形成可以涉及多個沈積或塗佈製程、多個圖案化製程及多個平坦化製程。沈積或塗佈製程可用於形成絕緣層或線路層12A。沈積或塗佈製程可以包括旋轉塗佈製程、電鍍製程(electroplating process)、化學鍍製程(electroless process)、化學氣相沈積(chemical vapor deposition,CVD)製程、物理氣相沈積(physical vapor deposition,PVD)製程、原子層沈積(atomic layer deposition,ALD)製程、或其他適用的製程及其組合。圖案化製程可用於圖案化所形成的絕緣層及線路層。圖案化製程可以包括光微影製程、能量束鑽孔製程(例如,雷射束鑽孔製程、離子束鑽孔製程或電子束鑽孔製程)、蝕刻製程、機械鑽孔製程或其他適用的製程及其組合。平坦化製程可用於為所形成的絕緣層及線路層提供平坦的頂表面,以利於後續的製程。平坦化製程可以包括機械研磨製程、化學機械研磨(chemical mechanical polishing,CMP)製程或其他適用的製程及其組合。另外,根據本申請一實施例,可透過機械鑽孔、蝕刻或雷射鑽孔等方式在線路重佈層10的表面11A形成溝槽13A、13B以及表面11B的絕緣層中形成溝槽13C、13D。
線路重佈層12還可以採用加成堆積製程(additive buildup process)形成,加成堆積製程可以包含一個或多個介電層與相應的導電圖案或跡線(trace)的線路層交替堆迭,導電圖案或跡線可將電跡線扇出電子裝置的佔用空間外,或將電跡線扇入電子裝置的佔用空間內。導電圖案可以使用電鍍製程或化學鍍製程等鍍覆製程來形成。導電圖案可以包括導電材料,例如銅或其它可鍍覆金屬。線路重佈層12的介電層可以由例如聚醯亞胺(PI)、苯並環丁烯(BCB)或聚苯並惡唑(PBO)等可光定義(photo-definable)的有機介電材料製成。在其他實施例中,線路重佈層12的介電材料也可以是無機介電層。無機介電層可以包括氮化矽(Si
3N
4)、氧化矽(SiO
2)或氮氧化矽(SiON)。無機介電層可以通過使用氧化或氮化製程生長無機介電層來形成。
接下來,參閱圖2B,將電子裝置16A與電子元件18A分別設置於線路重佈層12的頂面11A中的溝槽13A、13B,在圖2B中,僅顯示單一電子裝置16A以及電子元件18A,然而,實際數量並不限於此,本領域技術人員可根據實際需要設置特定個數的電子裝置16A與電子元件18A。電子裝置16A可為半導體晶粒、半導體晶片或包括多個電子裝置的封裝。電子裝置16A可經由例如金線、銅線或鋁線等導電線連接到線路重佈層12的線路層12A。電子裝置16A可為有關於光電裝置(optoelectronic devices)、微機電系統(Micro-electromechanical Systems,MEMS)、功率放大晶片、電源管理晶片、生物辨識裝置、微流體系統(microfluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package,WSP)製程對影像感測裝置、發光二極體(light-emitting diodes,LEDs)、太陽能電池(solar cells)、加速計(accelerators)、陀螺儀(gyroscopes)、指紋辨識器、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片。電子元件18A可電性連接到線路重佈層12的線路層12A。根據本申請一實施例,電子元件18A可為無源器件(被動元件),例如電阻器、電容器、電感器、濾波器、振盪器等。在其他實施例中,電子元件18A還可以是端子。
電子裝置16A與電子元件18A可以倒裝方式設置於線路重佈層12的頂面(第一面) 11A中的溝槽13A、13B,並與線路重佈層12中的線路層12A電性連接,此外,電子裝置16A與電子元件18A也可通過膠黏劑設置在線路重佈層12的頂面(第一面) 11A中的溝槽13A、13B,並通過打線方式(Wire bonding)電性連接至線路重佈層12中的線路層12A,也就是本申請可實施於倒裝式封裝,也可實施於打線式封裝,此為本領域技術人員所能推知的等效實施。
根據本申請實施例,膠黏劑可包括聚醯亞胺(Polyimide,PI)、聚乙烯對苯二甲酸酯(Polyethylene Terephthalate,PET)、鐵氟龍(Teflon)、液晶高分子(Liquid Crystal Polymer,LCP)、聚乙烯(Polyethylene,PE)、聚丙烯(Polypropylene,PP)、聚苯乙烯(Polystyrene,PS)、聚氯乙烯(Polyvinyl Chloride,PVC)、尼龍(Nylon or Polyamides)、聚甲基丙烯酸甲酯(Polymethylmethacrylate,PMMA)、ABS塑膠(Acrylonitrile-Butadiene-Styrene)、酚樹脂(Phenolic Resins)、環氧樹脂(Epoxy)、聚酯(Polyester)、矽膠(Silicone)、聚氨基甲酸乙酯(Polyurethane,PU)、聚醯胺-醯亞胺(polyamide-imide,PAI)或其組合,但不限於此,只要具有黏著特性的材料皆可應用於本申請。接下來,將半成品進行烘烤以使得電子裝置16A與電子元件18A和線路重佈層12之間的膠黏劑固化以固定電子裝置16A與電子元件18A於溝槽13A、13B。
接下來,參閱圖2C,將封膠層14A形成於線路重佈層12的頂面(第一面) 11A上,並包覆電子裝置16A與電子元件18A。根據本申請一實施例,封膠層14A的材料可為環氧樹脂(Expoxyresin)、氰酸脂(Cyanate Ester)、雙馬來醯亞胺三嗪、玻璃纖維、聚苯並㗁唑(polybenzoxazole)、聚醯亞胺(polyimide)、氮化物(例如,氮化矽)、氧化物(例如、氧化矽)、氮氧化矽、或類似絕緣材料,或混合環氧樹脂與玻璃纖維等絕緣有機材料或陶瓷材料所構成。接下來,參閱圖2D,利用平坦化製程研磨封膠層14A以減少封膠層14A的厚度。根據本申請實施例,平坦化製程可以包括機械研磨製程、化學機械研磨(chemical mechanical polishing,CMP)製程或其他適用的製程及其組合。
接下來,參閱圖2E,將半成品翻轉使線路重佈層12的底面(第二面)11B朝上,然後將電子裝置16B與電子元件18B分別設置於線路重佈層12的底面11B中的溝槽13C、13D,在圖2E中,僅顯示單一電子裝置16B以及電子元件18B,然而,實際數量並不限於此,本領域技術人員可根據實際需要設置特定個數的電子裝置16B與電子元件18B。關於電子裝置16B與電子元件18B的種類以及安裝方式,可參考電子裝置16A與電子元件18A的做法,在此不予贅述以精簡說明。
接下來,參閱圖2F,將封膠層14B形成於線路重佈層12的底面(第二面) 11B上,並包覆電子裝置16B與電子元件18B。根據本申請一實施例,封膠層14B的材料可為環氧樹脂(Expoxyresin)、氰酸脂(Cyanate Ester)、雙馬來醯亞胺三嗪、玻璃纖維、聚苯並㗁唑(polybenzoxazole)、聚醯亞胺(polyimide)、氮化物(例如,氮化矽)、氧化物(例如、氧化矽)、氮氧化矽、或類似絕緣材料,或混合環氧樹脂與玻璃纖維等絕緣有機材料或陶瓷材料所構成。
接下來,參閱圖2G,將封膠層14B的一部分移除以形成通孔17。根據本申請實施例,可使用機械鑽孔、蝕刻或雷射鑽孔形成通孔17。接下來,參閱圖2H,將導電端子19形成在封膠層14B的通孔17中,以與線路重佈層12的線路層12A實體接觸,根據本申請一實施例所述的半導體封裝裝置可利用這些導電端子19與外部裝置(如印刷電路板)電性連接。導電端子19可包括導電球、導電柱、導電凸塊、其組合、或藉由植球製程、無電鍍製程或其他合適製程形成的其他形式和形狀。接下來,參閱圖2I,可選擇性地執行焊接(soldering)製程和回焊(reflowing)製程,以增強導電端子19和重佈線結構150之間的黏著性。最後,參閱圖2J,將半成品翻轉使線路重佈層12的頂面11A (第一面)朝上,即完成本申請實施例的半導體封裝裝置。
根據本申請實施例,利用在線路重佈層形成溝槽,使得電子裝置或其他功能元件能夠內藏在線路重佈層中,可減少半導體封裝裝置的厚度,有效提高半導體封裝裝置的集成密度,達到半導體封裝裝置小型化的目的。
綜上所述,本申請符合發明專利要件,爰依法提出專利申請。惟,以上該者僅爲本申請之較佳實施方式,本申請之範圍並不以上述實施方式爲限,舉凡熟悉本案技藝之人士爰依本申請之精神所作之等效修飾或變化,皆應涵蓋於以下申請專利範圍內。
10:半導體封裝裝置
11A:頂面
11B:底面
12:線路重佈層
12A:線路層
13A、13B、13C、13D:溝槽
14A、14B:封膠層
16A、16B:電子裝置
17:通孔
18A、18B:電子元件
19:導電端子
圖1顯示根據本申請一實施例所述的半導體封裝裝置的側視剖面圖。
圖2A-圖2J顯示根據本申請一實施例所述的半導體封裝裝置的製造方法的剖面圖。
無
10:半導體封裝裝置
11A:頂面
11B:底面
12:線路重佈層
12A:線路層
14A、14B:封膠層
16A、16B:電子裝置
18A、18B:電子元件
19:導電端子
Claims (10)
- 一種半導體封裝裝置,包括: 一線路重佈層,具有第一面、相對於上述第一面的第二面、以及線路層,其中上述線路重佈層於上述第一面具有第一溝槽; 一第一電子裝置,設置於上述第一溝槽並電性連接上述線路層; 一第一封膠層,上述第一封膠層形成於上述線路重佈層的上述第一面以覆蓋上述第一電子裝置以及上述線路重佈層的上述第一面;及 複數導電端子,設置於上述第二面,且與上述線路層電性連接。
- 如請求項1所述的半導體封裝裝置,其中上述線路重佈層於上述第二面具有第二溝槽。
- 如請求項2所述的半導體封裝裝置,更包括第二電子裝置,設置於上述第二溝槽。
- 如請求項3所述的半導體封裝裝置,其中上述第二電子裝置設置於上述多個導電端子之間。
- 如請求項3所述的半導體封裝裝置,更包括第二封膠層,上述第二封膠層覆蓋上述第二電子裝置以及上述線路重佈層的上述第二面。
- 一種半導體封裝裝置製造方法,包括: 提供一線路重佈層,其中上述線路重佈層具有第一面、相對於上述第一面的第二面、以及線路層,上述線路重佈層於上述第一面具有第一溝槽; 設置一第一電子裝置於上述第一溝槽並電性連接上述線路層; 形成一第一封膠層於上述線路重佈層的上述第一面以覆蓋上述第一電子裝置以及上述線路重佈層的上述第一面;及 設置複數導電端子於上述第二面且與上述線路層電性連接。
- 如請求項6所述的半導體封裝裝置製造方法,其中上述線路重佈層於上述第二面具有第二溝槽。
- 如請求項7所述的半導體封裝裝置製造方法,更包括設置第二電子裝置於上述第二溝槽。
- 如請求項8所述的半導體封裝裝置製造方法,其中上述第二電子裝置設置於上述多個導電端子之間。
- 如請求項8所述的半導體封裝裝置製造方法,更包括形成第二封膠層以覆蓋上述第二電子裝置以及上述線路重佈層的上述第二面。
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