TW202401550A - Method of manufacturing semiconductor device for reducing defect in array region - Google Patents

Abstract

A method of manufacturing the same is provided. The method includes providing a substrate. The method also includes forming a target layer over the substrate. The method further includes forming a patterned mask structure over the target layer. In addition, the method includes forming an etching stop layer over the patterned mask structure. The method also includes forming an underlayer over the etching stop layer; and performing an etching process to pattern the target layer.

Description

Preparation method of semiconductor element with reduced defects in array area

This application claims priority to U.S. Patent Application Nos. 17/852,424 and 17/853,609 (that is, the priority date is "June 29, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a method of manufacturing a semiconductor device. In particular, it relates to a method of manufacturing a semiconductor element that reduces defects in an array region.

With the rapid development of the electronics industry, the development of integrated circuits (ICs) has reached high performance and miniaturization. Technological advances in IC materials and design have produced several generations of ICs, each with smaller and more complex circuits than the previous generation.

A dynamic random access memory (DRAM) device is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Typically, a DRAM is arranged in a square array with one capacitor and one transistor per cell. A vertical transistor has been developed for 4F ² DRAM cells, where F represents the lithographic minimum feature width or critical dimension (CD). However, recently, as the pitch of insulating structures (such as shallow trench isolation) continues to shrink, DRAM manufacturers face a huge challenge in reducing the memory cell area. As a result of this reduction, electrical shorts may occur within an array region, which may adversely affect the performance of a semiconductor device.

The above description of "prior art" only provides background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" does not constitute the prior art of the present disclosure. should not be used as any part of this case.

An embodiment of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes providing a substrate. The preparation method also includes forming a target layer on the substrate. The preparation method also includes forming a patterned mask structure on the target layer. In addition, the preparation method includes forming an etching stop layer on the patterned mask structure. The preparation method also includes forming a lower layer on the etching stop layer; and performing an etching process to pattern the target layer.

Another embodiment of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes providing a substrate. The preparation method also includes forming a target layer on the substrate. The preparation method also includes forming a patterned mask structure on the target layer. In addition, the preparation method includes forming an etching stop layer on the patterned mask structure. The preparation method also includes forming a lower layer on the etching stop layer. The preparation method also includes obtaining a defect distribution map of a plurality of defects on the lower surface. In response to the defect distribution map of the defects, a process condition for forming the lower layer is adjusted.

Another embodiment of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes providing a substrate. The preparation method also includes forming a lower layer on the substrate. The preparation method also includes obtaining a defect distribution map of a plurality of defects on the lower layer. Forming the lower layer includes disposing the substrate in a semiconductor manufacturing tool; and forming the lower layer includes determining a relative position of the nozzle and the substrate based on the defect distribution pattern of the defects on the lower layer.

The embodiments of the present disclosure provide a method of manufacturing a semiconductor device. The preparation method includes forming a lower layer on a substrate. The preparation method includes obtaining a defect distribution pattern of defects on or within the lower layer. When it is detected that a density of defects within a unit area exceeds a predetermined value, an etching process or a process condition for forming the lower layer can be adjusted. As a result, defects on or within the underlying layer can be reduced, and electrical short circuits in the array region can be prevented.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

Specific examples of components and configurations are described below to simplify embodiments of the present disclosure. Of course, these embodiments are only for illustration and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, or may include an additional component formed between the first and second components. An embodiment such that the first and second components are not in direct contact. In addition, embodiments of the present disclosure may repeat reference numbers and/or letters in many examples. These repetitions are for simplicity and clarity and do not in themselves represent a specific relationship between the various embodiments and/or configurations discussed unless otherwise specified herein.

It will be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be either directly connected or coupled to the other element, or other intermediate components.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not governed by these terms. limits. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present progressive concept.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. exists, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.

It will be understood that in the description of the present disclosure, the term "about" is used to alter the amount of an ingredient, composition, or reactant of the present disclosure, meaning, for example, by typical measurements and liquid handling used to prepare concentrates or solutions. Quantity changes may occur due to the procedure. Furthermore, variations may result from inadvertent errors in measurement procedures, differences in the manufacture, source or purity of the ingredients used to make the compositions or practice the methods, and the like. In one aspect, the term "about" means within 10% of a reported value. In another aspect, the term "about" means within 5% of the reported value. Furthermore, in another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2 or 1% of the reported value.

FIG. 1 is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

In some embodiments, the preparation method 1 may start with step S11, in which a substrate is provided and an isolation layer and a capping layer are formed on the substrate.

In some embodiments, the preparation method 1 may continue with step S12, wherein a target layer is formed on the capping layer.

In some embodiments, the preparation method 1 may continue with step S13, wherein a patterned mask structure is formed on the target layer.

In some embodiments, Method 1 may continue with step S14, wherein an etch stop layer is formed on the patterned mask structure and a lower layer is formed on the etch stop layer.

In some embodiments, the preparation method 1 may continue with step S15, wherein an etching process is performed to pattern the target layer to form a patterned target layer.

In some embodiments, preparation method 1 may continue with step S16, in which a plurality of strips bounded by the target layer are formed.

In some embodiments, the preparation method 1 may continue with step S17, in which the isolation layer and the capping layer are patterned.

Preparation Method 1 is only an example, and is not intended to limit the present disclosure beyond the scope explicitly stated in the claims of the patent application. Additional steps may be provided before, during, or after each step of Preparation Method 1, and some of the steps described may be replaced, eliminated, or reordered for additional embodiments of the preparation method. In some embodiments, the preparation method 1 may include another step not shown in Figure 1 . In some embodiments, the preparation method 1 may include one or more steps illustrated in FIG. 1 .

2-18 are schematic diagrams illustrating one or more stages of an exemplary method for preparing a semiconductor device 100 according to some embodiments of the present disclosure.

Referring to Figure 2, a substrate 101 is provided or received. The substrate 101 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate 101 may include an elemental semiconductor including a single crystal, a polycrystalline or an amorphous form of silicon or germanium; a compound semiconductor material including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and at least one of indium antimonide; an alloy semiconductor material including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a gradient Ge feature, wherein the Si and Ge compositions change from one ratio at one location of the gradient SiGe feature to another ratio at another location of the gradient SiGe feature . In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy can be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate 101 may have a multi-layer structure, or the substrate 101 may include a multi-layer compound semiconductor structure.

In some embodiments, the substrate 101 defines a surrounding area 101c and an array area 101d, and the array area 101c is at least partially surrounded by the surrounding area 101c. In some embodiments, substrate 101 defines a boundary 101e between surrounding area 101c and array area 101d.

In some embodiments, surrounding area 101c may be used to form a logic element. Logic components may include a system-on-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a microcontroller, a radio frequency (RF) component, a sensor device component, a microelectromechanical system (MEMS) component, a digital signal processing (DSP) component, a front-end component, an analog front-end (AFE) component or other components.

The array area 101d can be used to form a memory device. For example, the memory device may include a dynamic random access memory (DRAM) device, a one-time programmable (OTP) memory device, a static random access memory (SRAM) device, or other suitable memory devices. .

Referring to FIG. 2 , an isolation layer 102 is formed on the substrate 101 . In some embodiments, isolation layer 120 is in contact with substrate 101 . In some embodiments, isolation layer 102 includes an oxide, such as silicon oxide. In some embodiments, the isolation layer 102 is formed using a chemical vapor deposition (CVD) process, a thermal oxidation process, or any other suitable process.

Referring to FIG. 2 , a capping layer 103 is formed on the isolation layer 102 . In some embodiments, capping layer 103 is formed on isolation layer 102 . In some embodiments, capping layer 103 includes a nitride, such as silicon nitride. In some embodiments, a CVD process or any other suitable process may be used to form the capping layer 103 .

Referring to FIG. 3 , a hard mask stack 105 is formed on the capping layer 103 . In some embodiments, hard mask stack 105 includes several layers stacked on top of each other. For example, the hard mask stack 105 may include a first layer 105a, a second layer 105b, a third layer 105c, a fourth layer 105d, a fifth layer 105e, and a sixth layer 105f. In some embodiments, the first layer 105a, the second layer 105b, the third layer 105c, the fourth layer 105d, the fifth layer 105e, and the sixth layer 105f are sequentially formed on the cap layer 103.

In some embodiments, first layer 105a may be formed on capping layer 103. In some embodiments, first layer 105a may include carbon. In some embodiments, the manufacturing technology of the first layer 105a may include a CVD process or any other suitable process. In some embodiments, second layer 105b may be formed on first layer 105a. In some embodiments, second layer 105b may include nitride. In some embodiments, the manufacturing technology of the second layer 105b may include a CVD process or any other suitable process. In some embodiments, the first layer 105a and the second layer 105b have mutually different compositions to enable selective etching of each other relative to each other.

In some embodiments, third layer 105c may be formed on second layer 105b. In some embodiments, third layer 105c includes polysilicon. In some embodiments, the manufacturing technology of the third layer 105c includes a CVD process or any other suitable process. In some embodiments, fourth layer 105d may be formed on third layer 105c. In some embodiments, fourth layer 105d includes an oxide, such as silicon oxide. In some embodiments, the fabrication technology of the fourth layer 105d includes a CVD process or any other suitable process. In some embodiments, deposition of the third layer 105c and the fourth layer 105d may be performed in situ to save processing time and reduce the possibility of contamination. As used herein, the term "in situ" is used to refer to a process in which the substrate 101 being processed is not exposed to an external ambient environment (eg, outside the processing system). In some embodiments, the fourth layer 105d may also be called a target layer.

In some embodiments, fifth layer 105e may be formed on fourth layer 105d. In some embodiments, fifth layer 105e includes carbon. In some embodiments, the fifth layer 105e may be a sacrificial layer. In some embodiments, a CVD process or any other suitable process may be used to form the fifth layer 105e. In some embodiments, after depositing the fifth layer 105e, a polishing process may be performed to obtain a flat surface.

In some embodiments, sixth layer 105f may be formed on fifth layer 105e. In some embodiments, sixth layer 105f may include a dielectric material such as nitride or oxynitride. In some embodiments, sixth layer 105f is an anti-reflective coating (ARC) layer. In some embodiments, the manufacturing technology of the sixth layer 105f may include a plasma enhanced CVD (PECVD) process.

Referring to FIG. 4 , a first photoresist 106 may be formed. In some embodiments, first photoresist 106 may be formed on hard mask stack 105 . In some embodiments, the first photoresist 106 may be patterned through a lithography process and an etching process. The lithography process may include photoresist coating (eg, spin coating), soft bake, mask alignment, exposure, post-exposure bake, photoresist development, rinsing, and drying (eg, hard bake). For example, the etching process may include dry etching, wet etching or other suitable processes.

In some embodiments, the first photoresist 106 may include a plurality of slots 106a disposed on the hard mask stack 105 . Slots 106a may be formed on the array area 101d. In some embodiments, some portions of the sixth layer 105f may be exposed through the first photoresist 106. In some embodiments, to eliminate problems associated with light reflection when exposing first photoresist 106, sixth layer 105f may be formed between fifth layer 105e and first photoresist 106. In some embodiments, the sixth layer 105f can stabilize an etch selectivity of the fifth layer 105e.

Referring to Figure 5, hard stings can be patterned onto the stack 105. In some embodiments, the hard mask stack 105 in the array region 101d of the substrate 101 may be patterned. In some embodiments, some portions of the fourth layer 105d, the fifth layer 105e, and the sixth layer 105f exposed through the first photoresist 106 may be removed. In some embodiments, after removing the portions of the fourth layer 105d, the fifth layer 105e, and the sixth layer 105f exposed through the first photoresist 106, the first photoresist 106 and the sixth layer 105 are removed. The remainder of 105f. In some embodiments, a patterned mask structure 105m may be formed. In some embodiments, patterned mask structure 105m may include multiple islands 1051. In some embodiments, each island may include portions of fifth layer 105e and fourth layer 105d. The patterned mask structure 105m may have a spacing D1 defined by a distance between the two islands 1051.

Referring to FIG. 6, an etch stop layer 107 may be formed on the fifth layer 105e. In some embodiments, etch stop layer 107 may be conformally formed on patterned mask structure 105m. In some embodiments, etch stop layer 107 may be conformally formed on island 1051 . In some embodiments, the etch stop layer may include silicon oxide, for example. In some embodiments, lower layer 108 may be formed on etch stop layer 107 . In some embodiments, lower layer 108 may include an anti-reflective coating (ARC) or other suitable material. For example, the manufacturing technology of the lower layer 108 may include a coating process.

Please refer to the enlarged view of a portion CC' in FIG. 7 shown in FIG. 7 and FIG. 8 to sequentially remove some portions of the etching stop layer 107 and the fifth layer 105e. In some embodiments, lower layer 108 may be removed. In some embodiments, the portions of the etch stop layer 107 may be removed by an etching process P1. In some embodiments, the etching process P1 may include a dry etching process. In some embodiments, some portions of etch stop layer 107 remain on fourth layer 105d. In some embodiments, some portions of the fourth layer 105d, some portions of the third layer 105c, and some portions of the second layer 105b in the array region 101d are sequentially removed. In this way, several strips 109 protruding from the second layer 105b are formed in the array area 101d. In some embodiments, a patterned fourth layer 1052 (or a patterned target layer) may be formed. The patterned fourth layer 1052 may have a pitch D2. In some embodiments, distance D1 may be different than distance D2. In some embodiments, distance D1 may be greater than distance D2.

Referring to FIG. 9, a seventh layer 110 may be formed on the fourth layer 105d and the etch stop layer 107. Then, an eighth layer 111 may be formed on the seventh layer 110. In some embodiments, the seventh layer 110 may fill gaps between the strips 109 . In some embodiments, seventh layer 110 may include carbon or other suitable materials. In some embodiments, the seventh layer 110 may be a sacrificial layer. In some embodiments, a CVD process or any other suitable process may be used to form the seventh layer 110 . In some embodiments, after depositing the seventh layer 110, a polishing process may be performed to obtain a flat surface.

In some embodiments, the eighth layer 111 may be formed on the seventh layer 110 . In some embodiments, eighth layer 111 may include a dielectric material, such as nitride or oxynitride. In some embodiments, the eighth layer 111 may be an anti-reflective coating (ARC) layer. In some embodiments, the manufacturing technology of the eighth layer 111 may include a plasma enhanced CVD (PECVD) process.

Referring to FIG. 10 , a second photoresist 112 may be formed on the eighth layer 111 . In some embodiments, the second photoresist 112 includes a first portion 112a and a plurality of second portions 112b. In some embodiments, the first portion 112a and the second portions 112b may be formed by removing portions of the second photoresist 112 to pattern the second photoresist 112 . In some embodiments, the second photoresist 112 may be patterned by lithography, etching, or any other suitable process. In some embodiments, first portion 112a may be formed within array region 101d. In some embodiments, the second portions 112b may be formed within the surrounding area 101c.

After the second photoresist 112 is disposed on the eighth layer 111, several removal steps are performed. Figures 11 to 17 are enlarged views of the portion DD' of Figure 10, showing the steps for removing the portion DD'.

Referring to FIG. 11 , the first part 112 a of the second photoresist 112 may cover the eighth layer 111 .

Referring to FIG. 12 , some portions of the eighth layer 111 and some portions of the seventh layer 110 exposed through the first portion 112 a of the second photoresist 112 are removed. In some embodiments, several openings 110a are formed. The opening 110a may penetrate the seventh layer 110. In some embodiments, the upper surface of the etch stop layer 107 may be exposed through the opening 110a. In some embodiments, the remaining portion of eighth layer 111 may be removed after opening 110a is formed.

In some embodiments, the eighth layer 111 may be removed by dry etching or any other suitable process. In some embodiments, the second photoresist 112 can be removed through an ashing process, a wet stripping process, or any other suitable process. In some embodiments, the second photoresist 112 may be chemically altered so that it no longer adheres to the remaining portion of the eighth layer 111 . In some embodiments, the remaining portion of eighth layer 111 may then be removed to expose the remaining portion of seventh layer 110 .

Referring to Figure 13, the remaining portion of seventh layer 110 can be removed and strip 109 can be exposed. In some embodiments, etch stop layer 107 may be exposed. In some embodiments, fourth layer 105d may be exposed. In some embodiments, the remaining portion of seventh layer 110 may be removed by dry etching or any other suitable process.

Referring to Figure 14, some portions of the second layer 105b may also be removed. In some embodiments, portions of the second layer 105b may be removed by dry etching or any other suitable process. In some embodiments, portions of second layer 105b may remain and be insulated from each other. In some embodiments, after further removing portions of the second layer 105b, the etch stop layer 107, the fourth layer 105d, and the third layer 105c are also removed. In some embodiments, a portion of an upper surface of one of the first layers 105a may be exposed.

Referring to Figure 15, some portions of the first layer 105a that are exposed through the remaining portions of the second layer 105b may be removed. In some embodiments, portions of the first layer 105a may be removed by dry etching or any other suitable process. In some embodiments, portions of first layer 105a may remain and be insulated from each other. In some embodiments, the remaining portions of the second layer 105b are removed after removing some portions of the first layer 105a.

Referring to FIG. 16 , portions of the capping layer 103 and portions of the isolation layer 102 exposed through the remaining portion of the first layer 105 a may be removed. In some embodiments, the portions of the capping layer 103 and the portions of the isolation layer 102 may be removed simultaneously, sequentially, or separately. In some embodiments, the portions of capping layer 103 may be removed, and then the portions of isolation layer 102 may be removed. In some embodiments, the portions of capping layer 103 may be removed by dry etching or any other suitable process. In some embodiments, the portions of isolation layer 102 may be removed by dry etching or any other suitable process.

Referring to FIG. 17 , portions of the substrate 101 exposed through the remaining portions of the isolation layer 102 , the remaining portions of the capping layer 103 , and the remaining portions of the first layer 105 a may be removed to form a plurality of fins protruding from the base 101 Item 101f. In some embodiments, these portions of substrate 101 may be removed by dry etching or any other suitable process. In some embodiments, fins 101f may be separated from each other.

Referring to Figure 18, an elongated component 101h and a plurality of blocks 101i can be formed. In some embodiments, elongate component 101h may surround fin 101f. A plurality of blocks 101i may be formed in the surrounding area 101c. In some embodiments, fin 101f, elongate member 101h, and block 101i may protrude from an upper surface of base 101. In some embodiments, fin 101f, elongated component 101h, and block 101i may be integrally formed.

In some embodiments, fins 101f may be arranged in an array or matrix. In some embodiments, the heights of the fins 101f may be consistent with each other. In some embodiments, the height of fin 101f may range from approximately 30 nm to approximately 200 nm. In some embodiments, a spacing between adjacent pairs of fins 101f may be uniform. In some embodiments, fin 101f may have a cylindrical shape. In some embodiments, a cross-section of the fin 101f may have a circular, oval, quadrilateral or polygonal shape.

In some embodiments, elongated component 101h may partially or completely surround fin 101f. In some embodiments, elongated component 101h surrounds fin 101f. In some embodiments, elongated component 101h may be at least partially disposed between two fins 101f.

In some embodiments, elongated component 101h may have a width ranging from about 100 nm to about 800 nm. In some embodiments, a distance between the elongated component 101h and the outermost one of the fins 101f may be in a range between 50 nm and 500 nm. In some embodiments, an upper cross-section of the elongated component 101h may be a strip, a frame, or a ring-shaped structure. In some embodiments, the height of fin 101f may be substantially the same as a height of elongated component 101h.

In some embodiments, block 101i may protrude from base 101 and be disposed in surrounding region 101c. In some embodiments, block 101i at least partially surrounds array region 101d. In some embodiments, the cross-section of block 101 may have a quadrilateral or polygonal shape. In some embodiments, block 101i may have a width that is significantly greater than the width of fin 101f. In some embodiments, the height of block 101i may be substantially the same as the height of fin 101f.

FIG. 19 is a schematic flowchart illustrating a method 2 for manufacturing a semiconductor device according to some embodiments of the present disclosure.

In some embodiments, the preparation method 2 may start with step S21, in which a substrate is placed into a semiconductor manufacturing tool.

In some embodiments, preparation method 2 may continue with step S22, in which a lower layer is coated on the substrate.

In some embodiments, the preparation method 2 may continue with step S23, which involves obtaining a defect distribution map of a plurality of defects on the lower layer.

In some embodiments, the preparation method 2 may continue with step S24, which includes adjusting a process condition for forming the lower layer in response to the defect distribution pattern of the defects.

Preparation method 2 is only an example, and is not intended to limit the present disclosure beyond the scope explicitly stated in the claims of the patent application. Additional steps may be provided before, during, or after each step of Preparation Method 1, and some of the steps described may be replaced, eliminated, or reordered for additional embodiments of the preparation method. In some embodiments, the preparation method 2 may include another step not shown in FIG. 19 . In some embodiments, the preparation method 2 may include one or more steps illustrated in Figure 19.

Figure 20 is a graph of a defect distribution map 200 of one of the defects. More specifically, the defect profile 200 is measured after forming a lower layer (eg, 108 in FIG. 6 ) on a substrate, which may correspond to the stages shown in FIG. 6 . After forming the layer on an etch stop layer (eg, 107 of FIG. 6 ), a plurality of defects 201 may be generated on or in the underlying layer.

The defect distribution map 200 can be divided into a first defect distribution area 210 and a second defect distribution area 220 . The defect density of the first defect distribution area 210 may be greater than the defect density of the second defect distribution area 220 . In some embodiments, the classification of the first defect distribution area 210 and the second defect distribution area 220 can be used to adjust an etching process (eg, P1 in FIG. 7 ) and/or a process condition for forming a lower layer. The etching process or adjustments to form the underlying layer are configured to reduce defects created on or within the underlying layer. In some embodiments, the defect distribution map 200 may be without the first defect distribution area 210 .

In some embodiments, the first defect distribution area 210 may include at least one aggregated defect. For example, the first defect distribution area 210 may include 1 aggregated defect, 5 aggregated defects, 10 aggregated defects, 50 aggregated defects, 100 aggregated defects or more. The aggregated defects in the second defect distribution area 220 are less than the aggregated defects in the first defect distribution area 210 . In some embodiments, the first defect distribution area 210 may be defined as an area where the density of the aggregated defects in the area is greater than a predetermined value.

In some embodiments, adjusting a process condition of an etch process for removing or patterning a lower layer and/or an etch stop layer may include adjusting and/or optimizing the process temperature of the etch process.

In some embodiments, adjusting a process condition of an etch process for removing or patterning a lower layer and/or an etch stop layer may include adjusting and/or optimizing a concentration of a reactive gas in the etch process. or pressure.

In some embodiments, adjusting a process condition for forming the lower layer may include adjusting and/or optimizing a thickness of the lower layer.

In some embodiments, adjusting a process condition for forming the lower layer may include adjusting and/or optimizing a uniformity of a thickness of the lower layer.

21-23 are schematic diagrams illustrating one or more stages of an exemplary method for preparing a semiconductor device according to some embodiments of the present disclosure.

Referring to FIG. 21, a substrate 401 may be disposed in a semiconductor manufacturing tool 310. The semiconductor manufacturing tool 310 may include a support 311 , a nozzle 312 and a displacement device 313 . It should be understood that semiconductor manufacturing tool 310 may include other elements or components therein. Semiconductor fabrication tool 310 may be used to coat a layer, such as an ARC layer, over substrate 401 . In some embodiments, semiconductor fabrication tool 310 may be used to perform a reduced resistor consumption (RRC) process. For example, semiconductor fabrication tool 310 may be used to form a lower layer (eg, 108 of FIG. 6) over an etch stop layer (eg, 107 of FIG. 6).

Support 311 may be used to support base 401 . The nozzle 312 may be signally connected to the displacement device 313 . Nozzle 312 may be used to spray material onto substrate 401 . The shifting device 313 can be used to adjust a relative position between the nozzle 312 and the substrate 401 .

Referring to FIG. 22 , according to some embodiments of the present disclosure, in response to the defect distribution map 200 of the defects 201 , the relative position between the nozzle 312 and the substrate 401 can be adjusted to optimize the process conditions for forming the lower layer. The defect distribution pattern 200 of the defects 201 can be obtained by a substrate having a layer (eg, bottom layer) formed thereon. The substrate can be placed into a defect inspection tool so that a defect map 200 can be generated.

In some embodiments, when the defect distribution map 200 includes a first defect distribution area 210, the shifting device 313 will shift the position of the nozzle 312. For example, when a density of aggregated defects greater than a predetermined value is detected, the moving device 313 will move the position of the nozzle 312 . In some embodiments, adjusting a relative position between the nozzle 312 and the substrate 401 may include generating a horizontal displacement X1 between the nozzle 312 and the substrate 401 . In some embodiments, adjusting a relative position between the nozzle 312 and the substrate 401 may include generating a vertical displacement Y1 between the nozzle 312 and the substrate 401 . In some embodiments, the horizontal displacement X1 and/or the vertical displacement Y1 may depend on the position of the first defect distribution area 210 . In some embodiments, the nozzle 312 may be moved over an area corresponding to the second defect distribution area 220 of the defect distribution map 200 . In some embodiments, the horizontal displacement X1 may range from about 1 mm to about 10 mm, such as 1 mm, 3 mm, 5 mm, 7 mm, 9 mm, or 10 mm. In some embodiments, vertical displacement Y1 may range from about 1 mm to about 10 mm, such as 1 mm, 3 mm, 5 mm, 7 mm, 9 mm, or 10 mm.

Referring to FIG. 23 , after adjusting the relative position between the substrate 401 and the layer 402 (eg, the lower layer), the layer 402 (eg, the lower layer) can be coated on the substrate 401 . In some embodiments, a process P2 may be performed to form the layer 402 . In some embodiments, process P2 may include coating, deposition, or other suitable processes.

FIG. 24 is a block diagram illustrating a semiconductor manufacturing system 300 according to some embodiments of the present disclosure.

The semiconductor manufacturing system 300 may include a semiconductor manufacturing tool 310 and 330, and a defect inspection tool 320. Semiconductor manufacturing tools 310 and 330 and defect inspection tool 320 may be coupled to a controller 350 via a network 340 .

Semiconductor fabrication tool 310 may be used to form a lower layer, such as lower layer 108 shown in FIG. 6 . The defect inspection tool 320 can be used to detect defects on or within the underlying layer and generate a defect distribution map (eg, 200 of Figure 20). Semiconductor manufacturing tool 330 may be used to perform an etching process (eg, P1 of FIG. 7 ) to remove the underlying layer.

Network 340 may be the Internet or an intranet implementing a network protocol such as Transmission Control Protocol (TCP). Through the network 340 , the semiconductor manufacturing tools 310 and 330 and the defect inspection tool 320 may download or upload information about the wafers or the work-in-progress (WIP) of the semiconductor manufacturing tools from the controller 350 to the controller 350 .

Controller 350 may include a processor, such as a central processing unit (CPU), to determine adjustments to process conditions performed by semiconductor manufacturing tools 310 and/or 330 based on defect inspection tool 320 . In some embodiments, controller 350 may be used to determine the thickness and/or thickness uniformity of a layer (eg, a sublayer). For example, controller 350 may determine a displacement between a substrate and a nozzle of semiconductor manufacturing tool 310 . In some embodiments, the controller 350 may determine a horizontal displacement and/or a vertical displacement between the substrate and the nozzle. In some embodiments, controller 350 may determine a process condition of semiconductor manufacturing tool 330 to optimize the etching process.

Although FIG. 24 does not show any other semiconductor manufacturing tool prior to semiconductor manufacturing tool 310, the illustrated embodiment is not intended to be limiting. In other example embodiments, various types of semiconductor manufacturing tools may be arranged before semiconductor manufacturing tool 310 and may be used to perform various processes according to design requirements.

In the illustrated embodiment, substrate 401 is transferred to semiconductor manufacturing tool 310 to begin a series of different processes. Substrate 401 may be processed through various stages of forming at least one layer of material. The illustrative embodiments are not intended to limit the processing of substrate 401. In other example embodiments, the substrate 401 may include various layers prior to transferring the substrate 401 to the semiconductor manufacturing tool 310, or at any stage between product start and completion. In an exemplary embodiment, the substrate 401 may pass through the semiconductor manufacturing tool 310 , the defect inspection tool 320 , and the semiconductor manufacturing tool 330 in sequence.

FIG. 25 is a block diagram illustrating the hardware of a semiconductor manufacturing system 500 according to some embodiments of the present disclosure.

The processes shown in Figures 21-23 may be implemented in a controller 350 or a computing system that organizes wafer fabrication by controlling each part or portion of fabrication equipment in the facility. FIG. 25 is a block diagram illustrating the hardware of a semiconductor manufacturing system 500 according to some embodiments of the present disclosure. System 500 includes a hardware processor 501 and one or more of a non-transitory computer-readable storage medium 503 that stores program code (i.e., a set of executable instructions). Encoding. The computer-readable storage medium 503 may also be used to encode a plurality of instructions connected to manufacturing equipment for producing semiconductor components. The processor 501 is electrically coupled to the computer-readable storage medium 503 through a bus 505 . The processor 501 is also electrically coupled to the I/O interface 507 through the bus 505 . A network interface 509 is also electrically connected to the processor 501 via the bus 505 . The network interface is connected to a network so that the processor 501 and the computer-readable storage medium 503 can be connected to external components via the network 340 . Processor 501 is configured to execute computer code encoded in computer-readable storage medium 505 such that system 500 may be used to perform some or all of the steps described in the method illustrated in Figures 21-23.

In some example embodiments, processor 501 may be a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit, but not Not limited to this. Various circuits or units are within the intended scope of this disclosure.

In some exemplary embodiments, the computer-readable storage medium 503 may be an electronic, magnetic, optical, electromagnetic, infrared and/or a semiconductor system (or equipment or device), but is not limited thereto. For example, the computer-readable storage medium 503 includes a semiconductor or solid-state memory, a magnetic tape, a removable computer floppy disk, a random access memory (RAM), a read-only memory (ROM), a hard disk drive. disc and/or an optical disc. In one or more exemplary embodiments using optical discs, the computer-readable storage medium 503 also includes a compact disc read-only memory (CD-ROM), a compact disc read/write (CD-R/W), and/or A digital video disc (DVD).

In some example embodiments, storage medium 503 stores computer code configured to cause system 500 to perform the preparation methods shown in Figures 21-23. In one or more exemplary embodiments, the storage medium 501 also stores information required to perform the preparation methods shown in Figures 21-23 and in executing these methods and/or a set of executable instructions to perform the preparation methods shown in Figures 21-23 Information generated during the steps of the preparation method. In some example embodiments, a user interface 510, such as a graphical user interface (GUI), may be provided for a user to operate on the system 500.

In some example embodiments, storage medium 503 stores a plurality of instructions for interfacing with external machines. These instructions enable processor 501 to generate external machine-readable instructions to effectively implement the preparation methods shown in Figures 21-23 during analysis.

System 500 includes input/output (I/O) interface 507 . I/O interface 507 is coupled to external circuitry. In some example embodiments, I/O interface 507 may include a keyboard, keypad, mouse, trackball, trackpad, touch screen, and/or cursor direction keys for transmitting information and commands to processor 501 , but not limited to this.

In some example embodiments, I/O interface 507 may include a display, such as a cathode ray tube (CRT), liquid crystal display (LCD), a speaker, or the like. For example, the monitor displays data.

System 500 may also include a network interface 509 coupled to processor 501 . Network interface 509 allows system 500 to communicate with network 340 to which one or more other computer systems are connected.

Another embodiment of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes providing a substrate. The preparation method also includes forming a target layer on the substrate. The preparation method also includes forming a patterned mask structure on the target layer. In addition, the preparation method includes forming an etching stop layer on the patterned mask structure. The preparation method also includes forming a lower layer on the etching stop layer. The preparation method also includes obtaining a defect distribution map of a plurality of defects on the lower surface. In response to the defect distribution map of the defects, a process condition for forming the lower layer is adjusted.

Another embodiment of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes providing a substrate. The preparation method also includes forming a lower layer on the substrate. The preparation method also includes obtaining a defect distribution map of a plurality of defects on the lower layer. Forming the lower layer includes disposing the substrate in a semiconductor manufacturing tool; and forming the lower layer includes determining a relative position of the nozzle and the substrate based on the defect distribution pattern of the defects on the lower layer.

The embodiments of the present disclosure provide a method of manufacturing a semiconductor device. The preparation method includes forming a lower layer on a substrate. The preparation method includes obtaining a defect distribution pattern of defects on or within the lower layer. When it is detected that a density of defects within a unit area exceeds a predetermined value, an etching process or a process condition for forming the lower layer can be adjusted. As a result, defects on or within the underlying layer can be reduced, and electrical short circuits in the array region can be prevented.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.

1: Preparation method 2: Preparation method 100:Semiconductor components 101: Base 101c: Surrounding area 101d:Array area 101e:Border 101f: Fins 101h: Slender components 101i:Block 102:Isolation layer 103:Cover layer 105: Hard mask stacking 1051:Island 1052: Patterned fourth layer 105a:First floor 105b:Second floor 105c:Third floor 105d:Fourth floor 105e:Fifth floor 105f:Sixth floor 105m: Patterned mask structure 106:First photoresist 106a:Slot 107: Etch stop layer 108:Lower level 109:With body 110:Seventh floor 110a:Open your mouth 111:Eighth floor 112: Second photoresist 112a:Part 1 112b:Part 2 200: Defect distribution map 201: Defect 210: First defect distribution area 220: Second defect distribution area 300:Semiconductor Manufacturing Systems 301:Semiconductor Manufacturing Tools 310:Semiconductor Manufacturing Tools 311:Support 312:Nozzle 313: Shifting device 320: Defect inspection tool 330:Semiconductor Manufacturing Tools 340:Internet 350:Controller 401: Base 402:Layer 500: Semiconductor Manufacturing Systems 501: Hardware processor 503: Computer readable storage media 505:Bus 507:I/O interface 509:Network interface 510:User interface CC′: part D1: spacing D2: spacing DD′: part P1: Etching process P2:Process S11: Steps S12: Steps S13: Steps S14: Steps S15: Steps S16: Steps S17: Steps S21: Steps S22: Steps S23: Steps S24: Steps X1: Horizontal displacement Y1: vertical displacement

A more complete understanding of the present disclosure can be obtained by referring to the detailed description and claimed claims. The present disclosure should also be understood to be associated with the drawing element numbering, which represents similar elements throughout the description. FIG. 1 is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 2 is a schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. 3 is a schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. 4 is a schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 5 is a schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 6 is a schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. 7 is a schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 8 is an enlarged schematic diagram illustrating part CC′ of the semiconductor device shown in FIG. 7 . 9 is a schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 10 is a schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 11 is an enlarged schematic diagram illustrating part DD′ of the semiconductor device shown in FIG. 10 . 12 is a schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. 13 is a schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. 14 is a schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. 15 is a schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. 16 is a schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. 17 is a schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. 18 is a schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 19 is a schematic flowchart illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 20 is a schematic distribution diagram illustrating a defect distribution diagram of defects in one or more embodiments of the present disclosure. 21 is a schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. 22 is a schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. 23 is a schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 24 is a block diagram illustrating a semiconductor manufacturing system according to some embodiments of the present disclosure. FIG. 25 is a block diagram illustrating the hardware of a semiconductor manufacturing system according to some embodiments of the present disclosure.

101: Base

102:Isolation layer

103:Cover layer

105a:First floor

105b:Second floor

105c:Third floor

105d:Fourth floor

107: Etch stop layer

110:Seventh floor

110a:Open your mouth

112a:Part 1

Claims (20)

A method for preparing semiconductor components, including: provide a base; forming a target layer on the substrate; forming a patterned mask structure on the target layer; forming an etch stop layer on the patterned mask structure; forming a lower layer on the etch stop layer; and An etching process is performed to pattern the target layer. The preparation method as described in claim 1 also includes: Obtaining a defect distribution map of a plurality of defects on the underlying layer; and A process condition of the etching process is adjusted in response to the defect distribution map of the defects. The preparation method as described in claim 2 also includes: Obtaining a defect distribution map of a plurality of defects on the underlying layer; and A process condition for forming the lower layer is adjusted in response to the defect distribution map of the defects. The preparation method as described in claim 3, wherein adjusting a process condition for forming the lower layer includes: Optimize a uniformity of thickness of the underlying layer. The preparation method as described in claim 3, wherein adjusting a process condition for forming the lower layer includes: Optimize a thickness of the lower layer. The preparation method as described in claim 3, wherein forming the lower layer includes: disposing the substrate in a semiconductor manufacturing tool; Determine a relative position of a nozzle and the substrate. The preparation method as described in claim 6 also includes: Obtain a first defect distribution area and a second defect distribution area of the defect distribution map, wherein a first defect density of the first defect distribution area is greater than a second defect density of the second defect distribution area; and The relative position of the nozzle and the substrate is determined based on the first defect distribution area and the second defect distribution area of the defect distribution map. The preparation method as claimed in claim 1, wherein the lower layer includes an anti-reflective coating layer. The preparation method as claimed in claim 1, wherein the etching process includes a dry etching process. The preparation method as claimed in claim 1, wherein patterning the target layer includes: remove this lower layer; Remove the patterned mask structure; removing the etch stop layer; and Remove part of the target layer. The preparation method as claimed in claim 10, wherein a part of the etching stop layer remains on the target layer. A method for preparing semiconductor components, including: provide a base; forming a target layer on the substrate; forming a patterned mask structure on the target layer; forming an etch stop layer on the patterned mask structure; forming a lower layer on the etch stop layer; Obtaining a defect distribution map of a plurality of defects on the bottom; and In response to the defect distribution map of the defects, a process condition for forming the lower layer is adjusted. The preparation method as claimed in claim 12, wherein adjusting a process condition for forming the lower layer includes: Optimize a uniformity of thickness of the underlying layer. The preparation method as claimed in claim 12, wherein adjusting a process condition for forming the lower layer includes: Optimize a thickness of the lower layer. The preparation method as claimed in claim 14, wherein forming the lower layer includes: disposing the substrate in a semiconductor manufacturing tool; Determine a relative position of a nozzle and the substrate. . The preparation method as described in claim 15 also includes: Obtain a first defect distribution area and a second defect distribution area of the defect distribution map, wherein a first defect density of the first defect distribution area is greater than a second defect density of the second defect distribution area; and The relative position of the nozzle and the substrate is determined based on the first defect distribution area and the second defect distribution area of the defect distribution map. The preparation method of claim 12, wherein the lower layer includes an anti-reflective coating layer. The preparation method as claimed in claim 1, wherein the etching process includes a dry etching process. The preparation method as claimed in claim 12, wherein patterning the target layer includes: remove this lower layer; Remove the patterned mask structure; removing the etch stop layer; and Remove part of the target layer. The preparation method as claimed in claim 19, wherein a part of the etching stop layer remains on the target layer.

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