TW202349580A - Electronic device and manufacturing method thereof - Google Patents

Abstract

An electronic device and a manufacturing method thereof are provided. The electronic device includes an electronic unit, a first insulating layer, a second insulating layer and a connecting element. The electronic unit includes a first surface, a second surface opposite to the first surface, and a first side surface connecting the first surface and the second surface. The first insulating layer is disposed on the second surface. The second insulating layer is disposed on the first insulating layer. The second insulating layer includes a third surface, a fourth surface opposite to the third surface, and a second side surface connecting the third surface and the fourth surface. The connecting element is disposed on the second insulating layer and is electrically connected to the electronic unit. The third surface of the second insulating layer is in contact with the second surface of the electronic unit.

Description

Electronic device and manufacturing method thereof

The present disclosure relates to an electronic device and a manufacturing method thereof, and in particular to an electronic device including a first insulating layer and a second insulating layer and a manufacturing method thereof.

Generally speaking, a packaging process is performed on the electronic unit so that the electronic unit can resist pollutants in the external environment, avoid damage to the electronic unit due to manual operations, achieve fixed functions and/or achieve heat dissipation functions, thereby improving the electronics The reliability and/or other electrical performance of the unit.

In the current packaging process, the above-mentioned advantages of the packaging process are often achieved by disposing a protective layer on the electronic unit. However, as users' demands for electronic devices increase, the sizes of electronic units and their components are gradually reduced. Directly setting a protective layer on a small-sized electronic unit will lead to insufficient circuit design space, easy circuit breakage, easy short circuit, easy generation of leakage current, and many other problems.

Therefore, although existing electronic devices and their manufacturing methods have gradually met their intended uses, they have not yet fully met the requirements in all aspects. Therefore, there are still some problems to be overcome regarding electronic devices and methods of manufacturing them.

In some embodiments, an electronic device is provided. The electronic device includes an electronic unit, a first insulating layer, a second insulating layer and a connecting element. The electronic unit includes a first surface, a second surface opposite to the first surface, and a first side surface connecting the first surface and the second surface. The first insulation layer is disposed on the second surface. The second insulating layer is disposed on the first insulating layer. The second insulating layer includes a third surface, a fourth surface opposite the third surface, and a second side surface connecting the third surface and the fourth surface. The connection element is disposed on the second insulation layer and is electrically connected to the electronic unit. The third surface of the second insulating layer is in contact with the second surface of the electronic unit.

In some embodiments, methods of manufacturing electronic devices are provided. The manufacturing method includes providing a substrate. The substrate includes a plurality of electronic units. A first insulating layer is provided on the substrate. A second insulating layer is provided on the substrate. Wherein, the second insulating layer is in contact with a part of the surface of the plurality of electronic units.

The electronic device of the present disclosure can be applied in various types of electronic equipment. In order to make the features and advantages of the present disclosure more obvious and understandable, various embodiments are listed below and described in detail with reference to the accompanying drawings.

The following is a detailed description of the electronic devices of each embodiment of the present disclosure. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific components and arrangements described below are only used to briefly and clearly describe some embodiments of the present disclosure. Of course, these are only examples and do not limit the present disclosure. In addition, similar and/or corresponding element symbols may be used to identify similar and/or corresponding elements in different embodiments to clearly describe the present disclosure. However, the use of these similar and/or corresponding element symbols is only for the purpose of simply and clearly describing some embodiments of the present disclosure, and does not imply any correlation between the different embodiments and/or structures discussed.

It should be understood that relative terms, such as "lower" or "bottom" or "higher" or "top" may be used in various embodiments to describe the relative relationship of one element of the drawings to another element. . It will be understood that if the device in the figures is turned upside down, elements described as being on the "lower" side would then be elements described as being on the "higher" side. The embodiments of the present disclosure can be understood together with the drawings, and the drawings of the present disclosure are also regarded as part of the disclosure description.

Furthermore, when it is said that a first material layer is located on or above a second material layer, it may include the situation of direct contact between the first material layer and the second material layer or the situation between the first material layer and the second material layer. There may not be direct contact, that is, there may be one or more other material layers separated between the first material layer and the second material layer. However, if the first material layer is directly located on the second material layer, it means that the first material layer and the second material layer are in direct contact.

In addition, it should be understood that ordinal numbers such as "first", "second", etc. used in the description and claims are used to modify elements and are not intended to imply or represent the (or the) elements themselves. The components have any previous serial numbers, which do not represent the order of one component with another component, or the order of the manufacturing method. The use of these serial numbers is only used to make a component with a certain name and another component with the same name Components can be clearly distinguished. The same words may not be used in the patent scope and the description. For example, the first element in the description may be the second element in the patent scope.

In some embodiments of the present disclosure, terms related to joining and connecting, such as "connection", "interconnection", "joining", etc., unless otherwise defined, may mean that two structures are in direct contact, or may also refer to two structures. There is no direct contact, there are other structures placed between the two structures. And the terms about joining and connecting can also include the situation where both structures are movable, or both structures are fixed. In addition, the terms "electrical connection" or "electrical coupling" include any direct and indirect means of electrical connection.

In this context, the terms "about", "approximately" and "substantially" usually mean within 10%, or within 5%, or within 3%, or within 2%, or 1% of a given value or range. Within %, or within 0.5%. The quantities given here are approximate quantities. That is to say, without specifically stating "about", "approximately" and "substantially", the terms "about", "approximately" and "substantially" can still be implied. meaning. The term "range between a first value and a second value" means that the range includes the first value, the second value, and other values therebetween. Furthermore, any two numerical values or directions used for comparison may have certain errors. If the first value is equal to the second value, it implies that the first value and the second value may be within about 10%, or within 5%, or within 3%, or within 2%, or within 1%. Error within, or within 0.5%; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

Furthermore, it should be understood that according to the embodiments of the present disclosure, a scanning electron microscope (SEM), an optical microscope (OM), a film thickness profiler (α-step), and an ellipsometer can be used. Thickness gauge, or other suitable means to measure the width, thickness or height of each component, and the spacing or distance between components. Specifically, according to some embodiments, a scanning electron microscope can be used to obtain a cross-sectional structural image including the components to be measured, and measure the width, thickness, height or angle of each component, and the spacing or distance between components.

Throughout this disclosure and claims, certain words are used to refer to specific elements. It will be understood by those of ordinary skill in the art that manufacturers of electronic equipment may refer to the same component by different names. This article is not intended to differentiate between components that have the same function but have different names. In the following description and patent application, words such as "include", "contains", and "have" are open-ended words, so they should be interpreted as meaning "including but not limited to...". Therefore, when the terms "comprises," "containing," and/or "having" are used in the description of the present disclosure, they specify the presence of the corresponding features, regions, steps, operations, and/or elements, but do not exclude the presence of one or more the existence of corresponding features, regions, steps, operations and/or components.

It should be understood that the following embodiments can be replaced, reorganized, and combined with features of several different embodiments without departing from the spirit of the present disclosure to complete other embodiments. The features of various embodiments may be combined and used in any combination as long as they do not violate the spirit of the invention or conflict with each other.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted to have a meaning consistent with the relevant technology and the background or context of the present disclosure, and should not be interpreted in an idealized or overly formal manner. Unless otherwise defined in the embodiments of the present disclosure.

In this article, each direction is not limited to the three axes of the rectangular coordinate system, such as the X-axis, the Y-axis, and the Z-axis, and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For convenience of explanation, in the following, the X-axis direction is the first direction D1 (width direction), and the Z-axis direction is the second direction D2 (thickness direction). In some embodiments, the cross-sectional schematic diagrams described herein are schematic diagrams looking at the XZ plane.

In the present disclosure, the electronic device may include a display device, a lighting device, an antenna device, a sensing device or a titling device, but is not considered to be a limit. The electronic device may be a foldable or flexible electronic device. The display device may be a non-self-luminous display device or a self-luminous display device. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device, and the sensing device may be a sensing device that senses capacitance, light, heat energy or ultrasonic waves, but is not limited thereto. In the present disclosure, the electronic device may include an electronic unit. The electronic unit is, for example, a known good die (KGD) (that is, a known good wafer), a semiconductor wafer or a diode, but is not limited thereto. The electronic unit may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. Diodes may include light emitting diodes or photodiodes. The light emitting diode may include, for example, an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro light emitting diode (micro LED) or a quantum dot light emitting diode (quantum LED). dot LED), but not limited to this. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device can be any combination of the above, but is not limited thereto. The disclosure will be described below with an electronic device including an electronic unit, but the disclosure is not limited thereto.

In addition, the shape of the electronic device may be a rectangular shape, a circular shape, a polygonal shape, a shape with curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a processing system, a drive system, a control system, a light source system, a shelf system, etc. to support the electronic device or splicing device. It should be noted that the electronic device can be any combination of the above, but is not limited thereto.

It should be understood that in some embodiments, additional operational steps may be provided before, during, and/or after the method of manufacturing the electronic device. In some embodiments, some of the steps described may be replaced or omitted, and the order of some of the steps described is interchangeable. Furthermore, it should be understood that some of the recited steps may be substituted or deleted for other embodiments of the method.

In some embodiments, the manufacturing method of the electronic device of the present disclosure is suitable for a chip first process and a redistribution layer first (RDL first) process. In some embodiments, the manufacturing method of the electronic device of the present disclosure is suitable for face up processes and face down processes. For ease of explanation, in the following, a face-down wafer-first process is used as an example, but the present disclosure is not limited thereto. In addition, in the present disclosure, the number and size of each element in the drawings are only for illustration and are not used to limit the scope of the present disclosure.

Referring to FIG. 1 , which is a schematic cross-sectional view of an electronic device in an intermediate manufacturing stage according to some embodiments of the present disclosure. As shown in FIG. 1 , a substrate SB is provided, and the substrate SB includes a plurality of electronic units 10 . In some embodiments, the substrate SB may be a silicon wafer, a semiconductor on insulator (SOI) substrate, other suitable substrates, or a combination of the foregoing, but the disclosure is not limited thereto. The individual electronic units 10 are isolated from each other by a dotted line CL1, where the dotted line CL1 is, for example, a virtual first cutting line CL1, and a cutting process will be used in subsequent processes to separate each electronic unit 10 from the rest along the virtual first cutting line CL1. Subsequently formed parts.

In some embodiments, each of the plurality of electronic units 10 may include light-emitting elements such as pixels, light-emitting diodes, and photodiodes; conductive elements such as metal layers, wires, vias, and bonding pads; such as electrical Crystal driving elements; functional layers such as insulating layers, interlayer dielectric layers, passivation layers, planarization layers, dielectric materials; other suitable components, or combinations of the foregoing, but the disclosure is not limited thereto. In some embodiments, the electronic unit 10 may be a die, a chip unit, other suitable units, or a combination of the foregoing, but the disclosure is not limited thereto. In some embodiments, the electronic unit 10 may include a bottom surface 10B (first surface), a top surface 10T (second surface) opposite the bottom surface 10B, and side surfaces 10S connecting the bottom surface 10B and the top surface 10T.

In some embodiments, as shown in FIG. 1 , the substrate SB may include at least two electronic units 10 , but the present disclosure is not limited thereto. For example, the substrate SB may include any natural number of electronic units 10 greater than 2. In some embodiments, the electronic units 10 may be arranged in a matrix in the substrate SB.

In some embodiments, each of the plurality of electronic units 10 may include a connection pad 12 for electrical connection with other components. In some embodiments, connection pad 12 may include conductive material. For example, the conductive material may include metal, metal nitride, semiconductor material, any other suitable conductive material, or a combination of the foregoing, but the disclosure is not limited thereto. In some embodiments, the conductive material may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), Aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), silver (Ag), magnesium (Mg), alloys or compounds thereof, other suitable conductive materials, or combinations of the foregoing, but this disclosure Not limited to this. In some embodiments, the conductive material may include transparent conductive oxide (TCO), for example, may include indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (tin oxide, SnO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide, ITZO), antimony tin oxide (ATO), other suitable transparent conductive materials, or combinations of the foregoing, but the disclosure is not limited thereto.

In some embodiments, it can be achieved by, for example, chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or physical vapor deposition. PVD), other suitable deposition processes, or a combination of the foregoing to form the connection pads 12, but the disclosure is not limited thereto.

In some embodiments, a single electronic unit 10 may include a plurality of connection pads 12 . For example, as shown in FIG. 1 , a single electronic unit 10 may include four connection pads 12 , but the disclosure is not limited thereto. The electronic unit 10 may include any natural number of connection pads 12 depending on electrical requirements. In some embodiments, for ease of illustration, FIG. 1 shows that the top surface of the connection pad 12 is flush with the top surface 10T of the electronic unit 10, but it is not limited thereto. The top surface of the connection pad 12 may be higher than the top surface 10T of the electronic unit 10 .

As shown in Figure 1, in some embodiments, a first insulating layer 20 is provided on the substrate SB. In some embodiments, the first insulating layer 20 is provided on the top surface 10T of the electronic unit 10 such that the bottom surface 20B of the first insulating layer 20 is in contact with the top surface 10T of the electronic unit 10 . In some embodiments, the first insulating layer can be formed by, for example, chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, other suitable deposition methods, or a combination of the foregoing. 20 on the electronic unit 10.

In some embodiments, the first insulating layer 20 may be or include organic materials, inorganic materials, other suitable insulating materials, or combinations thereof, but the disclosure is not limited thereto. In some embodiments, the first insulating layer 20 may be or may include a polymer-based dielectric film such as an organic polymer film. In some embodiments, the first insulating layer 20 may be or may include a build-up insulating film (Ajinomoto Build-up Film, ABF), epoxy resin, silicone resin, benzocyclobutene (benzocyclobutene, BCB), polyimide (PI) such as photosensitive polyimide (PSPI), polybenzoxazole (PBO), such as silicon oxide (SiO) _x ), nitrides such as silicon nitride (SiN _x ), oxynitrides such as silicon oxynitride (SiO _x N _y ), other suitable build-up materials, other suitable insulating materials material, or a combination of the foregoing, but the present disclosure is not limited thereto. In some embodiments, the first insulating layer 20 may be or may include a molding material.

In some embodiments, the side surface 20S of the first insulating layer 20 is spaced apart from the outermost surfaces 10S of the plurality of electronic units 10 by a distance d. For details, please refer to Figure 1, which is a schematic cross-sectional view. The distance d is the width from the bottom of the side surface 20S of the first insulating layer 20 to the outermost surface 10S of the plurality of electronic units 10 in the first direction D1. . In some embodiments, the side surface 20S of the first insulating layer 20 and the outermost surface 10S of the electronic unit 10 are not aligned in the first direction D1. In some embodiments, the area of the bottom surface 20B of the first insulating layer 20 is smaller than the area of the top surfaces 10T of the plurality of electronic units 10 . In other words, the projection of the first insulating layer 20 to the top surfaces 10T of the plurality of electronic units 10 may fall within the top surfaces 10T of the plurality of electronic units 10 . In some embodiments, by providing the first insulating layer 20 with an area smaller than the top surface 10T of the plurality of electronic units 10, the difficulty of subsequent cutting of the first cutting process can be reduced and the margin of the first cutting process can be improved. However, Not limited to this.

In some embodiments, the side surface 20S of the first insulation layer 20 is an inclined side surface. In some embodiments, there is an angle a20 between the side surface 20S of the first insulation layer 20 and the bottom surface 20B of the first insulation layer 20 . In some embodiments, angle a20 may be greater than or equal to approximately 45 degrees and less than approximately 90 degrees. For example, the angle a20 may be 45 degrees, 50 degrees, 55 degrees, 60 degrees, 65 degrees, 70 degrees, 75 degrees, 80 degrees, 85 degrees, 89 degrees, or any value or range of values between the aforementioned values. In some embodiments, since the side surface 20S of the first insulating layer 20 has the angle a20, it is beneficial to improve the adhesion and/or reliability between the components disposed above the first insulating layer 20 and the first insulating layer 20. .

Referring to FIG. 2 , which is a schematic cross-sectional view of an electronic device in an intermediate manufacturing stage according to some embodiments of the present disclosure. As shown in FIG. 2 , the first insulating layer 20 is patterned to form first openings (or vias) 22 , 24 and expose a portion of the top surface 10T of the electronic unit 10 . In some embodiments, a corresponding patterning process may be selected according to the material of the first insulating layer 20 . For example, when the first insulating layer 20 is made of photoresist material, the first insulating layer 20 can be patterned through an exposure process and a development process. For example, when the first insulating layer 20 is made of a non-photoresist material, the first insulating layer 20 can be patterned by laser drilling, or an additional photoresist pattern can be further provided on the first insulating layer 20 to pattern the first insulating layer 20 . An insulating layer 20 may use other suitable manufacturing methods, but is not limited thereto.

In some embodiments, the first insulating layer 20 may be patterned according to the location of the connection pads 12 on the electronic unit 10 . For example, each of the plurality of connection pads 12 may correspond to one first opening 22, but the disclosure is not limited thereto. In some embodiments, along the first direction D1, the width of the first opening 24 between adjacent electronic units 10 may be greater than the width of the first opening 22, so as to facilitate the subsequent first cutting process. Adjacent electronic units 10 are separated from each other. As shown in Figure 2, the first opening 22 may have an angle a22. In some embodiments, angle a22 may be greater than or equal to approximately 90 degrees and less than approximately 180 degrees. For example, the angle a22 may be 90 degrees, 100 degrees, 110 degrees, 120 degrees, 130 degrees, 140 degrees, 150 degrees, 160 degrees, 170 degrees, 179 degrees, or any value or range of values between the aforementioned values. In some embodiments, the angle a22 can be adjusted by adjusting process parameters of the patterning process.

Referring to FIG. 3 , which is a schematic cross-sectional view of an electronic device in an intermediate manufacturing stage according to some embodiments of the present disclosure. As shown in FIG. 3 , a first conductive layer 30 is provided on the first insulating layer 20 . In some embodiments, the material and formation method of the first conductive layer 30 may be the same as or different from the material and formation method of the connection pad 12 . In some embodiments, the first conductive layer 30 is conformably formed on the first insulating layer 20 and extends into the first openings 22, 24. Next, the first conductive layer 30 may be patterned to expose a portion of the top surface 10T of the electronic unit 10 and a portion of the side surfaces 20S and the top surface 20T of the first insulating layer 20 . For example, the first conductive layer 30 is compliantly disposed and extends into the first openings 22 and 24. According to some embodiments, the top surface of the first conductive layer 30 corresponding to the first openings 22 and 24 may have a recess ( recess)R, furthermore, in the second direction D2, the top surface of the first conductive layer 30 corresponding to the first openings 22, 24 is higher than the top surface 20T of the first insulating layer 20 and the first conductive layer 30 corresponds to the first opening 22, 24. The top surfaces of the openings 22 and 24 are lower than the top surface of the first conductive layer 30 corresponding to the first insulating layer 20 . The first conductive layer 30 described in the present disclosure may be a single layer of conductive material or multiple layers of conductive material, and the first conductive layer 30 may include copper, titanium, aluminum, molybdenum, indium tin oxide, other suitable materials or a combination of the foregoing, But it is not limited to this.

In some embodiments, the patterned first conductive layer 30 may correspond to one of the plurality of first openings 22 of the first insulating layer 20 . In other embodiments, the patterned first conductive layer 30 may correspond to the plurality of first openings 22 of the first insulating layer 20 . For example, the patterned first conductive layer 30 may correspond to two first openings 22, but the disclosure is not limited thereto. The patterned first conductive layer 30 may correspond to any natural number of first openings 22, so as to The fan-out characteristics and/or fan-out range of the first conductive layer 30 are improved. Among them, the improvement of fan-out characteristics may include increasing the number and bonding capabilities of components bonded with other components, while improving the fan-out range means increasing the fan-out area to avoid space constraints during circuit design, but it does not mean increasing the fan-out area. This is the limit. In some embodiments, the first conductive layer 30 may be interposed between the first insulating layer 20 and the subsequently formed second insulating layer 40 (see FIG. 4 ). The first conductive layer 30 is electrically connected to the connection pad 12 of the electronic unit 10 through one of the plurality of first openings 22 .

In other embodiments, a seed layer (not shown) may be compliantly formed on the first insulating layer 20 and in the first openings 22 and 24, and then a metal layer may be formed on the seed layer. Materials of the seed layer and the metal layer include, for example, titanium and copper, but are not limited thereto. Next, the metal layer and the seed layer are patterned to remove a portion of the metal layer and to remove a portion of the seed layer, thereby exposing a portion of the top surface 10T of the electronic unit 10 .

Referring to FIG. 4 , which is a schematic cross-sectional view of an electronic device in an intermediate manufacturing stage according to some embodiments of the present disclosure. As shown in FIG. 4 , a second insulating layer 40 is provided on the substrate SB (shown in FIG. 1 ). Specifically, the second insulating layer 40 is formed on the top surface 10T of the electronic unit 10 , the top surface 20T and the side surfaces 20S of the first insulating layer 20 , the first opening 24 and the first conductive layer 30 . In some embodiments, the second insulating layer 40 may include a bottom surface 40B (third surface), a top surface 40T (fourth surface) opposite to the bottom surface 40B, and a side surface 40S ( second side surface). In some embodiments, the top surface 40T of the second insulating layer 40 is further away from the electronic unit 10 than the bottom surface 40B of the second insulating layer 40 .

In some embodiments, the material and formation method of the second insulation layer 40 may be the same as or different from the materials and formation method of the first insulation layer 20 . In some embodiments, since the materials of the first insulating layer 20 and the second insulating layer 40 are different, the first insulating layer 20 and the second insulating layer 40 may substantially have an interface. In the following description, the materials of the first insulating layer 20 and the second insulating layer 40 are different as an example.

In some embodiments, as shown in FIG. 4 , the first insulation layer 20 may have a first thickness T1 , and the second insulation layer 40 may have a second thickness T2 . In some embodiments, the first thickness T1 of the first insulating layer 20 is the distance between the bottom surface 20B and the top surface 20T of the first insulating layer 20 in the second direction D2. In some embodiments, the second thickness T2 of the second insulating layer 40 is a distance between the top surface 20T of the first insulating layer 20 and the top surface 40T of the second insulating layer 40 in the second direction D2.

In some embodiments, the first thickness T1 of the first insulating layer 20 may be greater than or equal to approximately 2 um and less than or equal to approximately 10 um. For example, the first thickness T1 may be 2 um, 3 um, 4 um, 5 um, 6 um, 7 um, 8 um, 9 um, 10 um, or any value or range of values between the aforementioned values. In some embodiments, the second thickness T2 of the second insulating layer 40 may be greater than or equal to approximately 13 um and less than or equal to approximately 50 um. For example, the second thickness T2 may be 13 um, 15 um, 20 um, 25 um, 30 um, 35 um, 40 um, 45 um, 50 um, or any value or range between the aforementioned values. In some embodiments, the first thickness T1 of the first insulation layer 20 may be smaller than the second thickness T2 of the second insulation layer 40 . In some embodiments, the ratio of the first thickness T1 of the first insulating layer 20 to the second thickness T2 of the second insulating layer 40 (T1/T2) may be greater than or equal to about 0.02 to less than or equal to about 0.85. For example, the ratio (T1/T2) can be 0.02, 0.04, 0.08, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.75, 0.8, 0.85, any value or range between the aforementioned values.

In some embodiments, since the first thickness T1 of the first insulating layer 20 may be smaller than the second thickness T2 of the second insulating layer 40 , the first insulating layer 20 and the second insulating layer 40 may be stacked to gradually Fan-out connection pad 12. For example, the connection pads 12 can be initially fanned out through the first opening 22 of the first insulating layer 20 , and then further fanned out through the second opening 42 of the second insulating layer 40 (refer to FIG. 5 below). , thereby improving the fan-out effect and/or fan-out range. In other embodiments, the electronic device may further dispose other insulating layers with openings between the top surface 10T of the electronic unit 10 and the subsequently formed connecting elements 60 (refer to the following Figure 13), thereby improving the fan-out effect and/or or fan-out range.

It should be noted that since the first insulating layer 20 and the second insulating layer 40 can simultaneously serve as protective layers of the electronic unit 10, the electronic unit 10 can be fully protected from damage. Furthermore, by sequentially disposing the first insulating layer 20 and the second insulating layer 40 on the electronic unit 10, the problem that a single protective layer is easily cracked and/or edge warped after cutting can be reduced during subsequent cutting processes. In addition, since the present disclosure stacks the first insulating layer 20 and the second insulating layer 40 multiple times, it can avoid the problem of difficulty in accurately forming openings penetrating a single insulating layer in a thicker single insulating layer.

It should be noted that, as shown in FIGS. 3 and 4 , since the patterned first conductive layer 30 exposes a portion of the top surface 10T of the electronic unit 10 , the bottom surface 40B of the second insulating layer 40 is in contact with the plurality of components. The top surface 10T of each electronic unit 10 is in direct contact to improve the reliability of the subsequent cutting process. For example, since there are fewer components intersecting the virtual first cutting line CL1 described below, the problem of uneven cutting edges, chipping and/or warping after cutting along the virtual first cutting line CL1 can be reduced.

In some embodiments, as shown in FIG. 4 , the second insulating layer 40 is in direct contact with the side surface 20S of the first insulating layer 20 . In some embodiments, since the inclined side surface 20S of the first insulating layer 20 has the above-mentioned angle a20, the first insulating layer 20 and the second insulating layer 40 can be joined more easily. Furthermore, when the materials of the first insulating layer 20 and the second insulating layer 40 are different, the angle a20 can disperse the stress between the heterojunction of the first insulating layer 20 and the second insulating layer 40 and/or can enhance the first insulating layer 20 and the second insulating layer 40 . Reliability of the heterojunction between the insulating layer 20 and the second insulating layer 40 .

In some embodiments, the coefficients of thermal expansion (Coefficient of Thermal Expansion, CTE) of the first insulating layer 20 and the second insulating layer 40 may be the same or different. In some embodiments, the thermal expansion coefficient of the first insulating layer 20 and/or the second insulating layer 40 may be greater than or equal to about 3 ppm/K to less than or equal to about 60 ppm/K. For example, the thermal expansion coefficient of the first insulating layer 20 and/or the second insulating layer 40 may be 3 ppm/K, 5 ppm/K, 10 ppm/K, 15 ppm/K, 20 ppm/K, 25 ppm/K. K, 30 ppm/K, 35 ppm/K, 40 ppm/K, 45 ppm/K, 50 ppm/K, 55 ppm/K, 60 ppm/K, any value or range of values between the aforementioned values. In some embodiments, when the thermal expansion coefficients of the first insulating layer 20 and the second insulating layer 40 are different, the degree of warpage of the electronic device can be reduced. In some embodiments, the thermal expansion coefficient of the first insulating layer 20 is smaller than the thermal expansion coefficient of the second insulating layer 40 , so the warpage of the electronic device can be reduced, but is not limited to this.

In some embodiments, the first insulation layer 20 and the second insulation layer 40 may be reverse warping layers of each other. In other words, because the first insulating layer 20 and the second insulating layer 40 have different warping directions, they can offset the warping phenomenon of each other, thereby reducing the degree of warping of the electronic device. For example, the first insulating layer 20 may be an insulating layer that warps upward (opening upward) toward the second direction D2, and the second insulating layer 40 may be an insulating layer that warps downward (opening downward) away from the second direction D2. The insulating layer, therefore, when the first insulating layer 20 and the second insulating layer 40 are combined, can offset the warpage of each other.

In some embodiments, the Young’s modulus of the first insulating layer 20 and/or the second insulating layer 40 may be greater than or equal to about 1000 MPa and less than or equal to about 20000 MPa. For example, the Young's modulus of the first insulating layer 20 and/or the second insulating layer 40 may be 1000 MPa, 2000 MPa, 4000 MPa, 6000 MPa, 8000 MPa, 10000 MPa, 12000 MPa, 14000 MPa, 16000 MPa , 18000 MPa, 20000 MPa, any value or range between the aforementioned values. In some embodiments, the Young's modulus of the first insulating layer 20 is smaller than the Young's modulus of the second insulating layer 40 . Therefore, the second insulating layer 40 is formed on the top surface 10T of the electronic unit 10 and the first insulating layer 20 The top surface 20T and side surfaces 20S, the first opening 24 and the first conductive layer 30 can avoid or reduce the risk of damage such as scratches to the electronic unit 10, the first insulating layer 20 or the first conductive layer 30, but this is not the case. is limited.

In some embodiments, since the water and oxygen resistance of the second insulating layer 40 can be better than that of the first insulating layer 20 , the resistance of the electronic device of the present disclosure can be further improved by providing the second insulating layer 40 . Water and oxygen properties. In some embodiments, since the hardness of the second insulating layer 40 may be greater than the hardness of the first insulating layer 20 , the hardness of the electronic device of the present disclosure can be further improved by providing the second insulating layer 40 . In these embodiments, even though the water and oxygen resistance properties and/or hardness of the first insulating layer 20 are slightly lower than those of the second insulating layer 40 , the first insulating layer 20 can accurately and easily The ground is formed on the electronic unit 10 and helps to form the first opening 22. Therefore, the combination of the first insulating layer 20 and the second insulating layer 40 can effectively improve various characteristics of the electronic device.

In some embodiments, since the first thickness T1 of the first insulating layer 20 is smaller than the second thickness T2 of the second insulating layer 40 , the first insulating layer 20 may include PSPI which is easier to perform a precise patterning process, and the The second insulating layer 40 may include ABF to improve the fan-out effect and/or the fan-out range through the thickness ratio and material selection between the first insulating layer 20 and the second insulating layer 40 .

Referring to FIG. 5 , which is a schematic cross-sectional view of an electronic device in an intermediate manufacturing stage according to some embodiments of the present disclosure. As shown in FIG. 5 , the second insulating layer 40 is patterned to form the second opening 42 and expose the top surface of the first conductive layer 30 . In some embodiments, second opening 42 may have angle a42. In some embodiments, angle a42 may be greater than or equal to 90 degrees and less than 180 degrees. For example, the angle a42 may be 90 degrees, 100 degrees, 110 degrees, 120 degrees, 130 degrees, 140 degrees, 150 degrees, 160 degrees, 170 degrees, 179 degrees, or any value or range of values between the aforementioned values. In some embodiments, angle a42 can be adjusted by adjusting process parameters of the patterning process.

In some embodiments, the angle a22 of one of the first openings 22 is different from the angle a42 of one of the second openings 42 . In some embodiments, the angle a22 of the first opening 22 is greater than the angle a42 of the second opening 42 , for example, so that the heat energy generated by the electronic unit 10 can be quickly dissipated, but is not limited thereto.

In some embodiments, the roughness of the first sidewall 22S of one of the plurality of first openings 22 may be less different than the roughness of the second sidewall 42S of one of the plurality of second openings 42 . In the present disclosure, roughness may be surface roughness, and may be measured by arithmetic mean roughness (Ra), maximum height (Ry), ten-point average roughness (Rz), and other similar measurement methods, Or a combination of the above. In some embodiments, since the first thickness T1 of the first insulating layer 20 may be smaller than the second thickness T2 of the second insulating layer 40 , the conductive component (eg, The thickness of the first conductive layer 30) is correspondingly smaller than the thickness of the conductive component (eg, subsequent connecting element 60) disposed in the second opening 42 of the second insulating layer 40. Therefore, when the roughness of the first sidewall 22S of the first opening 22 is smaller and thus has a smoother sidewall, it can help to accurately form the first conductive layer 30 in the first opening 22, thereby improving the first conductive layer. 30% reliability. In addition, since the first thickness T1 of the first insulating layer 20 is smaller than the second thickness T2 of the second insulating layer 40 , the formation accuracy of the first opening 22 will be greater than the formation accuracy of the second opening 42 .

On the other hand, when the second side wall 42S of the second opening 42 has a relatively large roughness and thus has a relatively uneven side wall, the friction of the rough side wall can help to form a structure with a larger thickness and/or larger diameter. The wider connecting element 60 is in the second opening 42, thereby improving the reliability of the connecting element 60. For example, the reliability of the subsequent formation of the connecting element 60 through an electroplating process can be improved.

In some embodiments, at least one of the plurality of first openings 22 and at least one of the plurality of second openings 42 do not overlap in the normal direction of the electronic unit 10 (ie, the second direction D2), This can improve the fan-out effect and/or the fan-out range or reduce the risk of cracking of the metal layer of the electronic device, but is not limited to this. In other embodiments, each of the plurality of first openings 22 and each of the plurality of second openings 42 do not overlap in the normal direction of the electronic unit 10 (ie, the second direction D2). In some embodiments, at least one of the plurality of first openings 22 overlaps with at least one of the plurality of second openings 42 in a normal direction of the electronic unit 10 (ie, the second direction D2), so that The margin for performing the patterning process of the second insulating layer 40 is improved. In other embodiments, each of the plurality of first openings 22 overlaps with each of the plurality of second openings 42 in a normal direction of the electronic unit 10 (ie, the second direction D2).

In some embodiments, following the above, a first cutting process may be performed to cut the substrate SB, so that the plurality of electronic units 10 are separated into a plurality of first electronic devices. In some embodiments, the first cutting process may include a blade saw process, a die break dicing process, a laser cutting process, other suitable cutting processes, or a combination of the foregoing. As shown in FIG. 5 , the first cutting process may perform cutting along the virtual first cutting line CL1 .

Referring to FIG. 6 , which is a schematic cross-sectional view of the first electronic device 1 after the first cutting process according to some embodiments of the present disclosure. In some embodiments, the first electronic device 1 may be a known good die (KGD), and the first electronic device 1 may include the first conductive layer 30 that may serve as a redistribution layer of a wafer level package. As shown in FIG. 6 , after the first cutting process, the side surface 10S of the electronic unit 10 of the first electronic device 1 is aligned with the side surface 40S of the second insulating layer 40 so that the second insulating layer 40 protects the first electrons. Electronic unit 10 of device 1 . That is to say, in the first direction D1, the distance between the side surface 10S of the electronic unit 10 and the side surface 40S of the second insulating layer 40 is less than or equal to 5 microns. Through the alignment design of the side surface 10S of the electronic unit 10 and the side surface 40S of the second insulating layer 40, the subsequent process quality will be beneficial.

In addition, it should be understood that, for clarity of explanation, some components of the first electronic device 1 are omitted in FIG. 6 and some components are schematically illustrated. In some embodiments, additional components may be added to the first electronic device 1 . In other embodiments, some components of the first electronic device 1 described above may be replaced or omitted.

Referring to FIG. 7 , a schematic cross-sectional view of the second electronic device 2 in an intermediate manufacturing stage is shown according to some embodiments of the present disclosure. As shown in FIG. 7 , a plurality of first electronic devices 1 are provided on the first carrier CP1. For ease of explanation, FIG. 7 shows that two first electronic devices 1 are provided on the first carrier CP1, but the disclosure is not limited thereto.

Specifically, in some embodiments, as shown in FIG. 7 , a first carrier CP1 is provided, and a first adhesive layer AL1 is disposed on the first carrier CP1 . In some embodiments, the first carrier CP1 may be or may include a wafer, a chip, glass, quartz, sapphire, ceramic, polyimide (PI), polycarbonate (PC) , polyethylene terephthalate (PET) carrier board, polypropylene (PP) carrier board, temporary carrier board, other suitable carrier boards or combinations of the above, but the present disclosure is not limited thereto.

In some embodiments, the first adhesive layer AL1 can serve as a peeling layer or a release layer. In some embodiments, the first adhesive layer AL1 may be or may include a pyrolytic glue, an ultraviolet photolysis (Ultra-Violet, UV) glue layer, a light-to-heat conversion (LTHC) glue layer, or other suitable A cleaved adhesive layer, or a combination of the foregoing, but the present disclosure is not limited thereto. In some embodiments, the first adhesive layer AL1 may be formed through a coating process or other suitable formation processes. Then, the first electronic device 1 as shown in FIG. 6 is turned up and down along the second direction D2, so that the top surface 40T of the second insulating layer 40 of the first electronic device 1 is in direct contact with the first adhesive layer AL1 ( bonding).

As shown in FIG. 7 , in some embodiments, a third insulating layer 50 is provided on a plurality of first electronic devices 1 . In some embodiments, the third insulating layer 50 may surround the electronic unit 10 in the first electronic device 1 . For example, the third insulating layer 50 may surround the side surface 10S and the bottom surface 10B of the electronic unit 10 . In some embodiments, the third insulation layer 50 may be disposed on the first adhesive layer AL1 and between adjacent first electronic units 10 . In some embodiments, the third insulating layer 50 may be disposed on the side surfaces 40S of the second insulating layer 40 , the side surfaces 10S of the electronic unit 10 , and the bottom surface 10B of the electronic unit 10 . In some embodiments, the third insulating layer 50 may expose a portion of the side surface 40S of the second insulating layer 40 and/or a portion of the side surface 10S of the electronic unit 10 . By aligning the side surface 10S of the electronic unit 10 with the side surface 40S of the second insulating layer 40 , the risk of cracking of the side surface 10S, the side surface 40S and the third insulating layer 50 can be reduced, but is not limited thereto.

In some embodiments, the third insulating layer 50 may be or may include organic materials, inorganic materials, other suitable packaging materials, or combinations thereof, but the disclosure is not limited thereto. In some embodiments, the aforementioned inorganic materials may include silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, other suitable materials, or combinations thereof, but the disclosure is not limited thereto. In some embodiments, the organic material may include epoxy resin, silicone resin, acrylic resins, other suitable materials, or combinations thereof, but the present disclosure is not limited thereto. For example, the acrylic resin may include polymethyl methacrylate (PMMA), benzocyclobutene (BCB), polyimide, copolyester (polyester), polydimethylsiloxy alkane (polydimethylsiloxane, PDMS), tetrafluoroethylene-perfluoroalkoxy vinyl ether copolymer (polyfluoroalkoxy, PFA). In some embodiments, the third insulating layer 50 may include ABF. In some embodiments, the third insulating layer 50 may be a light-transmissive, semi-transparent or light-opaque material.

In some embodiments, as shown in FIG. 7 , the third insulation layer 50 may have a fifth thickness T5. In some embodiments, the fifth thickness T5 may be a distance between the top surface 50T of the third insulating layer 50 and the bottom surface 50B of the third insulating layer 50 . In some embodiments, the fifth thickness T5 of the third insulation layer 50 may be greater than the second thickness T2 of the second insulation layer 40 . In some embodiments, the fifth thickness T5 of the third insulation layer 50 may be greater than the first thickness T1 of the first insulation layer 20 . In some embodiments, the fifth thickness T5 of the third insulating layer 50 may be greater than the sum of the thicknesses of the second thickness T2 of the second insulating layer 40 and the first thickness T1 of the first insulating layer 20 .

Referring to FIG. 8 , a schematic cross-sectional view of the second electronic device 2 in an intermediate manufacturing stage is shown according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 8 , a second carrier CP2 is provided, and a second adhesive layer AL2 is disposed on the second carrier CP2. In some embodiments, the material of the second carrier plate CP2 and the material of the first carrier plate CP1 may be the same or different. In some embodiments, the material and formation method of the second adhesive layer AL2 and the material and formation method of the first adhesive layer AL1 may be the same or different. Then, the structure as shown in FIG. 7 is flipped up and down along the second direction D2, so that the bottom surface 50B of the third insulating layer 50 directly contacts and joins the second adhesive layer AL2.

Referring to FIG. 9 , a schematic cross-sectional view of the second electronic device 2 in an intermediate manufacturing stage is shown according to some embodiments of the present disclosure. In some embodiments, as shown in Figure 9, a corresponding cracking process can be used to release or remove the first adhesive layer AL1 and the first carrier CP1 according to the material of the first adhesive layer AL1, thereby exposing Top surface 50T of third insulating layer 50 .

Referring to FIG. 10 , a schematic cross-sectional view of the second electronic device 2 in an intermediate manufacturing stage is shown according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 10 , the first photoresist 52 is formed on the top surface 50T of the third insulating layer 50 and the top surface 40T of the second insulating layer 40 . In some embodiments, the first photoresist 52 can be formed by a spin coating process, a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition (ALD) process, or a high-density plasma chemical process. It is formed by a high density plasma CVD (HDP-CVD) process, other suitable methods, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the first photoresist 52 may be a dry film photoresist. In some embodiments, the first photoresist 52 may have an opening 53 corresponding to the second opening 42 of the second insulating layer 40 to expose at least a portion of the top surface of the first conductive layer 30 . In some embodiments, one opening 53 of the first photoresist 52 may correspond to one of the second openings 42 of the second insulation layer 40 , but the disclosure is not limited thereto.

Referring to FIG. 11 , a schematic cross-sectional view of the second electronic device 2 in an intermediate manufacturing stage is shown according to some embodiments of the present disclosure. In some embodiments, the second conductive layer 62 is disposed in the opening 53 of the first photoresist 52 . In some embodiments, the second conductive layer 62 may be disposed on the top surface 50T of the third insulating layer 50 and the top surface 40T of the second insulating layer 40 . In some embodiments, a portion of second conductive layer 62 is in contact with top surface 50T of third insulating layer 50 . In some embodiments, second conductive layer 62 may include conductive material. For example, the conductive material may include metal, metal nitride, semiconductor material or combinations thereof, or any other suitable conductive material, but the disclosure is not limited thereto. In some embodiments, the conductive material may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), Aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), silver (Ag), magnesium (Mg), alloys or compounds thereof, other suitable conductive materials, or combinations of the foregoing, but this disclosure does not Limited to this. In some embodiments, it can be formed by, for example, electroplating, chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, other suitable deposition methods, or a combination of the foregoing. second conductive layer 62, but the present disclosure is not limited thereto.

In some embodiments, the first conductive layer 30 may have a third thickness T3 in the second direction D2. As shown in FIG. 11 , the third thickness T3 of the first conductive layer 30 may be between the bottom surface of the second conductive layer 62 and the top surface 20T of the first insulating layer 20 . In some embodiments, the second conductive layer 62 may have a fourth thickness T4 in the second direction D2. As shown in FIG. 11 , the fourth thickness T4 of the second conductive layer 62 may be the thickness of the second conductive layer 62 located on the third insulating layer 50 . In some embodiments, since the first conductive layer 30 may be a conductive layer in a wafer level package (Wafer Level Package, WLP) process, and the second conductive layer 62 may be a panel level package (Panel Level Package, PLP) process, Therefore, the fourth thickness T4 of the second conductive layer 62 may be greater than the third thickness T3 of the first conductive layer 30 .

In some embodiments, the second conductive layer 62 may include a multi-layer structure, wherein the multi-layer structure may include a seed layer and a metal layer. For example, a seed layer (not shown) may be compliantly formed in the top surface 50T of the third insulating layer 50 , the top surface of the second insulating layer 40 and the second opening 42 . Next, a metal layer (not shown) is formed on the seed layer to improve the reliability of the metal layer through the seed layer. In some embodiments, the seed layer and the metal layer can be formed by physical vapor deposition (PVD), electroplating, or other suitable formation processes, respectively, but the disclosure is not limited thereto. In some embodiments, the seed layer may be titanium copper alloy (TiCu) and the metal layer may include copper.

Referring to FIG. 12 , a schematic cross-sectional view of the second electronic device 2 in an intermediate manufacturing stage is shown according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 12 , a second photoresist 54 is formed on the first photoresist 52 . Specifically, the second photoresist 54 may be formed on the top surfaces of the first photoresist 52 and the second conductive layer 62 . In some embodiments, the material and formation method of the second photoresist 54 may be the same as or different from the materials and formation method of the first photoresist 52 . In some embodiments, the second photoresist 54 may be a dry film photoresist. In some embodiments, the second photoresist 54 may have an opening 55 corresponding to the second conductive layer 62 so as to expose the top surface of the second conductive layer 62 through the opening 55 of the second photoresist 54 . At least part of it.

Referring to FIG. 13 , a schematic cross-sectional view of the second electronic device 2 in an intermediate manufacturing stage is shown according to some embodiments of the present disclosure. In some embodiments, the third conductive layer 64 is disposed in the opening 55 of the second photoresist 54 . In some embodiments, the material and formation method of the third conductive layer 64 may be the same as or different from the materials and formation method of the third conductive layer 64 . In some embodiments, the third conductive layer 64 and the second conductive layer 62 may have an interface. In other embodiments, the third conductive layer 64 and the second conductive layer 62 may have substantially no interface. In some embodiments, the third conductive layer 64 may also include a seed layer and a metal layer, so as to improve the reliability of the metal layer through the seed layer. In some embodiments, the thickness of the third conductive layer 64 may be greater than that of the second conductive layer 62 in the second direction D2.

Referring to FIG. 14 , a schematic cross-sectional view of the second electronic device 2 in an intermediate manufacturing stage is shown according to some embodiments of the present disclosure. In some embodiments, the second photoresist 54 and the first photoresist 52 are removed to expose the top surface 40T of the second insulating layer 40 . In some embodiments, the second photoresist 54 and the first photoresist 52 can be removed through an ashing process, other suitable removal processes, or a combination of the foregoing, but the disclosure is not limited thereto. In some embodiments, the second photoresist 54 and the first photoresist 52 can be removed in the same process. In other embodiments, the second photoresist 54 and the first photoresist 52 can be removed in different processes. In some embodiments, due to the selectivity of the removal process, the removal process does not substantially damage the structures of the third conductive layer 64 and the second conductive layer 62 .

In some embodiments, the third conductive layer 64 and the second conductive layer 62 may jointly serve as the connection element 60 disposed on the second insulating layer 40 . In other words, the connection element 60 may include, for example, the second conductive layer 62 and the third conductive layer 64 . In some embodiments, the connection element 60 may serve as a rewiring element for electronic devices in panel-level processes. In some embodiments, the connection element 60 is connected to the connection pad 12 of the electronic unit 10 through the first conductive layer 30 . In some embodiments, since the third conductive layer 64 is in direct contact with and is electrically connected to the second conductive layer 62 , the second conductive layer 62 is in direct contact with and is electrically connected to the first conductive layer 30 , and the first conductive layer 30 is in direct contact with The connection pads 12 are in direct contact and electrically connected, so the fan-out effect and/or the fan-out range can be effectively improved.

Referring to FIG. 15 , a schematic cross-sectional view of the second electronic device 2 in an intermediate manufacturing stage is shown according to some embodiments of the present disclosure. In some embodiments, the fourth insulating layer 70 is provided on the connecting element 60 , the third insulating layer 50 and the second insulating layer 40 . In some embodiments, the fourth insulating layer 70 covers the side surfaces of the connection element 60 . In some embodiments, the fourth insulating layer 70 is in direct contact with the third insulating layer 50 and the second insulating layer 40 . In some embodiments, the material and formation method of the fourth insulation layer 70 and the material and formation method of the third insulation layer 50 may be the same or different. In some embodiments, the fourth insulation layer 70 and the third insulation layer 50 may have an interface. In other embodiments, the fourth insulation layer 70 and the third insulation layer 50 may have substantially no interface. In some embodiments, the hardness of the third insulating layer 50 and/or the fourth insulating layer 70 is different from that of the first insulating layer 20 and/or the second insulating layer 40 . For example, the hardness of the third insulating layer 50 and/or the fourth insulating layer 70 may be greater than the hardness of the first insulating layer 20 and/or the second insulating layer 40 .

Then, in some embodiments, a second cutting process may be performed to separate the plurality of first electronic devices 1 into a plurality of second electronic devices 2 . In some embodiments, the second cutting process and the first cutting process may be the same or different. As shown in FIG. 15, the second cutting process may perform cutting along the virtual second cutting line CL2.

In other embodiments, the fourth insulating layer 70 may include a first sub-insulating layer and a second sub-insulating layer formed in different processes. In this embodiment, continuing from FIG. 9 , a patterned first sub-insulating layer may be formed on the third insulating layer 50 first. Next, a second conductive layer 62 is formed in the opening of the first sub-insulating layer, and is formed on the third insulating layer 50 and the second insulating layer 40 . Then, a patterned second sub-insulating layer is formed on the patterned first sub-insulating layer. After that, a third conductive layer 64 is formed in the opening of the second sub-insulating layer, and the third conductive layer 64 is formed on the second conductive layer 62 , thereby obtaining the connection element 60 .

Referring to FIG. 16 , a schematic cross-sectional view of the second electronic device 2 after the second cutting process is shown according to some embodiments of the present disclosure. As shown in FIG. 16, in the first direction D1, the side surface 50S of the third insulating layer 50 of the second electronic device 2 is aligned with the side surface 70S of the fourth insulating layer 70, so that through the fourth insulating layer 70 and The third insulating layer 50 protects the electronic unit 10 of the second electronic device 2 . As shown in FIG. 16 , in some embodiments, connection pads 66 may be further disposed on the third conductive layer 64 . Therefore, the second electronic device 2 can be electrically connected to a printed circuit board (PCB) or other components through the connection pads 66 . In some embodiments, the material and formation method of connection pad 66 may be the same as or different from the material and formation method of connection pad 12 . The second conductive layer 62 , the third conductive layer 64 and the fourth insulating layer 70 are staggered and stacked to form a redistribution layer of the second electronic device 2 , thereby improving the fan-out characteristics and/or fan-out range of the electronic device.

In summary, according to embodiments of the present disclosure, an electronic device including a first insulating layer and a second insulating layer and a manufacturing method thereof are provided to avoid problems such as via holes, wires, redistribution layers, etc. by disposing the insulating layers in stages. The problem of tight circuit design space. In addition, by adjusting the thickness ratio and/or material properties (such as material type, thermal expansion coefficient, warping direction) of the first insulating layer and the second insulating layer, the fan out characteristics and/or of the electronic device can be improved. Or fan-out range, improve compatibility with fine wire diameter processes, reduce warpage (warpage) probability, improve reliability and/or improve electrical performance. Furthermore, the electronic device and the manufacturing method thereof of the present disclosure are also compatible with the wafer-first process and the layer-first process.

Components in the embodiments of the present disclosure may be mixed and matched as long as they do not violate the spirit of the invention or conflict. In addition, the protection scope of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Anyone with ordinary knowledge in the relevant technical field can learn from the disclosure It is understood that processes, machines, manufacturing, material compositions, devices, methods and steps currently or developed in the future can be used according to the present disclosure as long as they can perform substantially the same functions or obtain substantially the same results in the embodiments described herein. use. Therefore, the protection scope of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. Any embodiment or patentable scope of the disclosure need not achieve all the purposes, advantages and/or features disclosed in the disclosure.

Several embodiments are summarized above so that those with ordinary knowledge in the technical field to which this disclosure belongs can better understand the concepts of the embodiments of this disclosure. Those with ordinary knowledge in the technical field to which this disclosure belongs should understand that they can design or modify other processes and structures based on the embodiments of this disclosure to achieve the same purposes and/or advantages as the embodiments introduced here. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and they can be used without departing from the spirit and scope of the present disclosure. Make all kinds of changes, substitutions and substitutions.

1: The first electronic device 10: Electronic unit 10B, 20B, 40B, 50B: Bottom surface 10T, 20T, 40T, 50T: Top surface 10S, 20S, 40S, 50S, 70S: Side surface 12, 66: Connection pad 2: Second electronic device 20: First insulation layer 22, 24: First opening 22S: First side wall 30: First conductive layer 40: Second insulation layer 42:Second opening 42S: Second side wall 50:Third insulation layer 52:First photoresist 53, 55:Open your mouth 54: Second photoresist 60:Connecting components 62: Second conductive layer 64:Third conductive layer 70:Fourth insulation layer AL1: first adhesive layer AL2: Second adhesive layer a20, a22, a42: angle CL1: first cutting line CL2: Second cutting line CP1: first carrier board CP2: Second carrier board d: distance D1: first direction D2: second direction R: concave part SB:Substrate T1: first thickness T2: second thickness T3: The third thickness T4: The fourth thickness T5: fifth thickness

The present disclosure can be more fully understood from the following detailed description when read in conjunction with the accompanying drawings. It is worth noting that, following industry standard practice, features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. Figures 1 to 6 are respectively schematic cross-sectional views showing the first electronic device 1 at different manufacturing stages according to some embodiments of the present disclosure. Figures 7 to 16 are respectively schematic cross-sectional views showing the second electronic device 2 at different manufacturing stages according to some embodiments of the present disclosure.

1: The first electronic device

10: Electronic unit

10B, 40B: Bottom surface

10T, 40T: top surface

10S, 20S, 40S: side surface

12:Connection pad

20: First insulation layer

30: First conductive layer

40: Second insulation layer

42:Second opening

D1: first direction

D2: second direction

T1: first thickness

T2: second thickness

T3: The third thickness

Claims (20)

An electronic device including: An electronic unit includes a first surface, a second surface opposite to the first surface, and a first side surface connecting the first surface and the second surface; a first insulating layer disposed on the second surface; A second insulating layer is provided on the first insulating layer and includes a third surface, a fourth surface opposite to the third surface, and a second side surface connecting the third surface and the fourth surface. ;as well as a connecting component disposed on the second insulating layer and electrically connected to the electronic unit, Wherein, the third surface of the second insulating layer is in contact with the second surface of the electronic unit. The electronic device of claim 1, wherein the first insulating layer includes a plurality of first openings, the second insulating layer includes a plurality of second openings, and an angle of one of the plurality of first openings is consistent with the angle of the first opening. The angle of one of the plurality of second openings is different. The electronic device as described in claim 2 further includes: A first conductive layer is disposed between the first insulating layer and the second insulating layer, and the first conductive layer is electrically connected to the electronic unit through one of the plurality of first openings. . The electronic device of claim 2, wherein a roughness of a side wall of one of the plurality of first openings is smaller than a roughness of a side wall of one of the plurality of second openings. The electronic device of claim 2, wherein at least one of the plurality of first openings and at least one of the plurality of second openings do not overlap in a normal direction of the electronic unit. The electronic device of claim 2, wherein at least one of the first openings overlaps with at least one of the second openings in a normal direction of the electronic unit. The electronic device of claim 1, wherein the second side surface of the second insulating layer is aligned with the first side surface of the electronic unit. The electronic device of claim 1, wherein the first insulating layer has a third side surface, and the third side surface has an included angle with the second surface, and the included angle is greater than or equal to 45 degrees and less than 90 degrees. The electronic device of claim 8, wherein the second insulating layer is in contact with the third side surface of the first insulating layer. The electronic device as claimed in claim 1, wherein the connecting element further includes: A second conductive layer is electrically connected to the first conductive layer. The electronic device of claim 10, wherein the thickness of the second conductive layer is greater than the thickness of the first conductive layer. The electronic device as described in claim 10 further includes: A third insulating layer surrounds the electronic unit, wherein a portion of the second conductive layer is in contact with a surface of the third insulating layer. The electronic device of claim 12, wherein a first thickness of the first insulating layer is less than a second thickness of the second insulating layer, and the second thickness of the second insulating layer is less than the third insulating layer of a third thickness. The electronic device as described in claim 12 further includes: A fourth insulating layer is disposed on the connecting element and in contact with the second insulating layer and the third insulating layer. The electronic device of claim 1, wherein the first insulating layer and the second insulating layer have different thermal expansion coefficients. The electronic device as claimed in claim 1, wherein the first insulating layer and the second insulating layer are reverse warping layers. A method of manufacturing an electronic device, including: A substrate is provided, and the substrate includes a plurality of electronic units; providing a first insulating layer on the substrate; and providing a second insulating layer on the substrate, The second insulating layer is in contact with a portion of a surface of the substrate. The manufacturing method as described in claim 17 further includes: A first cutting process is performed to cut the substrate to separate the plurality of electronic units into a plurality of first electronic devices, wherein a side surface of the electronic unit in one of the plurality of first electronic devices is in contact with the second The side surfaces of the insulation layer are aligned. The manufacturing method as described in claim 18 further includes: providing the plurality of first electronic devices on a carrier board; providing a third insulating layer on the plurality of first electronic devices; Provide a connecting element on the second insulating layer and the third insulating layer; providing a fourth insulating layer on the connecting element and the third insulating layer; and A second cutting process is performed to separate the plurality of first electronic devices into a plurality of second electronic devices. The manufacturing method of claim 17, wherein a surface of the second insulating layer contacts a surface of the plurality of electronic units.

Images