TWI845958B - Electronic device and manufacturing method thereof - Google Patents

Abstract

An electronic device and a manufacturing method thereof are provided. The electronic device includes an electronic unit, a first insulating layer, a second insulating layer and a connecting element. The electronic unit includes a first surface, a second surface opposite to the first surface, and a first side surface connecting the first surface and the second surface. The first insulating layer is disposed on the second surface. The second insulating layer is disposed on the first insulating layer. The second insulating layer includes a third surface, a fourth surface opposite to the third surface, and a second side surface connecting the third surface and the fourth surface. The connecting element is disposed on the second insulating layer and is electrically connected to the electronic unit. The third surface of the second insulating layer is in contact with the second surface of the electronic unit.

Description

Electronic device and method of manufacturing the same

The present disclosure relates to an electronic device and a manufacturing method thereof, and in particular to an electronic device including a first insulating layer and a second insulating layer and a manufacturing method thereof.

Generally speaking, a packaging process is performed on an electronic unit to enable the electronic unit to resist pollutants in the external environment, prevent damage to the electronic unit caused by manual operation, achieve fixed functions and/or achieve heat dissipation functions, thereby improving the reliability and/or other electrical performance of the electronic unit.

In the current packaging process, a protective layer is often placed on the electronic unit to achieve the above advantages of executing the packaging process. However, as users' demands for electronic devices increase, the size of electronic units and their components is gradually decreasing. Directly placing a protective layer on a small-sized electronic unit will lead to many problems such as insufficient circuit design space, easy disconnection, easy short circuit, and easy leakage current.

Therefore, although existing electronic devices and their manufacturing methods have gradually met their intended uses, they still do not fully meet the requirements in all aspects. Therefore, there are still some problems to be overcome regarding electronic devices and their manufacturing methods.

In some embodiments, an electronic device is provided. The electronic device includes an electronic unit, a first insulating layer, a second insulating layer and a connecting element. The electronic unit includes a first surface, a second surface opposite to the first surface and a first side surface connecting the first surface and the second surface. The first insulating layer is disposed on the second surface. The second insulating layer is disposed on the first insulating layer. The second insulating layer includes a third surface, a fourth surface opposite to the third surface and a second side surface connecting the third surface and the fourth surface. The connecting element is disposed on the second insulating layer and is electrically connected to the electronic unit. The third surface of the second insulating layer contacts the second surface of the electronic unit.

In some embodiments, a method for manufacturing an electronic device is provided. The manufacturing method includes providing a substrate. The substrate includes a plurality of electronic units. A first insulating layer is provided on the substrate. A second insulating layer is provided on the substrate. The second insulating layer contacts a portion of a surface of the plurality of electronic units.

The electronic device disclosed herein can be applied to various types of electronic equipment. To make the features and advantages of the present disclosure more clearly understood, various embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

The following is a detailed description of the electronic devices of each embodiment of the present disclosure. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific elements and arrangements described below are only for simply and clearly describing some embodiments of the present disclosure. Of course, these are only used for exemplification and not for limiting the present disclosure. In addition, similar and/or corresponding element symbols may be used in different embodiments to indicate similar and/or corresponding elements to clearly describe the present disclosure. However, the use of these similar and/or corresponding element symbols is only for simply and clearly describing some embodiments of the present disclosure, and does not represent any correlation between the different embodiments and/or structures discussed.

It should be understood that relative terms may be used in various embodiments, such as "lower" or "bottom" or "higher" or "top" to describe the relative relationship of one element of the diagram to another element. It is understood that if the device in the diagram is turned upside down, the element described on the "lower" side will become the element on the "higher" side. The embodiments of the present disclosure can be understood in conjunction with the drawings, and the drawings of the present disclosure are also considered part of the disclosure.

Furthermore, when a first material layer is mentioned as being located on or above a second material layer, it may include a situation where the first material layer is in direct contact with the second material layer or the first material layer and the second material layer may not be in direct contact, that is, there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly located on the second material layer, it means that the first material layer and the second material layer are in direct contact.

In addition, it should be understood that the ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify the elements, and they themselves are not intended to imply or represent any previous ordinal numbers of the (or those) elements, nor do they represent the order of one element and another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The patent application and the specification may not use the same terms. For example, the first element in the specification may be the second element in the patent application.

In some embodiments of the present disclosure, terms such as "connected", "interconnected", "joined", etc., unless otherwise specifically defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, with other structures disposed between the two structures. Such terms may also include situations where both structures are movable, or both structures are fixed. In addition, the terms "electrically connected" or "electrically coupled" include any direct and indirect electrical connection means.

In the text, the terms "about", "approximately", and "substantially" usually mean within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range. The quantities given here are approximate quantities, that is, in the absence of specific description of "about", "approximately", and "substantially", the meanings of "about", "approximately", and "substantially" can still be implied. The term "ranging from a first value to a second value" means that the range includes the first value, the second value, and other values therebetween. Furthermore, any two values or directions used for comparison may have a certain error. If the first value is equal to the second value, it implies that there may be an error of about 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

Furthermore, it should be understood that according to the embodiments of the present disclosure, a scanning electron microscope (SEM), an optical microscope (OM), a film thickness profiler (α-step), an elliptical thickness gauge, or other suitable methods may be used to measure the width, thickness or height of each element, and the spacing or distance between elements. Specifically, according to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional structural image including the element to be measured, and the width, thickness, height or angle of each element, and the spacing or distance between elements may be measured.

Certain terms are used throughout the specification and patent applications in this disclosure to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same component by different names. This document is not intended to distinguish between components that have the same function but different names. In the following specification and patent applications, the words "include", "contain", "have" and the like are open-ended words, and therefore should be interpreted as "including but not limited to..." Therefore, when the terms "include", "contain" and/or "have" are used in the description of this disclosure, they specify the existence of corresponding features, regions, steps, operations and/or components, but do not exclude the existence of one or more corresponding features, regions, steps, operations and/or components.

It should be understood that the following embodiments may replace, reorganize, or combine features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. Features between embodiments may be combined and used in any manner as long as they do not violate the spirit of the invention or conflict with each other.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

In this document, each direction is not limited to three axes of a rectangular coordinate system such as the X-axis, the Y-axis, and the Z-axis, and can be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, hereinafter, the X-axis direction is the first direction D1 (width direction), and the Z-axis direction is the second direction D2 (thickness direction). In some embodiments, the cross-sectional schematic diagrams described herein are schematic diagrams for observing the XZ plane.

In the present disclosure, the electronic device may include a display device, a lighting device, an antenna device, a sensing device, or a titling device, but is not limited thereto. The electronic device may be a foldable or flexible electronic device. The display device may be a non-self-luminous display device or a self-luminous display device. The antenna device may be a liquid crystal antenna device or a non-liquid crystal antenna device, and the sensing device may be a sensing device for sensing capacitance, light, heat, or ultrasound, but is not limited thereto. In the present disclosure, the electronic device may include an electronic unit. The electronic unit may be, for example, a known good die (KGD) (i.e., a known good chip), a semiconductor chip, or a diode, but is not limited thereto. The electronic unit may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode or a photodiode. The light-emitting diode may, for example, include an organic light emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED, or a quantum dot light-emitting diode (quantum dot LED), but is not limited thereto. The splicing device may, for example, be a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any arrangement or combination of the foregoing, but is not limited thereto. The following will illustrate the content of the present disclosure using an electronic device including an electronic unit, but the present disclosure is not limited thereto.

In addition, the shape of the electronic device can be rectangular, circular, polygonal, with curved edges or other suitable shapes. The electronic device can have peripheral systems such as processing systems, drive systems, control systems, light source systems, rack systems, etc. to support the electronic device or splicing device. It should be noted that the electronic device can be any combination of the above arrangements, but is not limited thereto.

It should be understood that in some embodiments, additional operating steps may be provided before, during, and/or after the method of manufacturing an electronic device. In some embodiments, some of the operating steps described may be replaced or omitted, and the order of some of the operating steps described may be interchangeable. In addition, it should be understood that some of the described steps may be replaced or deleted for other embodiments of the method.

In some embodiments, the manufacturing method of the electronic device disclosed herein is applicable to a chip first process and a redistribution layer first (RDL first) process. In some embodiments, the manufacturing method of the electronic device disclosed herein is applicable to a face up process and a face down process. For ease of explanation, the face down chip first process is used as an example below, but the disclosure is not limited thereto. In addition, in the disclosure, the number and size of each component in the drawings are for illustration only and are not intended to limit the scope of the disclosure.

Referring to FIG. 1, it is a schematic cross-sectional view of an electronic device at an intermediate manufacturing stage according to some embodiments of the present disclosure. As shown in FIG. 1, a substrate SB is provided, and the substrate SB includes a plurality of electronic units 10. In some embodiments, the substrate SB may be a silicon wafer, a semiconductor on an insulating layer (SOI) substrate, other suitable substrates, or a combination thereof, but the present disclosure is not limited thereto. Individual electronic units 10 are isolated from each other by a dotted line CL1, wherein the dotted line CL1 is, for example, a virtual first cutting line CL1, and a cutting process will be used in a subsequent process to separate each electronic unit 10 and the remaining subsequently formed components along the virtual first cutting line CL1.

In some embodiments, each of the plurality of electronic units 10 may include light-emitting elements such as pixels, light-emitting diodes, photodiodes; conductive elements such as metal layers, wires, vias, and bonding pads; driving elements such as transistors; functional layers such as insulating layers, interlayer dielectric layers, passivation layers, planarization layers, and dielectric materials; other suitable components, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the electronic unit 10 may be a die, a chip unit, other suitable units, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the electronic unit 10 may include a bottom surface 10B (first surface), a top surface 10T (second surface) opposite to the bottom surface 10B, and a side surface 10S connecting the bottom surface 10B and the top surface 10T.

In some embodiments, as shown in FIG. 1 , the substrate SB may include at least two electronic units 10, but the present disclosure is not limited thereto. For example, the substrate SB may include any natural number of electronic units 10 greater than 2. In some embodiments, the electronic units 10 may be arranged in a matrix in the substrate SB.

In some embodiments, each of the plurality of electronic units 10 may include a connection pad 12 for electrically connecting to other components. In some embodiments, the connection pad 12 may include a conductive material. For example, the conductive material may include a metal, a metal nitride, a semiconductor material, any other suitable conductive material, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the conductive material may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), silver (Ag), magnesium (Mg), alloys thereof or compounds thereof, other suitable conductive materials, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the conductive material may include a transparent conductive oxide (TCO), for example, indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), antimony tin oxide (ATO), other suitable transparent conductive materials, or a combination thereof, but the present disclosure is not limited thereto.

In some embodiments, the connection pad 12 may be formed by, for example, chemical vapor deposition (CVD), sputtering, resistive thermal evaporation, electron beam evaporation, physical vapor deposition (PVD), other suitable deposition processes, or a combination thereof, but the present disclosure is not limited thereto.

In some embodiments, a single electronic unit 10 may include a plurality of connection pads 12. For example, as shown in FIG. 1, a single electronic unit 10 may include four connection pads 12, but the present disclosure is not limited thereto. According to electrical requirements, the electronic unit 10 may include any natural number of connection pads 12. In some embodiments, for ease of explanation, FIG. 1 shows that the top surface of the connection pad 12 is flush with the top surface 10T of the electronic unit 10, but this is not limited thereto. The top surface of the connection pad 12 may be higher than the top surface 10T of the electronic unit 10.

As shown in FIG. 1 , in some embodiments, a first insulating layer 20 is provided on a substrate SB. In some embodiments, the first insulating layer 20 is provided on a top surface 10T of the electronic unit 10, so that a bottom surface 20B of the first insulating layer 20 contacts the top surface 10T of the electronic unit 10. In some embodiments, the first insulating layer 20 can be formed on the electronic unit 10 by, for example, chemical vapor deposition (CVD), sputtering, resistive thermal evaporation, electron beam evaporation, other suitable deposition methods, or a combination thereof.

In some embodiments, the first insulating layer 20 may be or may include an organic material, an inorganic material, other suitable insulating materials, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the first insulating layer 20 may be or may include a polymer-based dielectric film such as an organic polymer film. In some embodiments, the first insulating layer 20 may be or may include an Ajinomoto Build-up Film (ABF), epoxy resin, silicone resin, benzocyclobutene (BCB), polyimide (PI) such as photosensitive polyimide (PSPI), polybenzoxazole (PBO), oxides such as silicon oxide ( _SiOx ), nitrides such as silicon nitride ( _SiNx ), silicon oxynitride ( _{SiOxNy )} or the like. ) of nitride oxide, other suitable build-up materials, other suitable insulating materials, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the first insulating layer 20 may be or may include a molding material.

In some embodiments, the side surface 20S of the first insulating layer 20 is spaced apart from the outermost surface 10S of the plurality of electronic units 10 by a distance d. For details, please refer to FIG. 1, which is a cross-sectional schematic diagram, and the distance d is the width from the bottom of the side surface 20S of the first insulating layer 20 to the outermost surface 10S of the plurality of electronic units 10 in the first direction D1. In some embodiments, the side surface 20S of the first insulating layer 20 is not aligned with the outermost surface 10S of the electronic unit 10 in the first direction D1. In some embodiments, the area of the bottom surface 20B of the first insulating layer 20 is smaller than the area of the top surfaces 10T of the plurality of electronic units 10. In other words, the projection of the first insulating layer 20 on the top surfaces 10T of the plurality of electronic units 10 may fall within the top surfaces 10T of the plurality of electronic units 10. In some embodiments, by providing the first insulating layer 20 having an area smaller than the top surfaces 10T of the plurality of electronic units 10, the difficulty of cutting in the subsequent first cutting process may be reduced, thereby increasing the margin of the first cutting process, but the present invention is not limited thereto.

In some embodiments, the side surface 20S of the first insulating layer 20 is an inclined side surface. In some embodiments, the side surface 20S of the first insulating layer 20 and the bottom surface 20B of the first insulating layer 20 have an angle a20. In some embodiments, the angle a20 may be greater than or equal to about 45 degrees and less than about 90 degrees. For example, the angle a20 may be 45 degrees, 50 degrees, 55 degrees, 60 degrees, 65 degrees, 70 degrees, 75 degrees, 80 degrees, 85 degrees, 89 degrees or any value or range of values therebetween. In some embodiments, since the side surface 20S of the first insulating layer 20 has the angle a20, it is helpful to improve the adhesion and/or reliability between the component disposed above the first insulating layer 20 and the first insulating layer 20.

Referring to FIG. 2, it is a schematic cross-sectional view of an electronic device at an intermediate manufacturing stage according to some embodiments of the present disclosure. As shown in FIG. 2, the first insulating layer 20 is patterned to form first openings (or vias) 22, 24 and expose a portion of the top surface 10T of the electronic unit 10. In some embodiments, a corresponding patterning process can be selected according to the material of the first insulating layer 20. For example, when the first insulating layer 20 is a photoresist material, the first insulating layer 20 can be patterned by an exposure process and a development process. For example, when the first insulating layer 20 is a non-photoresist material, the first insulating layer 20 can be patterned by laser drilling, or a photoresist pattern can be further provided on the first insulating layer 20 to pattern the first insulating layer 20, or other suitable process methods can be adopted, but are not limited thereto.

In some embodiments, the first insulating layer 20 may be patterned according to the location of the connection pads 12 on the electronic unit 10. For example, each of the plurality of connection pads 12 may correspond to a first opening 22, but the present disclosure is not limited thereto. In some embodiments, along the first direction D1, the width of the first opening 24 between adjacent electronic units 10 may be greater than the width of the first opening 22, so as to facilitate the separation of adjacent electronic units 10 from each other during the subsequent first cutting process. As shown in FIG. 2, the first opening 22 may have an angle a22. In some embodiments, the angle a22 may be greater than or equal to approximately 90 degrees and less than approximately 180 degrees. For example, the angle a22 can be 90 degrees, 100 degrees, 110 degrees, 120 degrees, 130 degrees, 140 degrees, 150 degrees, 160 degrees, 170 degrees, 179 degrees or any value or range of values therebetween. In some embodiments, the angle a22 can be adjusted by adjusting the process parameters of the patterning process.

Referring to FIG. 3 , it is a schematic cross-sectional view of an electronic device at an intermediate manufacturing stage according to some embodiments of the present disclosure. As shown in FIG. 3 , a first conductive layer 30 is provided on the first insulating layer 20 . In some embodiments, the material and the forming method of the first conductive layer 30 may be the same as or different from the material and the forming method of the connection pad 12 . In some embodiments, the first conductive layer 30 may be formed on the first insulating layer 20 in a conformal manner and the first conductive layer 30 extends into the first openings 22 , 24 . Then, the first conductive layer 30 may be patterned to expose a portion of the top surface 10T of the electronic unit 10 and a portion of the side surface 20S and the top surface 20T of the first insulating layer 20 . For example, the first conductive layer 30 is conformably disposed and extends into the first openings 22 and 24. According to some embodiments, the top surface of the first conductive layer 30 corresponding to the first openings 22 and 24 may have a recess R. Furthermore, in the second direction D2, the top surface of the first conductive layer 30 corresponding to the first openings 22 and 24 is higher than the top surface 20T of the first insulating layer 20 and the top surface of the first conductive layer 30 corresponding to the first openings 22 and 24 is lower than the top surface of the first conductive layer 30 corresponding to the first insulating layer 20. The first conductive layer 30 described in the present disclosure may be a single layer of conductive material or multiple layers of conductive material, and the first conductive layer 30 may include copper, titanium, aluminum, molybdenum, indium tin oxide, other suitable materials or a combination thereof, but is not limited thereto.

In some embodiments, the patterned first conductive layer 30 may correspond to one of the plurality of first openings 22 of the first insulating layer 20. In other embodiments, the patterned first conductive layer 30 may correspond to a plurality of first openings 22 of the plurality of first openings 22 of the first insulating layer 20. For example, the patterned first conductive layer 30 may correspond to two first openings 22, but the present disclosure is not limited thereto, and the patterned first conductive layer 30 may correspond to any natural number of first openings 22 to enhance the fan-out characteristics and/or fan-out range of the first conductive layer 30. The improved fan-out characteristics may include increasing the number of components and bonding capabilities for bonding with other component pairs, and the improved fan-out range means increasing the fan-out area to avoid space cramping during circuit design, but is not limited thereto. In some embodiments, the first conductive layer 30 may be between the first insulating layer 20 and the second insulating layer 40 (see FIG. 4 ) formed subsequently. The first conductive layer 30 is electrically connected to the connection pad 12 of the electronic unit 10 through one of the plurality of first openings 22 .

In other embodiments, a seed layer (not shown) may be first conformally formed on the first insulating layer 20 and in the first openings 22 and 24, and then a metal layer may be formed on the seed layer. The materials of the seed layer and the metal layer may include, for example, titanium and copper, but are not limited thereto. Then, the metal layer and the seed layer are patterned to remove a portion of the metal layer and a portion of the seed layer, thereby exposing a portion of the top surface 10T of the electronic unit 10.

Referring to FIG. 4 , it is a schematic cross-sectional view of an electronic device at an intermediate manufacturing stage according to some embodiments of the present disclosure. As shown in FIG. 4 , a second insulating layer 40 is provided on the substrate SB (as shown in FIG. 1 ). Specifically, the second insulating layer 40 is formed on the top surface 10T of the electronic unit 10, the top surface 20T and the side surface 20S of the first insulating layer 20, the first opening 24, and the first conductive layer 30. In some embodiments, the second insulating layer 40 may include a bottom surface 40B (third surface), a top surface 40T (fourth surface) opposite to the bottom surface 40B, and a side surface 40S (second side surface) connecting the bottom surface 40B and the top surface 40T. In some embodiments, the top surface 40T of the second insulating layer 40 is farther from the electronic unit 10 than the bottom surface 40B of the second insulating layer 40.

In some embodiments, the material and the forming method of the second insulating layer 40 may be the same as or different from the material and the forming method of the first insulating layer 20. In some embodiments, since the materials of the first insulating layer 20 and the second insulating layer 40 are different, the first insulating layer 20 and the second insulating layer 40 may substantially have an interface. Hereinafter, the case where the materials of the first insulating layer 20 and the second insulating layer 40 are different is taken as an example for explanation.

In some embodiments, as shown in FIG. 4 , the first insulating layer 20 may have a first thickness T1, and the second insulating layer 40 may have a second thickness T2. In some embodiments, the first thickness T1 of the first insulating layer 20 is a distance between the bottom surface 20B and the top surface 20T of the first insulating layer 20 in the second direction D2. In some embodiments, the second thickness T2 of the second insulating layer 40 is a distance between the top surface 20T of the first insulating layer 20 and the top surface 40T of the second insulating layer 40 in the second direction D2.

In some embodiments, the first thickness T1 of the first insulating layer 20 may be greater than or equal to about 2 um and less than or equal to about 10 um. For example, the first thickness T1 may be 2 um, 3 um, 4 um, 5 um, 6 um, 7 um, 8 um, 9 um, 10 um, any value or range of values therebetween. In some embodiments, the second thickness T2 of the second insulating layer 40 may be greater than or equal to about 13 um and less than or equal to about 50 um. For example, the second thickness T2 may be 13 um, 15 um, 20 um, 25 um, 30 um, 35 um, 40 um, 45 um, 50 um, any value or range of values therebetween. In some embodiments, the first thickness T1 of the first insulating layer 20 may be less than the second thickness T2 of the second insulating layer 40. In some embodiments, the ratio (T1/T2) of the first thickness T1 of the first insulating layer 20 to the second thickness T2 of the second insulating layer 40 may be greater than or equal to about 0.02 to less than or equal to about 0.85. For example, the ratio (T1/T2) may be 0.02, 0.04, 0.08, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.75, 0.8, 0.85, any value or range of values therebetween.

In some embodiments, since the first thickness T1 of the first insulating layer 20 may be less than the second thickness T2 of the second insulating layer 40, the connection pad 12 may be gradually fanned out by stacking the first insulating layer 20 and the second insulating layer 40. For example, the connection pad 12 may be initially fanned out through the first opening 22 of the first insulating layer 20, and then the connection pad 12 may be further fanned out through the second opening 42 of the second insulating layer 40 (see FIG. 5 below), thereby improving the fan-out effect and/or fan-out range. In other embodiments, the electronic device may further dispose other insulating layers with openings between the top surface 10T of the electronic unit 10 and the subsequently formed connection element 60 (see FIG. 13 ), thereby improving the fan-out effect and/or fan-out range.

It should be particularly noted that the first insulating layer 20 and the second insulating layer 40 can simultaneously serve as protective layers for the electronic unit 10, thereby fully protecting the electronic unit 10 from damage. Furthermore, by sequentially arranging the first insulating layer 20 and the second insulating layer 40 on the electronic unit 10, the problem of a single protective layer being easily broken and/or having edge warping after cutting can be reduced during the subsequent cutting process. In addition, since the present disclosure provides the first insulating layer 20 and the second insulating layer 40 by stacking them multiple times, the problem of difficulty in accurately forming an opening penetrating a single thick insulating layer can be avoided.

It is also particularly noted that, as shown in FIG. 3 and FIG. 4 , since the patterned first conductive layer 30 exposes a portion of the top surface 10T of the electronic unit 10, the bottom surface 40B of the second insulating layer 40 is in direct contact with the top surfaces 10T of the plurality of electronic units 10, thereby improving the reliability of the subsequent cutting process. For example, since there are fewer components intersecting with the virtual first cutting line CL1 described later, the problem of uneven cutting edges, cracks and/or warping after cutting along the virtual first cutting line CL1 can be reduced.

In some embodiments, as shown in FIG. 4 , the second insulating layer 40 is in direct contact with the side surface 20S of the first insulating layer 20. In some embodiments, since the inclined side surface 20S of the first insulating layer 20 has the above-mentioned angle a20, the first insulating layer 20 and the second insulating layer 40 can be more easily bonded. Furthermore, when the materials of the first insulating layer 20 and the second insulating layer 40 are different, the angle a20 can disperse the stress between the heterojunctions of the first insulating layer 20 and the second insulating layer 40 and/or can improve the reliability of the heterojunctions of the first insulating layer 20 and the second insulating layer 40.

In some embodiments, the coefficient of thermal expansion (CTE) of the first insulating layer 20 and the second insulating layer 40 may be the same or different. In some embodiments, the coefficient of thermal expansion of the first insulating layer 20 and/or the second insulating layer 40 may be greater than or equal to about 3 ppm/K to less than or equal to about 60 ppm/K. For example, the thermal expansion coefficient of the first insulating layer 20 and/or the second insulating layer 40 may be 3 ppm/K, 5 ppm/K, 10 ppm/K, 15 ppm/K, 20 ppm/K, 25 ppm/K, 30 ppm/K, 35 ppm/K, 40 ppm/K, 45 ppm/K, 50 ppm/K, 55 ppm/K, 60 ppm/K, or any value or range of values therebetween. In some embodiments, when the thermal expansion coefficients of the first insulating layer 20 and the second insulating layer 40 are different, the warping degree of the electronic device can be reduced. In some embodiments, the thermal expansion coefficient of the first insulating layer 20 is smaller than the thermal expansion coefficient of the second insulating layer 40, so that the warping of the electronic device can be reduced, but the present invention is not limited thereto.

In some embodiments, the first insulating layer 20 and the second insulating layer 40 may be oppositely warped layers. In other words, because the first insulating layer 20 and the second insulating layer 40 have different warping directions, they can offset each other's warping phenomenon, thereby reducing the warping degree of the electronic device. For example, the first insulating layer 20 may be an insulating layer that is curved upward toward the second direction D2 (opening upward), and the second insulating layer 40 may be an insulating layer that is curved downward away from the second direction D2 (opening downward), so that when the first insulating layer 20 and the second insulating layer 40 are combined, the curvatures can offset each other.

In some embodiments, the Young’s modulus of the first insulating layer 20 and/or the second insulating layer 40 may be greater than or equal to about 1000 MPa to less than or equal to about 20000 MPa. For example, the Young’s modulus of the first insulating layer 20 and/or the second insulating layer 40 may be 1000 MPa, 2000 MPa, 4000 MPa, 6000 MPa, 8000 MPa, 10000 MPa, 12000 MPa, 14000 MPa, 16000 MPa, 18000 MPa, 20000 MPa, or any value or range of values therebetween. In some embodiments, the Young's modulus of the first insulating layer 20 is smaller than the Young's modulus of the second insulating layer 40. Therefore, forming the second insulating layer 40 on the top surface 10T of the electronic unit 10, the top surface 20T and the side surface 20S of the first insulating layer 20, the first opening 24 and the first conductive layer 30 can avoid or reduce the risk of damage such as scratches to the electronic unit 10, the first insulating layer 20 or the first conductive layer 30, but is not limited thereto.

In some embodiments, since the water and oxygen resistance of the second insulating layer 40 is better than that of the first insulating layer 20, the water and oxygen resistance of the electronic device of the present disclosure can be further improved by providing the second insulating layer 40. In some embodiments, since the hardness of the second insulating layer 40 is greater than that of the first insulating layer 20, the hardness of the electronic device of the present disclosure can be further improved by providing the second insulating layer 40. In these embodiments, even if the water and oxygen resistance and/or hardness of the first insulating layer 20 is slightly lower than the water and oxygen resistance and/or hardness of the second insulating layer 40, the first insulating layer 20 can be accurately and easily formed on the electronic unit 10 and helps to form the first opening 22. Therefore, the combination of the first insulating layer 20 and the second insulating layer 40 can effectively improve various properties of the electronic device.

In some embodiments, since the first thickness T1 of the first insulating layer 20 is less than the second thickness T2 of the second insulating layer 40, the first insulating layer 20 may include PSPI, which is easier to perform a precise patterning process, and the second insulating layer 40 may include ABF, so as to enhance the fan-out effect and/or fan-out range by the thickness ratio and material selection between the first insulating layer 20 and the second insulating layer 40.

Referring to FIG. 5 , it is a schematic cross-sectional view of an electronic device at an intermediate manufacturing stage according to some embodiments of the present disclosure. As shown in FIG. 5 , the second insulating layer 40 is patterned to form a second opening 42 and expose the top surface of the first conductive layer 30. In some embodiments, the second opening 42 may have an angle a42. In some embodiments, the angle a42 may be greater than or equal to 90 degrees and less than 180 degrees. For example, the angle a42 may be 90 degrees, 100 degrees, 110 degrees, 120 degrees, 130 degrees, 140 degrees, 150 degrees, 160 degrees, 170 degrees, 179 degrees, or any value or range of values therebetween. In some embodiments, the angle a42 may be adjusted by adjusting the process parameters of the patterning process.

In some embodiments, the angle a22 of one of the plurality of first openings 22 is different from the angle a42 of one of the plurality of second openings 42. In some embodiments, the angle a22 of the first opening 22 is greater than the angle a42 of the second opening 42, for example, to quickly conduct heat generated by the electronic unit 10, but not limited thereto.

In some embodiments, the roughness of the first sidewall 22S of one of the plurality of first openings 22 may be smaller than that of the second sidewall 42S of one of the plurality of second openings 42. In the present disclosure, the roughness may be surface roughness, and may be obtained by, for example, arithmetic mean roughness (Ra), maximum height (Ry), ten-point mean roughness (Rz), other similar measurement methods, or a combination thereof. In some embodiments, since the first thickness T1 of the first insulating layer 20 may be smaller than the second thickness T2 of the second insulating layer 40, the thickness of the conductive component (e.g., the first conductive layer 30) disposed in the first opening 22 of the first insulating layer 20 is correspondingly smaller than the thickness of the conductive component (e.g., the subsequent connecting element 60) disposed in the second opening 42 of the second insulating layer 40. Therefore, when the roughness of the first sidewall 22S of the first opening 22 is smaller and thus has a smoother sidewall, it can help to accurately form the first conductive layer 30 in the first opening 22, thereby improving the reliability of the first conductive layer 30. In addition, since the first thickness T1 of the first insulating layer 20 is smaller than the second thickness T2 of the second insulating layer 40 , the forming accuracy of the first opening 22 is greater than the forming accuracy of the second opening 42 .

On the other hand, when the second sidewall 42S of the second opening 42 has a greater roughness and thus has a more uneven sidewall, the friction of the rough sidewall can help form a connection element 60 with a greater thickness and/or a greater width in the second opening 42, thereby improving the reliability of the connection element 60. For example, the reliability of the connection element 60 formed by a subsequent electroplating process can be improved.

In some embodiments, at least one of the plurality of first openings 22 and at least one of the plurality of second openings 42 do not overlap in the normal direction of the electronic unit 10 (i.e., the second direction D2), thereby improving the fan-out effect and/or fan-out range or reducing the risk of cracking of the metal layer of the electronic device, but not limited thereto. In other embodiments, each of the plurality of first openings 22 and each of the plurality of second openings 42 do not overlap in the normal direction of the electronic unit 10 (i.e., the second direction D2). In some embodiments, at least one of the plurality of first openings 22 and at least one of the plurality of second openings 42 overlap in the normal direction of the electronic unit 10 (i.e., the second direction D2), thereby improving the margin of the patterning process of the second insulating layer 40. In some other embodiments, each of the plurality of first openings 22 overlaps with each of the plurality of second openings 42 in the normal direction of the electronic unit 10 (ie, the second direction D2 ).

In some embodiments, following the above, a first cutting process may be performed to cut the substrate SB so that the plurality of electronic units 10 are separated into a plurality of first electronic devices. In some embodiments, the first cutting process may include a blade saw process, a die break dicing process, a laser cutting process, other suitable cutting processes or a combination thereof. As shown in FIG. 5 , the first cutting process may be performed along a virtual first cutting line CL1.

Referring to FIG. 6 , it is a schematic cross-sectional view of the first electronic device 1 after the first cutting process according to some embodiments of the present disclosure. In some embodiments, the first electronic device 1 may be a known good die (KGD), and the first electronic device 1 may include a first conductive layer 30 that may be used as a redistribution layer for wafer-level packaging. As shown in FIG. 6 , after the first cutting process, the side surface 10S of the electronic unit 10 of the first electronic device 1 is aligned with the side surface 40S of the second insulating layer 40, so that the second insulating layer 40 protects the electronic unit 10 of the first electronic device 1. That is, in the first direction D1, the distance between the side surface 10S of the electronic unit 10 and the side surface 40S of the second insulating layer 40 is less than or equal to 5 microns. The alignment design of the side surface 10S of the electronic unit 10 and the side surface 40S of the second insulating layer 40 will be beneficial to the quality of subsequent processes.

In addition, it should be understood that, for the sake of clarity, some components of the first electronic device 1 are omitted in FIG. 6 , and some components are schematically illustrated. In some embodiments, additional components may be added to the first electronic device 1. In other embodiments, some components of the first electronic device 1 described above may be replaced or omitted.

Referring to FIG. 7 , a schematic cross-sectional view of a second electronic device 2 in an intermediate manufacturing stage is shown according to some embodiments of the present disclosure. As shown in FIG. 7 , a plurality of first electronic devices 1 are provided on a first carrier board CP1. For ease of explanation, FIG. 7 shows that two first electronic devices 1 are provided on the first carrier board CP1, but the present disclosure is not limited thereto.

In detail, in some embodiments, as shown in FIG. 7 , a first carrier CP1 is provided, and a first adhesive layer AL1 is disposed on the first carrier CP1. In some embodiments, the first carrier CP1 may be or may include a wafer, a chip, glass, quartz, sapphire, ceramic, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET) carrier, polypropylene (PP) carrier, temporary carrier, other suitable carriers or a combination thereof, but the present disclosure is not limited thereto.

In some embodiments, the first adhesive layer AL1 may be used as a peeling layer or a release layer. In some embodiments, the first adhesive layer AL1 may be or may include a pyrolytic adhesive, an ultraviolet (UV) adhesive layer, a light-to-heat conversion (LTHC) adhesive layer, other suitable cleavage-type adhesive layers, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the first adhesive layer AL1 may be formed by a coating process or other suitable forming process. Then, the first electronic device 1 shown in FIG. 6 is flipped up and down along the second direction D2 so that the top surface 40T of the second insulating layer 40 of the first electronic device 1 is in direct contact and bonding with the first adhesive layer AL1.

As shown in FIG. 7 , in some embodiments, a third insulating layer 50 is provided on a plurality of first electronic devices 1. In some embodiments, the third insulating layer 50 may surround the electronic unit 10 in the first electronic device 1. For example, the third insulating layer 50 may surround the side surface 10S and the bottom surface 10B of the electronic unit 10. In some embodiments, the third insulating layer 50 may be disposed on the first adhesive layer AL1 and between adjacent first electronic units 10. In some embodiments, the third insulating layer 50 may be disposed on the side surface 40S of the second insulating layer 40, the side surface 10S of the electronic unit 10, and the bottom surface 10B of the electronic unit 10. In some embodiments, the third insulating layer 50 may expose a portion of the side surface 40S of the second insulating layer 40 and/or a portion of the side surface 10S of the electronic unit 10. By aligning the side surface 10S of the electronic unit 10 with the side surface 40S of the second insulating layer 40, for example, the risk of cracking of the side surface 10S, the side surface 40S and the third insulating layer 50 may be reduced, but the present invention is not limited thereto.

In some embodiments, the third insulating layer 50 may be or may include an organic material, an inorganic material, other suitable packaging materials, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the aforementioned inorganic material may include silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, other suitable materials, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the aforementioned organic material may include epoxy resin, silicone resin, acrylic resins, other suitable materials, or a combination thereof, but the present disclosure is not limited thereto. For example, the acrylic resin may include polymethylmethacrylate (PMMA), benzocyclobutene (BCB), polyimide, copolyester (polyester), polydimethylsiloxane (PDMS), polyfluoroalkoxy (PFA). In some embodiments, the third insulating layer 50 may include ABF. In some embodiments, the third insulating layer 50 may be a light-transmitting, semi-transmitting, or opaque material.

In some embodiments, as shown in FIG. 7 , the third insulating layer 50 may have a fifth thickness T5. In some embodiments, the fifth thickness T5 may be a distance between a top surface 50T of the third insulating layer 50 and a bottom surface 50B of the third insulating layer 50. In some embodiments, the fifth thickness T5 of the third insulating layer 50 may be greater than the second thickness T2 of the second insulating layer 40. In some embodiments, the fifth thickness T5 of the third insulating layer 50 may be greater than the first thickness T1 of the first insulating layer 20. In some embodiments, the fifth thickness T5 of the third insulating layer 50 may be greater than the sum of the second thickness T2 of the second insulating layer 40 and the first thickness T1 of the first insulating layer 20 .

Referring to FIG. 8, a cross-sectional schematic diagram of the second electronic device 2 in an intermediate manufacturing stage is shown according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 8, a second carrier CP2 is provided, and a second adhesive layer AL2 is disposed on the second carrier CP2. In some embodiments, the material of the second carrier CP2 may be the same as or different from the material of the first carrier CP1. In some embodiments, the material and formation method of the second adhesive layer AL2 may be the same as or different from the material and formation method of the first adhesive layer AL1. Then, the structure shown in FIG. 7 is flipped up and down along the second direction D2 so that the bottom surface 50B of the third insulating layer 50 is directly in contact with and bonded to the second adhesive layer AL2.

Referring to FIG. 9 , a cross-sectional schematic diagram of the second electronic device 2 at an intermediate manufacturing stage is shown according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 9 , a corresponding cracking process can be used to release or remove the first adhesive layer AL1 and the first carrier CP1 according to the material of the first adhesive layer AL1, thereby exposing the top surface 50T of the third insulating layer 50.

Referring to FIG. 10 , a cross-sectional schematic diagram of the second electronic device 2 at an intermediate manufacturing stage is shown according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 10 , a first photoresist 52 is formed on the top surface 50T of the third insulating layer 50 and the top surface 40T of the second insulating layer 40. In some embodiments, the first photoresist 52 can be formed by a spin coating process, a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition (ALD) process, a high density plasma chemical vapor deposition (HDP-CVD) process, other suitable methods or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the first photoresist 52 can be a dry film photoresist. In some embodiments, the first photoresist 52 may have an opening 53, and the opening 53 corresponds to the second opening 42 of the second insulating layer 40 to expose at least a portion of the top surface of the first conductive layer 30. In some embodiments, one opening 53 of the first photoresist 52 may correspond to one of the second openings 42 of the second insulating layer 40, but the present disclosure is not limited thereto.

Referring to FIG. 11 , a cross-sectional schematic diagram of the second electronic device 2 at an intermediate manufacturing stage is shown according to some embodiments of the present disclosure. In some embodiments, a second conductive layer 62 is disposed in the opening 53 of the first photoresist 52. In some embodiments, the second conductive layer 62 may be disposed on the top surface 50T of the third insulating layer 50 and the top surface 40T of the second insulating layer 40. In some embodiments, a portion of the second conductive layer 62 contacts the top surface 50T of the third insulating layer 50. In some embodiments, the second conductive layer 62 may include a conductive material. For example, the conductive material may include a metal, a metal nitride, a semiconductor material or a combination thereof, or any other suitable conductive material, but the present disclosure is not limited thereto. In some embodiments, the conductive material may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), silver (Ag), magnesium (Mg), alloys or compounds thereof, other suitable conductive materials, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the second conductive layer 62 may be formed by, for example, electroplating, chemical vapor deposition (CVD), sputtering, resistive thermal evaporation, electron beam evaporation, other suitable deposition methods, or combinations thereof, but the present disclosure is not limited thereto.

In some embodiments, the first conductive layer 30 may have a third thickness T3 in the second direction D2. As shown in FIG. 11, the third thickness T3 of the first conductive layer 30 may be between the bottom surface of the second conductive layer 62 and the top surface 20T of the first insulating layer 20. In some embodiments, the second conductive layer 62 may have a fourth thickness T4 in the second direction D2. As shown in FIG. 11, the fourth thickness T4 of the second conductive layer 62 may be the thickness of the second conductive layer 62 located on the third insulating layer 50. In some embodiments, since the first conductive layer 30 may be a conductive layer in a wafer level package (WLP) process and the second conductive layer 62 may be a conductive layer in a panel level package (PLP) process, the fourth thickness T4 of the second conductive layer 62 may be greater than the third thickness T3 of the first conductive layer 30 .

In some embodiments, the second conductive layer 62 may include a multi-layer structure, wherein the multi-layer structure may include a seed layer and a metal layer. For example, a seed layer (not shown) may be formed on the top surface 50T of the third insulating layer 50, the top surface of the second insulating layer 40, and the second opening 42. Then, a metal layer (not shown) is formed on the seed layer to improve the reliability of the metal layer by the seed layer. In some embodiments, the seed layer and the metal layer may be formed by physical vapor deposition (PVD), electroplating, or other suitable formation processes, respectively, but the present disclosure is not limited thereto. In some embodiments, the seed layer may be a titanium-copper alloy (TiCu), and the metal layer may include copper.

Referring to FIG. 12 , a schematic cross-sectional view of a second electronic device 2 at an intermediate manufacturing stage is shown according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 12 , a second photoresist 54 is formed on the first photoresist 52. Specifically, the second photoresist 54 may be formed on the top surface of the first photoresist 52 and the second conductive layer 62. In some embodiments, the material and the forming method of the second photoresist 54 may be the same as or different from the material and the forming method of the first photoresist 52. In some embodiments, the second photoresist 54 may be a dry film photoresist. In some embodiments, the second photoresist 54 may have an opening 55, and the opening 55 corresponds to the second conductive layer 62, so as to expose at least a portion of the top surface of the second conductive layer 62 through the opening 55 of the second photoresist 54.

Referring to FIG. 13 , a schematic cross-sectional view of the second electronic device 2 at an intermediate manufacturing stage is shown according to some embodiments of the present disclosure. In some embodiments, a third conductive layer 64 is disposed in the opening 55 of the second photoresist 54. In some embodiments, the material and the forming method of the third conductive layer 64 may be the same as or different from the material and the forming method of the third conductive layer 64. In some embodiments, the third conductive layer 64 and the second conductive layer 62 may have an interface. In other embodiments, the third conductive layer 64 and the second conductive layer 62 may not have substantially an interface. In some embodiments, the third conductive layer 64 may also include a seed layer and a metal layer, so as to improve the reliability of the metal layer by the seed layer. In some embodiments, in the second direction D2, the thickness of the third conductive layer 64 may be greater than that of the second conductive layer 62 .

Referring to FIG. 14 , a cross-sectional schematic diagram of the second electronic device 2 at an intermediate manufacturing stage is shown according to some embodiments of the present disclosure. In some embodiments, the second photoresist 54 and the first photoresist 52 are removed to expose the top surface 40T of the second insulating layer 40. In some embodiments, the second photoresist 54 and the first photoresist 52 may be removed by an ashing process, other suitable removal processes, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the second photoresist 54 and the first photoresist 52 may be removed in the same process. In other embodiments, the second photoresist 54 and the first photoresist 52 may be removed separately in different processes. In some embodiments, due to the selectivity of the removal process, the removal process does not substantially destroy the structures of the third conductive layer 64 and the second conductive layer 62.

In some embodiments, the third conductive layer 64 and the second conductive layer 62 may be used together as a connection element 60 disposed on the second insulating layer 40. In other words, the connection element 60 may include, for example, the second conductive layer 62 and the third conductive layer 64. In some embodiments, the connection element 60 may be used as a redistribution element of an electronic device in a panel-level process. In some embodiments, the connection element 60 is connected to the connection pad 12 of the electronic unit 10 via the first conductive layer 30. In some embodiments, since the third conductive layer 64 is in direct contact and electrically connected to the second conductive layer 62, the second conductive layer 62 is in direct contact and electrically connected to the first conductive layer 30, and the first conductive layer 30 is in direct contact and electrically connected to the connection pad 12, the fan-out effect and/or fan-out range can be effectively improved.

Referring to FIG. 15 , a cross-sectional schematic diagram of the second electronic device 2 at an intermediate manufacturing stage is shown according to some embodiments of the present disclosure. In some embodiments, a fourth insulating layer 70 is provided on the connecting element 60, the third insulating layer 50 and the second insulating layer 40. In some embodiments, the fourth insulating layer 70 covers the side surface of the connecting element 60. In some embodiments, the fourth insulating layer 70 is in direct contact with the third insulating layer 50 and the second insulating layer 40. In some embodiments, the material and the forming method of the fourth insulating layer 70 may be the same as or different from the material and the forming method of the third insulating layer 50. In some embodiments, the fourth insulating layer 70 may have an interface with the third insulating layer 50. In other embodiments, the fourth insulating layer 70 may not have substantially an interface with the third insulating layer 50. In some embodiments, the hardness of the third insulating layer 50 and/or the fourth insulating layer 70 is different from that of the first insulating layer 20 and/or the second insulating layer 40. For example, the hardness of the third insulating layer 50 and/or the fourth insulating layer 70 may be greater than that of the first insulating layer 20 and/or the second insulating layer 40.

Then, in some embodiments, a second cutting process may be performed to separate the plurality of first electronic devices 1 into a plurality of second electronic devices 2. In some embodiments, the second cutting process may be the same as or different from the first cutting process. As shown in FIG. 15 , the second cutting process may be performed along a virtual second cutting line CL2.

In other embodiments, the fourth insulating layer 70 may include a first sub-insulating layer and a second sub-insulating layer formed in different processes. In this embodiment, following FIG. 9, a patterned first sub-insulating layer may be formed on the third insulating layer 50. Then, a second conductive layer 62 is formed in the opening of the first sub-insulating layer and formed on the third insulating layer 50 and the second insulating layer 40. Then, a patterned second sub-insulating layer is formed on the patterned first sub-insulating layer. Thereafter, a third conductive layer 64 is formed in the opening of the second sub-insulating layer, and the third conductive layer 64 is formed on the second conductive layer 62, thereby obtaining the connecting element 60.

Referring to FIG. 16 , a cross-sectional schematic diagram of the second electronic device 2 after the second cutting process is shown according to some embodiments of the present disclosure. As shown in FIG. 16 , in the first direction D1, the side surface 50S of the third insulating layer 50 of the second electronic device 2 is aligned with the side surface 70S of the fourth insulating layer 70, so that the electronic unit 10 of the second electronic device 2 is protected by the fourth insulating layer 70 and the third insulating layer 50. As shown in FIG. 16 , in some embodiments, a connection pad 66 may be further disposed on the third conductive layer 64. Therefore, the second electronic device 2 may be electrically connected to a printed circuit board (PCB) or other components through the connection pad 66. In some embodiments, the material and formation method of the connection pad 66 may be the same as or different from the material and formation method of the connection pad 12. The second conductive layer 62, the third conductive layer 64 and the fourth insulating layer 70 are alternately stacked to form a redistribution layer of the second electronic device 2, thereby improving the fan-out characteristics and/or fan-out range of the electronic device.

In summary, according to the disclosed embodiments, an electronic device including a first insulating layer and a second insulating layer and a manufacturing method thereof are provided, so that problems such as cramped circuit design space such as vias, wires, and redistribution layers can be avoided by disposing the insulating layers in stages. In addition, by adjusting the thickness ratio and/or material properties (e.g., material type, thermal expansion coefficient, warp direction) of the first insulating layer and the second insulating layer, the fan-out characteristics and/or fan-out range of the electronic device can be improved, the compatibility with fine-diameter processes can be improved, the warpage probability can be reduced, the reliability can be improved, and/or the electrical performance can be improved. Furthermore, the electronic device and the manufacturing method thereof disclosed in the present invention are also compatible with a chip-first process and a redistribution layer-first process.

As long as the components between the embodiments of the present disclosure do not violate the spirit of the invention or conflict with each other, they can be mixed and matched at will. In addition, the scope of protection of the present disclosure is not limited to the process, machine, manufacture, material composition, device, method and step in the specific embodiment described in the specification. Any person with ordinary knowledge in the relevant technical field can understand from the content of the present disclosure that the process, machine, manufacture, material composition, device, method and step currently or developed in the future can be used according to the present disclosure as long as they can implement substantially the same function or obtain substantially the same result in the embodiment described herein. Therefore, the scope of protection of the present disclosure includes the above-mentioned process, machine, manufacture, material composition, device, method and step. Any embodiment or patent application scope of the present disclosure does not need to achieve all the purposes, advantages and/or features disclosed in the present disclosure.

Several embodiments are summarized above so that those with ordinary knowledge in the art to which the present disclosure belongs can better understand the perspectives of the embodiments of the present disclosure. Those with ordinary knowledge in the art to which the present disclosure belongs should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and/or advantages as the embodiments introduced herein. Those with ordinary knowledge in the art to which the present disclosure belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present disclosure.

1: first electronic device 10: electronic unit 10B, 20B, 40B, 50B: bottom surface 10T, 20T, 40T, 50T: top surface 10S, 20S, 40S, 50S, 70S: side surface 12, 66: connection pad 2: second electronic device 20: first insulating layer 22, 24: first opening 22S: first side wall 30: first conductive layer 40: second insulating layer 42: second opening 42S: second side wall 50: third insulating layer 52: first photoresist 53, 55: opening 54: second photoresist 60: Connecting element 62: Second conductive layer 64: Third conductive layer 70: Fourth insulating layer AL1: First adhesive layer AL2: Second adhesive layer a20, a22, a42: Angles CL1: First cutting line CL2: Second cutting line CP1: First carrier CP2: Second carrier d: Distance D1: First direction D2: Second direction R: Recess SB: Substrate T1: First thickness T2: Second thickness T3: Third thickness T4: Fourth thickness T5: Fifth thickness

The disclosure may be more fully understood from the following detailed description when read together with the accompanying drawings. It is worth noting that, in accordance with standard practice in the industry, the features are not drawn to scale. In fact, the sizes of the various features may be arbitrarily enlarged or reduced for clarity. Figures 1 to 6 are schematic cross-sectional views of a first electronic device 1 at different manufacturing stages according to some embodiments of the disclosure. Figures 7 to 16 are schematic cross-sectional views of a second electronic device 2 at different manufacturing stages according to some embodiments of the disclosure.

1: first electronic device 10: electronic unit 10B, 40B: bottom surface 10T, 40T: top surface 10S, 20S, 40S: side surface 12: connection pad 20: first insulating layer 30: first conductive layer 40: second insulating layer 42: second opening D1: first direction D2: second direction T1: first thickness T2: second thickness T3: third thickness

Claims (19)

An electronic device includes: an electronic unit including a first surface, a second surface opposite to the first surface, and a first side surface connecting the first surface and the second surface; a first insulating layer disposed on the second surface; a second insulating layer disposed on the first insulating layer and including a third surface, a fourth surface opposite to the third surface, and a second side surface connecting the third surface and the fourth surface; and a connecting element disposed on the second insulating layer and electrically connected to the electronic unit, wherein the third surface of the second insulating layer contacts the second surface of the electronic unit, and the thermal expansion coefficients of the first insulating layer and the second insulating layer are different. An electronic device as described in claim 1, wherein the first insulating layer includes a plurality of first openings, the second insulating layer includes a plurality of second openings, and the angle of one of the plurality of first openings is different from the angle of one of the plurality of second openings. The electronic device as described in claim 2 further includes: a first conductive layer disposed between the first insulating layer and the second insulating layer, and the first conductive layer is electrically connected to the electronic unit through one of the plurality of first openings. An electronic device as described in claim 2, wherein the roughness of the side wall of one of the plurality of first openings is less than the roughness of the side wall of one of the plurality of second openings. An electronic device as described in claim 2, wherein at least one of the plurality of first openings and at least one of the plurality of second openings do not overlap in the normal direction of the electronic unit. An electronic device as described in claim 2, wherein at least one of the plurality of first openings and at least one of the plurality of second openings overlap in the normal direction of the electronic unit. An electronic device as described in claim 1, wherein the second side surface of the second insulating layer is aligned with the first side surface of the electronic unit. An electronic device as described in claim 1, wherein the first insulating layer has a third side surface, the third side surface and the second surface have an angle, and the angle is greater than or equal to 45 degrees and less than 90 degrees. An electronic device as described in claim 8, wherein the second insulating layer contacts the third side surface of the first insulating layer. An electronic device as described in claim 3, wherein the connecting element further comprises: a second conductive layer electrically connected to the first conductive layer. An electronic device as described in claim 10, wherein the thickness of the second conductive layer is greater than the thickness of the first conductive layer. The electronic device as described in claim 10 further comprises: a third insulating layer surrounding the electronic unit, wherein a portion of the second conductive layer contacts a surface of the third insulating layer. An electronic device as described in claim 12, wherein a first thickness of the first insulating layer is less than a second thickness of the second insulating layer, and the second thickness of the second insulating layer is less than a third thickness of the third insulating layer. The electronic device as described in claim 12 further includes: a fourth insulating layer disposed on the connecting element and in contact with the second insulating layer and the third insulating layer. An electronic device as described in claim 1, wherein the first insulating layer and the second insulating layer are reversely warped layers. A method for manufacturing an electronic device, comprising: providing a substrate, wherein the substrate comprises a plurality of electronic units; providing a first insulating layer on the substrate; and providing a second insulating layer on the substrate, wherein the second insulating layer contacts a portion of a surface of the substrate, and the first insulating layer and the second insulating layer have different thermal expansion coefficients. The manufacturing method as described in claim 16 further includes: performing a first cutting process to cut the substrate so that the plurality of electronic units are separated into a plurality of first electronic devices, wherein the side surface of the electronic unit in one of the plurality of first electronic devices is aligned with the side surface of the second insulating layer. The manufacturing method as described in claim 17 further includes: providing the plurality of first electronic devices on a carrier; providing a third insulating layer on the plurality of first electronic devices; providing a connecting element on the second insulating layer and the third insulating layer; providing a fourth insulating layer on the connecting element and the third insulating layer; and performing a second cutting process to separate the plurality of first electronic devices into a plurality of second electronic devices. A manufacturing method as described in claim 16, wherein a surface of the second insulating layer contacts a surface of the plurality of electronic units.

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