TWI826023B - Electronic device - Google Patents

Abstract

An electronic device including an electronic unit and a redistribution layer is disclosed. The electronic unit includes a plurality of connection pads. The redistribution layer is electrically connected to the redistribution layer and includes a first insulating layer, a first metal layer and a second insulating layer. The first insulating layer is disposed on the electronic unit and has a plurality of first openings. The plurality of first openings are disposed corresponding to the plurality of connection pads. The first metal layer is disposed on the first insulating layer and electrically connected to the electronic unit through the plurality of connection pads. The second insulating layer is disposed on the first metal layer. The first insulating layer includes a plurality of first fillers, and the second insulating layer includes a plurality of second fillers. The plurality of first fillers has a first top filler size, the plurality of second fillers has a second top filler size, and the second top filler size is greater than the first top filler size.

Description

electronic device

The present disclosure relates to an electronic device, and in particular to an electronic device including an insulating layer having filled particles.

In recent years, electronic components in electronic devices have gradually tended to be miniaturized and highly dense. For this reason, diversified electronic component packaging technologies have been developed. In the conventional technology, the insulating layer or dielectric layer provided on the electronic components can have a thicker thickness to protect the electronic components, but this will cause the problem of limited space in the device, resulting in the subsequent installation of circuit wiring on the insulating layer. Space is limited.

One of the purposes of the present disclosure is to provide an electronic device to solve the problems encountered by existing electronic devices, improve the fan-out circuit design of the electronic device, thereby improving the input/output design flexibility of the electronic device, and improving the reliability of the electronic device. .

An embodiment of the present disclosure provides an electronic device. The electronic device includes an electronic unit and a redistribution layer. The electronic unit has multiple bonding pads. The redistribution layer is electrically connected to the electronic unit, and the redistribution layer includes a first insulation layer, a first metal layer and a second insulation layer. The first insulating layer is disposed on the electronic unit, and the first insulating layer has a plurality of first openings, and the plurality of first openings are arranged corresponding to the plurality of bonding pads. The first metal layer is disposed on the first insulating layer and electrically connected to the electronic unit through a plurality of bonding pads. The second insulating layer is disposed on the first metal layer. Wherein, the first insulating layer includes a plurality of first filling particles, the second insulating layer includes a plurality of second filling particles, the plurality of first filling particles have a first maximum particle diameter, and the plurality of second filling particles have a second maximum particle size. diameter, and the second maximum particle diameter is larger than the first maximum particle diameter.

The content of the present disclosure is described in detail below with reference to specific embodiments and drawings. It should be noted that, in order to make the readers easy to understand and the drawings to be concise, many of the drawings in the disclosure only depict a part of the device, and the figures Certain components in the formulas are not drawn to actual scale. In addition, the number and size of components in the figures are only for illustration and are not intended to limit the scope of the present disclosure.

Certain words are used throughout this disclosure and patent claims to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may refer to the same component by different names. This article is not intended to differentiate between components that have the same function but have different names. In the following description and patent application, the words "including" and "include" are open-ended words, so they should be interpreted to mean "including but not limited to...". When the terms "comprises," "including," and/or "having" are used in this specification, they specify the presence of the stated features, regions, steps, operations, and/or elements but do not exclude one or more other The presence or addition of features, regions, steps, operations, elements and/or combinations thereof.

When an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or directly connected to the other element or layer. Components or layers, or there may be an intervening component or layer between them. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present.

The directional terms mentioned in this article, such as "up", "down", "front", "back", "left", "right", etc., are only for reference to the directions in the accompanying drawings. Accordingly, the directional terms used are illustrative and not limiting of the disclosure.

The terms "about", "equal to", "equal" or "the same", "substantially" or "substantially" are generally interpreted to mean within 20% of a given value or range, or to mean within a given value or range. Within 10%, 5%, 3%, 2%, 1% or 0.5% of the value or range.

The ordinal numbers used in the specification and the scope of the patent application, such as "first", "second", etc., are used to modify elements. They themselves do not imply and represent that the element (or elements) have any previous ordinal number, nor do they mean that the element (or elements) has any previous ordinal number. It does not represent the order of one element with another element, or the order of the manufacturing method. The use of these numbers is only used to clearly distinguish an element with a certain name from another element with the same name. The same words may not be used in the patent application scope and the description. Accordingly, the first component in the description may be the second component in the patent application scope.

The electronic device described in the present disclosure can be applied to semiconductor packaging components, display devices, light emitting devices, backlight devices, antenna devices, sensing devices or splicing devices, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The manufacturing process of semiconductor packaging components may be a chip-first or a redistribution layer-first (RDL-first) process, but is not limited thereto. The display device may be a non-self-luminous display device or a self-luminous display device. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device, and the sensing device may be a sensing device that senses capacitance, light, heat energy or ultrasonic waves, but is not limited thereto. The electronic device may include, for example, passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. Diodes may include light emitting diodes or photodiodes. The light emitting diode may include, for example, an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro light emitting diode (micro LED) or a quantum dot light emitting diode (quantum LED). dot LED), but not limited to this. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device can be any combination of the above, but is not limited thereto.

It should be noted that, without departing from the spirit of the present disclosure, features in several different embodiments can be replaced, reorganized, and mixed to complete other embodiments.

Please refer to Figure 1 and Figure 2. FIG. 1 is a partial cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure. 2 is a schematic bottom perspective view of an electronic device according to an embodiment of the present disclosure, that is, a perspective schematic bottom view along the direction Y. FIG. 1 is, for example, a partial cross-sectional schematic view along the tangent line A-A' of FIG. 2 . As shown in FIGS. 1 and 2 , an electronic device 100 according to an embodiment of the present disclosure may include an electronic unit 110 and a redistribution layer (RDL). The electronic unit 110 has a plurality of bonding pads 112. The surface of the electronic unit 110 provided with the bonding pads 112 may be called an active surface, for example. The electronic unit 110 may include a die, a chip, a circuit, or a chip. An integrated circuit (IC) or other suitable electronic unit, but is not limited to this. In some embodiments, the electronic unit 110 may further include a carrier board, where the carrier board may include a flexible carrier board or a non-flexible carrier board, such as glass, steel plate, polyimide (PI), polyterephthalate Polyethylene terephthalate (PET) or other suitable materials. In some embodiments, the electronic device 100 may include one or more electronic units 110. FIG. 2 shows that the electronic device 100 includes multiple electronic units 110 as an example, but the disclosure is not limited thereto. For example, in In some embodiments, the electronic device 100 may include only a single electronic unit 110 (for example, the electronic unit 110 on the right side of FIG. 2 is included, but not the electronic unit 110 on the left side of FIG. 2 ). In some embodiments, the electronic device 100 may also include a plurality of alignment marks 102. When setting the electronic unit 110, alignment may be performed based on the alignment marks 102 to confirm the placement position of the electronic unit 110, but is not limited to this.

As shown in FIG. 1 , the redistribution layer RDL can electrically connect the electronic unit 110 . Specifically, the redistribution layer RDL may include a first insulation layer 120, a first metal layer 130, and a second insulation layer 140. The first insulating layer 120 is disposed on the electronic unit 110 and has a plurality of first openings 120H. The plurality of first openings 120H of the first insulating layer 120 and the plurality of bonding pads 112 of the electronic unit 110 Corresponding settings. The first openings 120H can be arranged one-to-one corresponding to the bonding pads 112. For example, each first opening 120H can overlap one of the bonding pads 112 in the direction Y. In the embodiment of the present disclosure, the direction Y can be the normal direction of the electronic device 100, that is, opposite to the top view direction of the electronic device 100, and the direction X can be perpendicular to the direction Y, and the direction X can be parallel to the horizontal direction of the cross-sectional view, but Not limited to this.

The first metal layer 130 is disposed on the first insulating layer 120 and is electrically connected to the electronic unit 110 through a plurality of bonding pads 112 . For example, the redistribution layer RDL may further include a second metal layer 150, and the second metal layer 150 is correspondingly filled in the plurality of first openings 120H. The second metal layer 150 can directly contact the bonding pads 112 corresponding to each first opening 120H to electrically connect the corresponding bonding pads 112 respectively, and the first metal layer 130 can directly contact through the first openings 120H. And electrically connected to the second metal layer 150, that is, the first metal layer 130 can be electrically connected to the bonding pad 112 of the electronic unit 110 through the second metal layer 150 disposed in the first opening 120H, but is not limited to this. . The first metal layer 130 and the second metal layer 150 can be produced in the same process. For example, a metal layer (not shown) is first formed on the first insulating layer 120 and then a patterning process is performed to remove part of the metal layer. , the part of the patterned metal layer located on the first insulating layer 120 is regarded as the first metal layer 130, and the part located in the first opening 120H is regarded as the second metal layer 150, but the first metal layer of the present disclosure The manufacturing method and process of the layer 130 and the second metal layer 150 are not limited to the above.

Furthermore, the second insulating layer 140 is disposed on the first metal layer 130 , wherein the edge of the first metal layer 130 may, for example but not limited to, have an arc angle R to reduce the amount of the second insulating layer disposed on the first metal layer 130 140 rupture. Furthermore, the first insulating layer 120 includes a plurality of first filling particles 122 , and the second insulating layer 140 includes a plurality of second filling particles 142 . The plurality of first filling particles 122 may have a first maximum particle diameter D1, the plurality of second filling particles 142 may have a second maximum particle diameter D2, and the second maximum particle diameter D2 is greater than the first maximum particle diameter D1 (ie, D2> D1).

The measurement method of the top filler sizes such as the first maximum particle size D1 and the second maximum particle size D2 described in the present disclosure can be referred to, for example, FIG. 3 . FIG. 3 is a partial cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure. FIG. 3 may be, for example, a partially enlarged schematic diagram of area I in FIG. 1 . As shown in FIG. 3 , in a cross-sectional view of the electronic device (for example, but not limited to, an image taken by a scanning electron microscope), at the junction of the first insulating layer 120 and the second insulating layer 140 , in the direction Y The first distance H1 between the upper surface 120a of the first insulating layer 120 and the upper surface 110a of the electronic unit 110 is used as a reference. A range R1 of length*width H1*H1 is framed in the first insulating layer 120, and at the The second insulating layer 140 frames a range R2 whose length*width is H1*H1. Furthermore, the first filling particle 122 with the largest particle diameter is selected among the first filling particles 122 in the range R1. The particle diameter of the first filling particle 122 is defined as the first maximum particle diameter D1. The first filling particle 122 in the range R2 is The second filling particle 142 with the largest particle diameter is selected among the particles 122, and the particle diameter of the second filling particle 142 is defined as the second maximum particle diameter D2, but is not limited to this.

The first insulation layer 120 may include first filling particles 122 and organic materials 126 , and the second insulation layer 140 may include second filling particles 142 and organic materials 146 . The first filling particles 122 and the second filling particles 142 may respectively include silicon dioxide (SiO ₂ ), titanium dioxide (TiO ₂ ), aluminum oxide (Al ₂ O ₃ ) or other suitable filling particles (filler). The organic material 126 and the organic material 146 include, for example, epoxy resin (epoxy), Ajinomoto build-up film (ABF) material, polyimide (PI), photosensitive polyimide (photosensitive), respectively. polyimide, PSPI) or other suitable materials, but not limited to this.

The first maximum particle diameter D1 of the first filling particles 122 may range from 1 micron (um) to 5 microns (i.e., 1um≤D1≤5um), and the second maximum particle diameter D2 of the second filling particles 142 may range from 10 microns to 5 μm. 20 microns (i.e. 10um≤D2≤20um). The rigidity (tensile strength) of the first insulating layer 120 may range from 70 MPa to 100 MPa (i.e., 70MPa≤rigidity≤100MPa), and the rigidity of the second insulating layer 140 may be greater than 100 MPa (i.e., rigidity >100MPa). ), that is, the rigidity of the second insulating layer 140 may be different from the rigidity of the first insulating layer 120 , for example, the rigidity of the second insulating layer 140 may be greater than the rigidity of the first insulating layer 120 . The thickness T1 of the first insulating layer 120 in the direction Y (as shown in FIG. 1 ) may range from 10 microns to 5 microns (ie, 1um≤T1≤5um), and the thickness T2 of the second insulating layer 140 in the direction Y (eg, As shown in Figure 1), the range can be from 10 microns to 200 microns (i.e. 10um≤T2≤200um). The dielectric constant (Dk) of the first insulating layer 120 may range from 3.0 to 3.4 (ie, 3.0 ≤ dielectric coefficient ≤ 3.4), and the dielectric constant of the second insulating layer 140 may range from 3.2 to 4.0 (ie, 3.2 ≤ dielectric coefficient ≤ 4.0), wherein the dielectric coefficient of the second insulating layer 140 may be the same as or different from the dielectric coefficient of the first insulating layer 120 .

According to the embodiment of the present disclosure, since the first insulating layer 120 close to the electronic unit 110 (or located in the lower layer) includes the first filling particles 122 with smaller particle sizes, it is beneficial to form smaller-sized particles in the first insulating layer 120 . The first opening 120H allows the circuit formed after the second metal layer 150 is filled in the first opening 120H to have a thinner line width and/or a smaller line spacing, thereby improving the fan-out of the electronic device 100. ) lines, and/or provide more flexibility in the design of fan-out lines, thereby improving the input/output (I/O) design flexibility of the electronic device 100. In addition, since the second insulating layer 140 far away from the electronic unit 110 (or located on the upper layer) includes second filling particles 142 with larger particle sizes, the rigidity of the second insulating layer 140 can be increased, thereby providing a better protection effect. , and improve the reliability of the electronic device 100 .

The rigidity measurement method described in the present disclosure can, for example, conduct a tensile test on a sample of the material to be measured using a universal testing machine. For example, but not limited to, a tensile test can be conducted through the ASTM D638 standard to obtain its proportional limit. (proportional limit), yield point (yield point), ultimate stress (ultimate stress), fracture stress (fracture stress) and other material properties. The value of the ultimate stress obtained is the value of the rigidity described in the present disclosure. In other embodiments, the stiffness value can be obtained according to the material properties of the film layer, but is not limited to this.

As shown in FIG. 1 , according to the electronic device 100 according to the embodiment of the present disclosure, the second insulating layer 140 may also have a plurality of second openings 140H. The plurality of second openings 140H may respectively overlap with a portion of the second openings 140H in the direction Y. A metal layer 130. Moreover, the redistribution layer RDL may also include a third metal layer 160. The third metal layer 160 is correspondingly filled in the plurality of second openings 140H, and the third metal layer 160 provided in the second openings 140H may be in direct contact. The first metal layer 130 is electrically connected to the first metal layer 130 , that is, the third metal layer 160 disposed in the second opening 140H can be electrically connected to the electronic unit through the first metal layer 130 and the second metal layer 150 110 of the bonding pad 112, but is not limited to this. Multiple layers of insulating layers (eg, the first insulating layer 120 and the second insulating layer 140 ) and multiple layers of metal layers (eg, the second metal layer 150 , the first metal layer 130 and the third metal layer 160 ) stacked in the direction Y may constitute a heavy metal layer. The wiring layer RDL is used to redistribute circuits, but the number of layers of insulation layers and metal layers and circuit layout in the redistribution layer RDL are not limited to the drawings provided in this disclosure. For example, the first insulating layer 120 may be the insulating layer located at the lowermost layer and closest to the electronic unit 110, and the second insulating layer 140 may be the insulating layer located at the uppermost layer and farthest from the electronic unit 110, and, in In some embodiments, at least one insulating layer and/or at least one metal layer may be disposed between the first insulating layer 120 and the second insulating layer 140, but is not limited thereto. The second metal layer 150 , the first metal layer 130 and/or the third metal layer 160 may include a seed layer and an electroplated metal layer. For example, but not limited to, the first metal layer 130 shown in FIG. 8 includes a seed layer 132 and electroplated metal layer 134. The seed layer and the electroplated metal layer may include a single layer of material or multiple layers of materials. The materials include, for example, titanium, copper, molybdenum, aluminum, nickel, silver, tin, other suitable conductive materials, or combinations of the above materials, but are not limited thereto. , where the seed layer can help form the electroplated metal layer or improve adhesion.

In some embodiments, as shown in FIG. 1 , the electronic device 100 may further include a protective layer 170 , and the protective layer 170 may surround the electronic unit 110 to isolate moisture, air and/or reduce damage to the electronic unit 110 , where “ "Around" may mean that the protective layer 170 contacts at least one surface of the electronic unit 110 in the cross-sectional view. For example, the electronic unit 110 may include an upper surface 110a, a lower surface 110b opposite to the upper surface 110a, and a side surface 110c connected to the upper surface 110a and the lower surface 110b. The protective layer 170 may cover the side surface 110c of the electronic unit 110. However, the lower surface 110b is not covered, or the protective layer 170 can cover both the side surface 110c and the lower surface 110b of the electronic unit 110 (as shown in FIG. 1 ). The protective layer 170 may include an encapsulating material 174, where the encapsulating material 174 includes, for example, epoxy resin, epoxy molding compound (EMC), poly(methyl methacrylate) (PMMA), polyethylene glycol Methylsiloxane (polydimethylsiloxane, PDMS), ceramics, other suitable encapsulation materials, or combinations of the above materials, but are not limited to this. In some embodiments, the hardness of the protective layer 170 may be different from the hardness of the first insulating layer 120 and the second insulating layer 140 .

The first insulating layer 120 may include an upper surface 120a, a lower surface 120b opposite to the upper surface 120a, and a side surface 120c connected to the upper surface 120a and the lower surface 120b, and the second insulating layer 140 may include an upper surface 140a and an upper surface 120b. The surface 140a is opposite to the lower surface 140b, where the protective layer 170 may contact a portion of the side surface 120c of the first insulating layer 120 and a portion of the lower surface 140b of the second insulating layer 140. In some embodiments, the side surface 120c of the first insulating layer 120 may be flush with the side surface 110c of the electronic unit 110, but is not limited thereto.

In some embodiments, as shown in FIGS. 1 and 3 , the upper surface 170a of the protective layer 170 contacts a portion of the lower surface 140b of the second insulating layer 140 , and the upper surface 120a of the first insulating layer 120 is in contact with a portion of the protective layer 170 . There may be a step S between the upper surfaces 170a. Specifically, in the normal direction Y of the electronic device 100, there is a first distance H1 between the upper surface 120a of the first insulating layer 120 and the upper surface 110a of the electronic unit 110 (for example, substantially equal to thickness T1), and there is a second distance H2 between the upper surface 170a of the protective layer 170 and the plane PL where the upper surface 110a of the electronic unit 110 is located, wherein the first distance H1 may be greater than the second distance H2, for example, anchoring, Fixed effect, thereby improving the adhesion between film layers.

In some embodiments, the protective layer 170 may include a plurality of third filling particles 172, the plurality of third filling particles 172 having a third maximum particle diameter D3, wherein the third maximum particle diameter D3 may be greater than the second maximum particle diameter D2, And the second maximum particle diameter D2 may be larger than the first maximum particle diameter D1 (ie, D3>D2>D1). In some embodiments, the third maximum particle diameter D3 may be greater than or equal to 6 times the first maximum particle diameter D1 and less than or equal to 9 times the first maximum particle diameter D1 (ie, D1*6≤D3≤D1*9) , but not limited to this. In some embodiments, the third maximum particle diameter D3 may be greater than or equal to 3 times the second maximum particle diameter D2 and less than or equal to 6 times the second maximum particle diameter D2 (ie, D2*3≤D3≤D2*6) , but not limited to this. Through the design of different particle sizes, the protection effect can be improved and the circuit fan-out capability can be achieved.

The measurement method of the third maximum particle diameter D3 described in the present disclosure may, for example, refer to FIG. 3 and the aforementioned measurement methods of the first maximum particle diameter D1 and the second maximum particle diameter D2. As shown in FIG. 3 , in the cross-sectional view of the electronic device 100 , at the junction of the first insulating layer 120 , the second insulating layer 140 and the protective layer 170 , with the first distance H1 as a reference, a frame can be drawn in the protective layer 170 . Extract the range R3 whose length*width is H1*H1. Furthermore, the third filling particle 172 with the largest particle diameter is selected from the third filling particles 172 in the range R3, and the particle diameter of the third filling particle 172 is defined as the third maximum particle diameter D3, but is not limited to this.

Please refer to Figure 4 in conjunction with Figure 1. FIG. 4 is a schematic diagram of a partial cross-section of an electronic device according to an embodiment of the present disclosure. FIG. 4 shows, for example, the detailed structure of the first opening 120H in FIG. 1 . As shown in FIG. 4 , since the first insulating layer 120 includes the first filling particles 122 , the sidewall of one of the first openings 120H of the plurality of first openings 120H formed in the first insulating layer 120 through the patterning process. The roughness of 124 may be greater than the roughness of the upper surface 120a of the first insulating layer 120, that is, the sidewall 124 of the first opening 120H may, for example, present an uneven rough surface along the surface profile of the first filling particles 122, so that The adhesion between the second metal layer 150 and the first insulating layer 120 disposed in the first opening 120H is improved. In other embodiments, since the second insulating layer 140 includes the second filling particles 142, among the plurality of second openings 140H (not shown in FIG. 4) formed in the second insulating layer 140 through the patterning process The roughness of the sidewall of a second opening 140H may be greater than the roughness of the upper surface 140a of the second insulating layer 140 , that is, the sidewall of the second opening 140H may appear uneven along the surface contour of the second filling particle 142 . The rough surface can improve the adhesion between the third metal layer 160 and the second insulating layer 140 provided in the second opening 140H, but is not limited to this. The roughness can be measured, for example, using a surface roughness meter or a scanning electron microscope, but is not limited thereto.

As shown in FIG. 1 , according to the electronic device 100 according to the embodiment of the present disclosure, the second insulating layer 140 may expose the uppermost third metal layer 160 in the redistribution layer RDL, and the electronic device 100 may further include a plurality of bonding connections. Component 180 and the joining component 180 may be disposed on the exposed third metal layer 160 and electrically connected to the third metal layer 160 respectively, so that the third metal layer 160 may serve as an upper metal pad connected to the joining component 180 bonding pad). The bonding element 180 may be, for example, a bump, a solder ball, a pad, or other suitable bonding element. The bonding element 180 may include copper, aluminum, gold, silver, nickel, tin, lead, Other suitable conductive materials or combinations of the above materials, but are not limited to this. In some embodiments, as shown in FIG. 1 , the upper surface 140a of the second insulating layer 140 may be flush with the upper surface 160a of the third metal layer 160, but is not limited thereto. In other embodiments, as shown in FIG. 5 , which is a partial cross-sectional view of an electronic device according to another embodiment of the present disclosure, between the upper surface 140a of the second insulating layer 140 and the upper surface 160a of the third metal layer 160 Can have step differences. Specifically, in the normal direction Y of the electronic device 100, there is a third distance H3 between the upper surface 140a of the second insulating layer 140 and the upper surface 130a of the first metal layer 130, and the upper surface of the third metal layer 160 is There is a fourth distance H4 between the surface 160a and the upper surface 130a of the first metal layer 130, where the third distance H3 may be greater than the fourth distance H4. This design may be beneficial to the positioning and stability of the joint component 180, but it is not used in this way. To be limited, in other embodiments, the third distance H3 may be smaller than the fourth distance H4.

Please refer to Figure 6 in conjunction with Figure 2. FIG. 6 is another partial cross-sectional schematic view of an electronic device according to an embodiment of the present disclosure. FIG. 6 is, for example, a partial cross-sectional schematic view along the tangent line B-B' of FIG. 2 . In some embodiments, as shown in FIG. 6 , one of the first openings 120H of the plurality of first openings 120H may have a first upper width W1 , and one of the second openings 140H of the plurality of second openings 140H There may be a second upper width W2, and the first upper width W1 may be smaller than the second upper width W2. Since the first opening 120H has a smaller first upper width W1, the second metal layer 150 corresponding to the first opening 120H can have a smaller upper width. This design can reduce input/output design or Layout effects. Moreover, since the second opening 140H has a larger second upper width W2, the third metal layer 160 corresponding to the second opening 140H can have a larger upper width. This design can increase the line fan-out area. And it is beneficial to connect with the joint element (such as the joint element 180 shown in Figure 1). Through the above design, the signal transmission of the electronic device 100 can be improved. For example, in the cross-sectional view, the side wall 124 of the first opening 120H and the side wall 144 of the second opening 140H may be inclined walls respectively, that is, the width of the first opening 120H and the width of the second opening 140H may be respectively Gradually decrease from top to bottom. The maximum width of the first opening 120H measured in the direction X may be the first upper width W1, and the maximum width of the second opening 140H measured in the direction X may be the second upper width W2, but Not limited to this.

As shown in FIG. 6 , in some embodiments, the first maximum particle diameter D1 of the first filling particles 122 of the first insulating layer 120 may be smaller than the thickness T3 of the second metal layer 150 in the direction Y, where the second metal layer The thickness T3 of the first insulating layer 150 is, for example, substantially equal to the thickness T1 of the first insulating layer 120 . In other embodiments, the second maximum particle diameter D2 of the second filling particles 142 of the second insulating layer 140 may be smaller than the thickness T4 of the first metal layer 130 in the direction Y, where the thickness T4 of the first metal layer 130 is, for example, It is one third of the thickness T2 of the second insulating layer 140, but is not limited thereto. In still other embodiments, the second maximum particle diameter D2 of the second filling particles 142 of the second insulating layer 140 may be smaller than the thickness T5 of the third metal layer 160 in the direction Y, where the thickness T5 of the third metal layer 160 is, for example, It is two-thirds of the thickness T2 of the second insulating layer 140, but is not limited to this.

Please refer to Figure 7 in conjunction with Figure 2. FIG. 7 is another partial cross-sectional schematic view of an electronic device according to an embodiment of the present disclosure. FIG. 7 is, for example, a partial cross-sectional schematic view along the tangent line C-C’ of FIG. 2 . As shown in FIG. 7 , the disclosed electronic device 100 may further include a plurality of via structures 190 , the first metal layer 130 is disposed on the protective layer 170 , and the via structures 190 may be disposed on one side of the first metal layer 130 ( such as the lower side) and extends through the protective layer 170 in a direction opposite to the direction Y. Each through-hole structure 190 can be electrically connected or electrically isolated from the first metal layer 130 respectively, and the plurality of through-hole structures 190 can also achieve the function of heat dissipation, but is not limited to this. In some embodiments, warpage can be slowed down through the arrangement of the through hole structure 190, but it is not limited to this. The via structure 190 may be a single layer or a multi-layer material stack, and may include, for example, copper, tin, nickel, gold, titanium, other suitable conductive materials, other suitable heat dissipation materials, or combinations of the above materials, but is not limited thereto. In some embodiments, the electronic unit 110 can be located between two adjacent through-hole structures 190 of the plurality of through-hole structures 190 , and these through-hole structures 190 can limit the position of the electronic unit 110 . Reduce electronic unit 110 positional deviation.

Please refer to Figure 8 in conjunction with Figure 7. FIG. 8 is a partial cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure. FIG. 8 shows, for example, a modified embodiment of the first metal layer 130 and the through-hole structure 190 of FIG. 7 . In some embodiments, as shown in FIG. 8 , the first metal layer 130 may include a seed layer 132 and an electroplated metal layer 134 , the seed layer 132 may be disposed on the protective layer 170 , and the electroplated metal layer 134 may be disposed on the seed layer 132 superior. in. The seed layer 132 may include a multi-layer material or a single layer of material as shown in FIG. 8 . The materials of the seed layer 132 and the electroplated metal layer 134 may refer to the description of the previous embodiments and will not be described again here. Furthermore, one of the through-hole structures 190 may include an upper surface 190a and a lower surface 190b opposite to the upper surface 190a, and the upper surface 190a of the through-hole structure 190 may contact the first metal layer 130. The lower surface 190b of the through-hole structure 190 can be a concave surface or a rough surface, which can facilitate connection with joint components (not shown), and the through-hole structure 190 can also be electrically connected to other electronic components through the connected joint components. But it is not limited to this. In addition, the rough surface 190b of the through-hole structure 190 can also improve the heat dissipation effect.

To sum up, according to the electronic device according to the embodiment of the present disclosure, by making the maximum particle size of the filling particles of the second insulating layer larger than the maximum particle size of the filling particles of the first insulating layer, the fan-out circuit of the electronic device can be improved, thereby improving the fan-out circuit of the electronic device. Improve the input/output design flexibility of electronic devices and improve the reliability of electronic devices. In addition, through the design of the present disclosure in which the first distance is greater than the second distance, the adhesion between the film layers can be improved.

The above descriptions are only embodiments of the disclosure and are not intended to limit the disclosure. For those skilled in the art, the disclosure may have various modifications and changes. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this disclosure shall be included in the protection scope of this disclosure.

100: Electronic devices 102: Counterpoint marks 110: Electronic unit 110a,120a,140a,170a,160a,130a,190a: upper surface 110b,120b,140b,190b: lower surface 110c,120c: side surface 112:Joining pad 120: First insulation layer 120H: First opening 122: First filling particle 124,144:Side wall 126,146:Organic materials 130: First metal layer 132:Seed layer 134: Electroplated metal layer 140: Second insulation layer 140H: Second opening 142: Second filling particle 150: Second metal layer 160:Third metal layer 170:Protective layer 172: The third filling particle 174:Packaging materials 180:joint element 190:Through hole structure D1: first maximum particle size D2: The second largest particle size D3: The third largest particle size H1: first distance H2: second distance H3: The third distance H4: The fourth distance I:Area R: arc angle R1, R2, R3: range RDL: redistribution layer S: Segment difference T1, T2, T3, T4, T5: Thickness W1: first upper width W2: Second upper width X,Y: direction

FIG. 1 is a partial cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure. FIG. 2 is a bottom perspective view of an electronic device according to an embodiment of the present disclosure. FIG. 3 is a schematic diagram of a partial cross-section of an electronic device according to an embodiment of the present disclosure. FIG. 4 is a schematic diagram of a partial cross-section of an electronic device according to an embodiment of the present disclosure. FIG. 5 is a partial cross-sectional view of an electronic device according to another embodiment of the present disclosure. FIG. 6 is another partial cross-sectional view of an electronic device according to an embodiment of the present disclosure. FIG. 7 is another partial cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure. FIG. 8 is a partial cross-sectional view of an electronic device according to an embodiment of the present disclosure.

100: Electronic devices

110: Electronic unit

110a,120a,140a,170a,160a: upper surface

110b,120b,140b: lower surface

110c,120c: side surface

112:Joining pad

120: First insulation layer

120H: First opening

122: First filling particle

126,146:Organic materials

130: First metal layer

140: Second insulation layer

140H: Second opening

142: Second filling particle

150: Second metal layer

160:Third metal layer

170:Protective layer

172: The third filling particle

174:Packaging materials

180:joint element

I:Area

R: arc angle

RDL: redistribution layer

T1, T2: thickness

X,Y: direction

Claims (10)

An electronic device including: an electronic unit having a plurality of bonding pads; and A rewiring layer is electrically connected to the electronic unit. The rewiring layer includes: A first insulating layer is provided on the electronic unit, the first insulating layer has a plurality of first openings, and the plurality of first openings are arranged corresponding to the plurality of bonding pads; a first metal layer disposed on the first insulating layer and electrically connected to the electronic unit through the plurality of bonding pads; and a second insulating layer disposed on the first metal layer; Wherein, the first insulating layer includes a plurality of first filling particles, the second insulating layer includes a plurality of second filling particles, the plurality of first filling particles have a first maximum particle diameter, and the plurality of second filling particles It has a second maximum particle diameter, and the second maximum particle diameter is larger than the first maximum particle diameter. The electronic device according to claim 1, further comprising a protective layer surrounding the electronic unit, wherein the protective layer contacts a portion of the side surface of the first insulating layer and a portion of the lower surface of the second insulating layer. The electronic device of claim 2, wherein there is a first distance between an upper surface of the first insulating layer and an upper surface of the electronic unit in a normal direction of the electronic device, and the protection There is a second distance between an upper surface of the layer and a plane where the upper surface of the electronic unit is located, wherein the first distance is greater than the second distance. The electronic device of claim 2, wherein the protective layer includes a plurality of third filling particles, the plurality of third filling particles have a third maximum particle diameter, wherein the third maximum particle diameter is larger than the second maximum particle size. diameter. The electronic device of claim 4, wherein the third maximum particle diameter is greater than or equal to 6 times the first maximum particle diameter and less than or equal to 9 times the first maximum particle diameter. The electronic device of claim 4, wherein the third maximum particle diameter is greater than or equal to 3 times the second maximum particle diameter and less than or equal to 6 times the second maximum particle diameter. The electronic device according to claim 2, further comprising a plurality of through-hole structures disposed on one side of the first metal layer and extending through the protective layer. The electronic device according to claim 7, wherein the electronic unit is located between two adjacent through-hole structures of the plurality of through-hole structures. The electronic device as claimed in claim 7, wherein a lower surface of one of the plurality of through-hole structures is a concave surface. The electronic device of claim 1, wherein the second maximum particle diameter is smaller than a thickness of the first metal layer in a normal direction of the electronic device.

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