TW202347778A - Semiconductor device and power conversion device using same - Google Patents

Abstract

Provided is a semiconductor device capable of preventing a flow of carriers due to an avalanche into a region where a switching element body is present, while controlling the location where the avalanche occurs, through the formation of an electric-field concentration layer 7. The electric-field concentration layer 7 makes an avalanche occur in a region where a second body layer 5b is present. A floating layer 8 is provided between a first body layer 5a where the switching element body is present and the second body layer 5b where the avalanche occurs, whereby the first body layer 5a and the second body layer 5b are separated from each other, and it is possible to prevent a flow of carriers due to the avalanche into the first body layer 5a, where the switching element body is present.

Description

Semiconductor devices and power conversion devices using the same

The present invention relates to a semiconductor device and a power conversion device using the same.

As the power density of power modules increases, switching elements such as IGBT (Insulated Gate Bipolar Transistor) or MOSFET (Metal Oxide Semiconductor Field Effect Transistor) are required to It operates at a higher current density and has a larger RBSOA (Reverse Bias Safe Operating Area) endurance than before.

For example, it is described in Figure 1 and paragraph 0029 of Patent Document 1 that "by forming the n electric field concentration layer 115 in the second region with a higher carrier concentration than the n barrier layer 114, current concentration is generated in the second region where no parasitic thyristor exists. , and the current flowing through the first area where the parasitic thyristor exists is reduced," and "Because the second area and the first area are separated by the trench, it is possible to suppress latch-up in the first area due to current concentration in the second area." , it is described in paragraph 0024 of Patent Document 1 that "it is possible to provide an IGBT with a large RBSOA by dispersing the current during shutdown to reduce heat generation due to latch-up." [Prior technical literature] [Patent Document]

[Patent Document 1] Japanese Patent Application Laid-Open No. 2016-184712

[Problem to be solved by the invention]

However, in Patent Document 1, although the first region and the second region are separated by a trench, they are still adjacent to each other. Therefore, part of the avalanche current generated in the n electric field concentration layer 115 flows to the first area where the parasitic thyristor exists (the area where the switching element body exists). The parasitic thyristor may latch up, and the latch-up prevention may not be complete enough. problem.

In addition, in the case of MOSFET instead of IGBT, since the p collector layer on the back side is an n+ layer, there is no parasitic thyristor of pnpn in the area where the switching element body exists, but there is npn in the area where the switching element body exists. Because of the parasitic transistor, when an avalanche current occurs, there is a problem that the npn parasitic transistor is turned on.

The problem to be solved by the present invention is to provide a semiconductor device that can control the place where an avalanche occurs by forming an electric field concentration layer, and suppress the flow of carriers caused by the avalanche to the area where the switching element body exists, and a power conversion device using the same. . [Technical means to solve problems]

In order to solve the above problems, a first semiconductor device of the present invention includes, for example: a first conductivity type drift layer; a second conductivity type first body layer formed on the front surface of the drift layer; and a first conductivity type front side electrode. A layer formed on the front surface of the first body layer; a front main electrode connected to the first body layer and the front electrode layer; a first trench connected to the first body layer and the front electrode layer The gate electrode is formed inside the first trench; and the gate insulating film is formed inside the first trench, and between the first body layer and the gate electrode and between the front-side electrode layer and the gate electrode; and the above-mentioned semiconductor device is characterized by having: a second conductive type second body layer, which is formed on the front surface of the above-mentioned drift layer, and the above-mentioned front-side electrode is not formed layer is connected to the above-mentioned front-side main electrode; a second trench is formed in contact with the above-mentioned second body layer; a dummy electrode is formed inside the above-mentioned second trench and has the same potential as the above-mentioned front-side main electrode; An insulating film formed inside the second trench and between the second body layer and the dummy electrode; an electric field concentration layer of the first conductivity type formed at the bottom of the second body layer with a high impurity concentration in the above-mentioned drift layer; and a floating layer of the second conductivity type, which is formed between the above-mentioned first trench and the above-mentioned second trench and is electrically floating.

Furthermore, in order to solve the above problems, the second semiconductor device of the present invention includes, for example, a drift layer of a first conductivity type; a first body layer of a second conductivity type formed on the front surface of the drift layer; and a front surface side of the first conductivity type. An electrode layer formed on the front surface of the first body layer; a front main electrode connected to the first body layer and the front electrode layer; a trench connected to the first body layer and the front electrode layer Formed in contact with each other; a gate electrode formed on the sidewall of the first body layer inside the trench; and a gate insulating film formed inside the trench, and the first body layer and the above between the gate electrodes, and between the front-side electrode layer and the gate electrode; and the above-mentioned semiconductor device is characterized by having: a second conductive type second body layer, which is in contact with the above-mentioned trench, and is in the above-mentioned third 1. The opposite side of the main body layer is formed on the front side of the above-mentioned drift layer. The above-mentioned front-side electrode layer is not formed and is connected to the above-mentioned front-side main electrode; a dummy electrode is formed on the side of the above-mentioned second body layer inside the above-mentioned trench. The side wall has the same potential as the front-side main electrode; a first insulating film is formed inside the trench and between the second body layer and the dummy electrode; and an electric field concentration layer of the first conductivity type is formed inside the trench. The bottom of the second body layer has a higher impurity concentration than the drift layer; a field plate is formed inside the trench and has the same potential as the front-side main electrode; a second insulating film is formed inside the trench , and between the field plate and the drift layer; a third insulating film formed inside the trench, between the field plate and the gate electrode, and between the field plate and the dummy electrode.

Furthermore, the power conversion device of the present invention is characterized by using, for example, the first semiconductor device or the second semiconductor device of the present invention as a switching element. [Effects of the invention]

According to the present invention, the electric field concentration layer is used to generate an avalanche in a certain area of the second body layer, and a floating layer is provided between the first body layer where the switching element body exists and the second body layer where the avalanche is generated, or is formed internally. There are wide grooves in the field plate, whereby the first body layer and the second body layer are separated from each other, which can inhibit the flow of carriers caused by avalanches to the first body layer where the switching element body exists.

Hereinafter, embodiments of the present invention will be described using drawings. In each figure and each embodiment, the same or similar components are denoted by the same symbols, and repeated descriptions are omitted. [Example 1]

FIG. 1 is a cross-sectional view illustrating the semiconductor device of Embodiment 1.

Figure 1 is an example applied to trench IGBT. In addition, it is not limited to IGBT, but can also be applied to MOSFET as mentioned later.

The semiconductor device of Embodiment 1 has, for example, in the unit cell 9: a drift layer 10 of a first conductivity type (n-type in Figure 1); a first body of a second conductivity type (p-type in Figure 1) Layer 5a, which is formed on the front surface of the drift layer 10; emitter layer 6 (front-side electrode layer) of the first conductivity type, which is formed on the front surface of the first body layer 5a; emitter electrode 2 (front-side main electrode), It is connected to the first body layer 5a and the emitter layer 6; the first trench 20a is formed in contact with the first body layer 5a and the emitter layer 6; the gate electrode 3 is formed in the first trench 20a and a gate insulating film 21a formed inside the first trench 20a, between the first body layer 5a and the gate electrode 3, and between the emitter layer 6 and the gate electrode 3.

Furthermore, the semiconductor device of Example 1 includes, for example, a first conductivity type buffer layer 11 formed on the back surface of the drift layer 10 (opposite to the first body layer 5a); and a second conductivity type collector layer 12 (the back surface). Side electrode layer), which is formed on the back surface of the buffer layer 11; and collector electrode 1 (back side main electrode), which is formed on the back surface of the collector layer 12.

And, by these, the switching element body is constituted.

Here, the impurity concentration of the drift layer 10 is a low concentration (n-), and the impurity concentration of the emitter layer 6 is a high concentration (n+). Regarding the conductivity types, FIG. 1 takes as an example the case where the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be p-type. The conductivity type is set to n type. In this case, the carriers are electrons rather than holes.

In FIG. 1 , IGBT is used as an example for explanation. However, in the case of MOSFET, it is only necessary to replace the front-side electrode layer, that is, the emitter layer 6 with the source layer, and to replace the front-side main electrode, that is, the emitter electrode 2 with the source layer. It is sufficient to replace the collector electrode 1, which is the main electrode on the back side, with the drain electrode. In the case of a MOSFET, the collector layer 12 of the second conductivity type, which is the back side electrode layer, is replaced with a drain layer of the first conductivity type. The impurity concentration of the drain layer is high (n+).

In addition, the semiconductor device of Example 1 has, for example, a second body layer 5 b of the second conductivity type in the unit cell 9 , which is formed on the front surface of the drift layer 10 , and is connected to the emitter electrode 2 without forming the emitter layer 6 . ; The second trench 20b is formed in contact with the second body layer 5b; the dummy electrode 4 is formed inside the second trench 20b and has the same potential as the emitter electrode 2; the insulating film 21b is formed on Inside the second trench 20b and between the second body layer 5b and the dummy electrode 4; and the first conductive type electric field concentration layer 7, which is formed at the bottom of the second body layer 5b and has an impurity concentration higher than that of the drift layer 10 .

Since the electric field concentration layer 7 is formed at the bottom of the second body layer 5b, the avalanche voltage at this location is lower than that at other locations. When the IGBT is turned off and an avalanche occurs, an avalanche occurs at this location. A large number of carriers generated by the avalanche, namely holes, flow through the second body layer 5b and leak to the emitter electrode 2. Since the emitter layer 6 of the first conductivity type is not formed in the second body layer 5b, there is no pnpn parasitic thyristor in the second body layer 5b, and latch-up of the parasitic thyristor does not occur.

Here, assuming that the first body layer 5a of the switching element body having the emitter layer 6 of the first conductivity type is located nearby, carriers caused by the avalanche also flow to the first body layer 5a, and parasitism may occur. Thyroid fluid latch.

Therefore, the semiconductor device of Embodiment 1 is configured to have, for example, a floating layer 8 of the second conductivity type in the unit cell 9, which is formed between the first trench 20a and the second trench 20b and is electrically floating. . In order to electrically float, the floating layer 8 is insulated from the emitter electrode 2 by the insulating film 22 .

The floating layer 8 separates the first body layer 5a and the second body layer 5b from each other, thereby suppressing carriers caused by avalanche from flowing to the first body layer 5a where the switching element body is present. Thereby, the latch-up of the parasitic thyristor can also be suppressed. In addition, it is possible to suppress a decrease in RBSOA endurance due to latch-up due to parasitic thyristor fluid. In addition, in the case of MOSFET, since an npn parasitic transistor exists in place of the parasitic thyristor, it is possible to suppress the parasitic transistor from turning on.

In addition, since the floating layer 8 is electrically floating and is not connected to the emitter electrode 2, when the IGBT is turned on, holes will not leak to the emitter electrode 2 through the floating layer 8. Assume that when the IGBT is turned on, if holes leak from a certain area of the floating layer 8 to the emitter electrode 2, the hole density will decrease, the IE (Injection Enhancement) effect will weaken, and the conductivity modulation will not be sufficient. Therefore, There is a problem that the turn-on voltage becomes high. However, since the floating layer 8 is electrically floating and is not connected to the emitter electrode 2, this problem does not occur.

As described above, according to Embodiment 1, an avalanche is generated in a certain area of the second body layer 5b by the electric field concentration layer 7, and between the first body layer 5a where the switching element body exists and the second body layer 5b where the avalanche is generated By having the floating layer 8, the first body layer 5a and the second body layer 5b are separated from each other, carriers caused by avalanches can be suppressed from flowing to the first body layer 5a where the switching element body exists. [Example 2]

Embodiment 2 is a variation of Embodiment 1. The description will focus on the differences from Embodiment 1, and repeated description will be omitted.

FIG. 2 is a cross-sectional view illustrating the semiconductor device of Embodiment 2.

Figure 2 is an example of an IGBT applied to a so-called side gate structure. In addition, like Embodiment 1, it is not limited to IGBT but can also be applied to MOSFET. Alternatively, the conductivity type may be reversed.

The semiconductor device of Embodiment 2 has, for example, in the unit cell 9: a drift layer 10 of the first conductivity type; a first body layer 5a of the second conductivity type, which is formed on the front surface of the drift layer 10; an emitter of the first conductivity type. The electrode layer 6 (front-side electrode layer) is formed on the front surface of the first body layer 5a; the emitter electrode 2 (front-side main electrode) is connected to the first body layer 5a and the emitter layer 6; the trench 20c, It is formed in contact with the first body layer 5a and the emitter layer 6; the gate electrode 13 is formed on the side wall of the first body layer 5a side inside the trench 20c; and the gate insulating film 23a is formed on Inside the trench 20c, between the first body layer 5a and the gate electrode 13, and between the emitter layer 6 and the gate electrode 13. Since the structure of the back side is the same as that of Embodiment 1, description is omitted. By these, the switching element body of the so-called side gate structure is formed.

In addition, the semiconductor device of Example 2 has, for example, a second body layer 5b of the second conductivity type in the unit cell 9, which is in contact with the trench 20c and is formed in the drift layer on the opposite side of the first body layer 5a. The front side of 10 is not formed with the emitter layer 6 but is connected to the emitter electrode 2; the dummy electrode 14 is formed on the side wall of the second body layer 5b inside the trench 20c and has the same potential as the emitter electrode 2; The insulating film 23b is formed inside the trench 20c and between the second body layer 5b and the dummy electrode 14; and the first conductive type electric field concentration layer 7 is formed at the bottom of the second body layer 5b. The impurity concentration above drift layer 10. Since the effect of the electric field concentration layer 7 is the same as that of Embodiment 1, description thereof is omitted.

Furthermore, the semiconductor device of Embodiment 2 has, for example, in the unit cell 9: a field plate 15 formed inside the trench 20c and having the same potential as the emitter electrode 2; and a second insulating film 23c formed inside the trench. 20c, and between the field plate 15 and the drift layer 10; and the third insulating film 24a, which is formed inside the trench 20c, between the field plate 15 and the gate electrode 13, and between the field plate 15 and the dummy electrode. between 14. In addition, the third insulating film 24a represents a portion of the insulating film 24 formed in the trench 20c.

In Embodiment 2, instead of the floating layer 8 of Embodiment 1, a wide trench 20c in which the field plate 15 is formed is provided. Thereby, similarly to Embodiment 1, the first body layer 5a and the second body layer 5b are separated from each other, and carriers caused by avalanches can be suppressed from flowing to the first body layer 5a where the switching element body is present.

In addition, the reason why the field plate 15 is set to the same potential as the emitter electrode 2 is that if this is not the case, the electric field will be concentrated under the dummy electrode 14 , causing damage to the first insulating film 23 b and carriers flowing to the dummy electrode 14 .

In addition, since the field plate 15 is surrounded by the second insulating film 23c and the third insulating film 24a, when the IGBT is turned on, holes do not leak to the emitter electrode 2 via the field plate 15. Therefore, similarly to Embodiment 1, the problem of high turn-on voltage is avoided.

Since the other effects are the same as those of Embodiment 1 or the effects of the side gate structure, description is omitted. [Example 3]

Embodiment 3 is a variation of Embodiment 1. The description will focus on differences from the embodiment, and repeated description will be omitted. In addition, Embodiment 3 can also be applied to Embodiment 2.

3 is a cross-sectional view illustrating the semiconductor device of Embodiment 3.

In Embodiment 3, the difference from Embodiment 1 is that the width Wb of the second body layer 5b is greater than the width Wa of the first body layer 5a. Otherwise it is the same as Example 1.

By widening the width Wb, the area of the pn junction between the second body layer 5b and the drift layer 10 or between the second body layer 5b and the electric field concentration layer 7 can be increased. Therefore, compared with the case of the width Wa , the avalanche voltage can be further reduced, and an avalanche can be reliably generated at a certain location in the second main body layer 5b. However, if the width Wb is too wide, the avalanche voltage will drop excessively and the overall withstand voltage will be lowered. Therefore, it is better to set it in consideration of the balance with the overall withstand voltage.

Since other effects are the same as those of Embodiment 1, description is omitted. [Example 4]

Embodiment 4 is a variation of Embodiment 1. The description will focus on differences from the embodiment, and repeated description will be omitted. In addition, Embodiment 4 can also be applied to Embodiment 2 or Embodiment 3.

4 is a cross-sectional view illustrating the semiconductor device of Embodiment 4.

In Embodiment 4, the difference from Embodiment 1 is that there is also an electric field concentration layer 7 at the bottom of the first body layer 5a, and the avalanche voltage in the second body layer 5b is smaller than the avalanche voltage in the first body layer 5a. . Otherwise it is the same as Example 1.

According to Embodiment 4, during the RBSOA operation period when the IGBT is turned off, a negative voltage is applied between the gate and the emitter, so the electric field is dispersed in the pn junction composed of the first body layer 5a and the electric field concentration layer 7. and the bottom of the first trench 20a. Thereby, the avalanche voltage of the first body layer 5a becomes high. Therefore, the avalanche voltage in the second main body layer 5b is smaller than the avalanche voltage in the first main body layer 5a, and an avalanche can be generated on the side with the second main body layer 5b. In addition, the same applies to Example 2. Since the electric field is dispersed in the pn junction composed of the first body layer 5a and the electric field concentration layer 7 and at the bottom of the trench 20c, the avalanche voltage of the first body layer 5a becomes High, so an avalanche can be generated on the side with the second main body layer 5b.

Furthermore, in Embodiment 4, the electric field concentration layer 7 formed at the bottom of the first body layer 5a can block the leakage path of the holes in the first body layer 5a, so when the IGBT is turned on, IE can be prevented. (Injection Enhancement) effect is weakened, which prevents the turn-on voltage from becoming high.

Since other effects are the same as those of Embodiment 1, description is omitted. [Example 5]

Embodiment 5 is a variation of Embodiment 4. The description will focus on differences from Embodiment 4, and repeated description will be omitted. In addition, Example 5 can also be applied to any one of Examples 1 to 3.

FIG. 5 is a cross-sectional view illustrating the semiconductor device of Embodiment 5.

In Embodiment 5, the difference from Embodiment 4 is that the impurity concentration (n+) of the electric field concentration layer 7 formed at the bottom of the second body layer 5b is higher than that of the electric field concentration layer 7 formed at the bottom of the first body layer 5a. 7 has high impurity concentration (n). Otherwise, it is the same as Example 4.

According to Embodiment 5, since the avalanche voltage of the pn junction composed of the second body layer 5b and the high-concentration electric field concentration layer 7 is lower than that of the pn junction composed of the first body layer 5a and the electric field concentration layer 7, it can be used in the second The main body layer 5b reliably generates an avalanche.

Since other effects are the same as those of Embodiment 4, description is omitted. [Example 6]

Embodiment 6 is a variation of Embodiment 4. The description will focus on differences from Embodiment 4, and repeated description will be omitted. In addition, Example 6 can also be applied to any one of Example 1 to Example 3 and Example 5.

FIG. 6 is a cross-sectional view illustrating the semiconductor device of Embodiment 6.

In Embodiment 6, the difference from Embodiment 4 is that the bottom (depth Db) of the electric field concentration layer 7 formed at the bottom of the second body layer 5b is deeper than the electric field concentration layer formed at the bottom of the first body layer 5a. The bottom of 7 (depth is big) is deep. Otherwise, it is the same as Example 4.

According to Embodiment 6, when the depth Db of the electric field concentration layer 7 of the second body layer 5b is formed deeper, the avalanche voltage becomes lower, so an avalanche can be reliably generated in the second body layer 5b.

Since other effects are the same as those of Embodiment 4, description is omitted. [Example 7]

Embodiment 7 is an embodiment of the power conversion device.

A power conversion device can be constructed by using the semiconductor device according to any one of Examples 1 to 6 as a switching element. Since the structure of the power conversion device is general, description is omitted.

Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications can be made within the scope of the technical idea of the present invention. In addition, part or all of the components described in each embodiment may be combined and applied.

1: Collector electrode (main electrode on the back side) 2: Emitter electrode (front side main electrode) 3: Gate electrode 4: Dummy electrode 5a: Main layer 1 5b: 2nd main layer 6: Emitter layer (front side electrode layer) 7: Electric field concentration layer 8: Floating layer 9: unit cell 10:Drift layer 11: Buffer layer 12: Collector layer (backside electrode layer) 13: Gate electrode 14:Dummy electrode 15: Field board 20a: 1st trench 20b: 2nd trench 20c:Trench 21a: Gate insulation film 21b: Insulating film 22:Insulating film 23a: Gate insulation film 23b: 1st insulating film 23c: 2nd insulating film 24:Insulating film 24a: 3rd insulating film Da,Db: depth Wa, Wb: width

FIG. 1 is a cross-sectional view illustrating the semiconductor device of Embodiment 1. FIG. 2 is a cross-sectional view illustrating the semiconductor device of Embodiment 2. 3 is a cross-sectional view illustrating the semiconductor device of Embodiment 3. 4 is a cross-sectional view illustrating the semiconductor device of Embodiment 4. FIG. 5 is a cross-sectional view illustrating the semiconductor device of Embodiment 5. FIG. 6 is a cross-sectional view illustrating the semiconductor device of Embodiment 6.

1: Collector electrode (main electrode on the back side)

2: Emitter electrode (front side main electrode)

3: Gate electrode

4: Dummy electrode

5a: Main layer 1

5b: 2nd main layer

6: Emitter layer (front side electrode layer)

7: Electric field concentration layer

8: Floating layer

9: unit cell

10:Drift layer

11: Buffer layer

12: Collector layer (back side electrode layer)

20a: 1st trench

20b: 2nd trench

21a: Gate insulation film

21b: Insulating film

22:Insulating film

Claims (9)

A semiconductor device having: Drift layer of conductivity type 1; The first body layer of the second conductivity type is formed on the front surface of the above-mentioned drift layer; A front-side electrode layer of the first conductivity type is formed on the front surface of the above-mentioned first body layer; A front-side main electrode connected to the above-mentioned first body layer and the above-mentioned front-side electrode layer; A first trench formed in contact with the first body layer and the front-side electrode layer; A gate electrode formed inside the first trench; and A gate insulating film formed inside the first trench, between the first body layer and the gate electrode, and between the front-side electrode layer and the gate electrode; and the characteristics of the semiconductor device consists in having: A second body layer of the second conductivity type is formed on the front surface of the drift layer, without forming the front-side electrode layer and connected to the front-side main electrode; a second trench formed in contact with the above-mentioned second body layer; A dummy electrode is formed inside the second trench and has the same potential as the front-side main electrode; An insulating film formed inside the second trench and between the second body layer and the dummy electrode; An electric field concentration layer of the first conductivity type is formed at the bottom of the above-mentioned second body layer and has an impurity concentration higher than that of the above-mentioned drift layer; and A floating layer of the second conductivity type is formed between the first trench and the second trench and is electrically floating. A semiconductor device having: Drift layer of conductivity type 1; The first body layer of the second conductivity type is formed on the front surface of the above-mentioned drift layer; A front-side electrode layer of the first conductivity type is formed on the front surface of the above-mentioned first body layer; A front-side main electrode connected to the above-mentioned first body layer and the above-mentioned front-side electrode layer; A trench formed in contact with the first body layer and the front-side electrode layer; A gate electrode formed on the sidewall of the first body layer side inside the trench; and A gate insulating film is formed inside the trench, between the first body layer and the gate electrode, and between the front-side electrode layer and the gate electrode; and the semiconductor device is characterized by having : A second body layer of the second conductivity type is connected to the trench and is formed on the front side of the drift layer on the opposite side of the first body layer. The front side electrode layer is not formed and is connected to the front side main layer. electrode; A dummy electrode is formed on the side wall of the second body layer side inside the trench and has the same potential as the front-side main electrode; a first insulating film formed inside the trench and between the second body layer and the dummy electrode; An electric field concentration layer of the first conductivity type is formed at the bottom of the above-mentioned second body layer and has an impurity concentration higher than that of the above-mentioned drift layer; A field plate is formed inside the trench and has the same potential as the front-side main electrode; a second insulating film formed inside the trench and between the field plate and the drift layer; and A third insulating film is formed inside the trench, between the field plate and the gate electrode, and between the field plate and the dummy electrode. The semiconductor device of claim 1 or 2, wherein The width of the second main body layer is greater than the width of the first main body layer. The semiconductor device of claim 1 or 2, wherein There is also the above-mentioned electric field concentration layer at the bottom of the above-mentioned first body layer; and The avalanche voltage in the second body layer is smaller than the avalanche voltage in the first body layer. The semiconductor device of claim 4, wherein The impurity concentration of the electric field concentration layer formed at the bottom of the second body layer is higher than the impurity concentration of the electric field concentration layer formed at the bottom of the first body layer. The semiconductor device of claim 4, wherein The bottom of the electric field concentration layer formed at the bottom of the second body layer is formed deeper than the bottom of the electric field concentration layer formed at the bottom of the first body layer. The semiconductor device of claim 1 or 2, wherein The front-side electrode layer is an emitter layer, and the front-side main electrode is an emitter electrode. The semiconductor device of claim 1 or 2, wherein The front-side electrode layer is a source layer, and the front-side main electrode is a source electrode. A power conversion device characterized by using the semiconductor device according to claim 1 or 2 as a switching element.