TW202339310A - Light-emitting device - Google Patents

Abstract

A light-emitting device includes a substrate including a surface; a first light-emitting unit and a second light-emitting unit formed on the substrate, the irst light-emitting unit and the second light-emitting unit respectively includes a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor laeyr and the second semiconductor layer; a trench formed between the first light-emitting unit and the second light-emitting unit, exposing the surface of the substrate; a first surrounding part formed on the first light-emitting unit, surrounding the first light-emitting unit and exposing the first semiconductor layer of the first light-emitting unit; a second surrounding part formed on the second light-emitting unit, surrounding the second light-emitting unit and exposing the first semiconductor layer of the second light-emitting unit; a first insulating layer including a first opening on the first surrounding part and a second opening on the second semiconductor layer of the second light-emitting unit; and one or a plurality of connecting electrodes respectively includes a first connecting end on the first light-emitting unit and connected to the first semiconductor layer formed in the first opening, a second connecting end on the second light-emitting unit and connected to the second semiconductor layer of the second light-emitting unit, and a third connecting end formed in the trench to connect the first connecting end and the second connecting end.

Description

Light emitting element

The present invention relates to a light-emitting element, and in particular to a light-emitting element, which includes a plurality of light-emitting units and one or a plurality of connecting electrodes located between the plurality of light-emitting units.

Light-Emitting Diode (LED) is a solid-state semiconductor light-emitting element. Its advantages are low power consumption, low heat energy generation, long working life, shockproof, small size, fast response speed and good optoelectronic properties, such as Stable luminescence wavelength. Therefore, light-emitting diodes are widely used in household appliances, equipment indicators, and optoelectronic products.

A light-emitting element includes a substrate with a surface; a first light-emitting unit and a second light-emitting unit are located on the substrate, each of the first light-emitting unit and the second light-emitting unit includes a first semiconductor layer and a second semiconductor layer, and An active layer is located between the first semiconductor layer and the second semiconductor layer; a trench is located between the first light-emitting unit and the second light-emitting unit, exposing the surface of the substrate; a first surrounding portion is located on the first light-emitting unit and surrounds the first light-emitting unit. a light-emitting unit and exposes the first semiconductor layer located on the first light-emitting unit; a second surrounding portion located on the second light-emitting unit, surrounding the second light-emitting unit and exposing the first semiconductor layer located on the second light-emitting unit; An insulating layer includes a first opening on the first surrounding portion of the first light-emitting unit and a second opening on the second semiconductor layer of the second light-emitting unit; and one or a plurality of connection electrodes each include a first connection terminal. is located on the first light-emitting unit and connected to the first semiconductor layer located in the first opening, a second connection terminal is located on the second light-emitting unit and connected to the second semiconductor layer located in the second light-emitting unit, and a third connection The end is located in the trench to connect the first connection end and the second connection end.

A light-emitting element includes a substrate with a surface; a first light-emitting unit and a second light-emitting unit are located on the substrate, each of the first light-emitting unit and the second light-emitting unit includes a first semiconductor layer and a second semiconductor layer, and An active layer is located between the first semiconductor layer and the second semiconductor layer; a trench is located between the first light-emitting unit and the second light-emitting unit, exposing the surface of the substrate; a first surrounding portion is located on the first light-emitting unit and surrounds the first light-emitting unit. a light-emitting unit and exposing the first semiconductor layer located on the first light-emitting unit; a second surrounding portion located on the second light-emitting unit, surrounding the second light-emitting unit and exposing the first semiconductor layer located on the second light-emitting unit; or Each of the plurality of connection electrodes includes a first connection end located on the first light-emitting unit and connected to the first semiconductor layer of the first light-emitting unit, and a second connection end located on the second light-emitting unit and connected to the second light-emitting unit. two semiconductor layers, and a third connection end located in the trench to connect the first connection end and the second connection end; and an insulating layer including a first opening located below the first connection end and a second opening located under the second connection end Below, as seen from a top view of one of the self-luminous elements, the second opening includes an opening area larger than the opening area of the first opening.

A light-emitting element includes a substrate with a surface; a first light-emitting unit and a second light-emitting unit are located on the substrate, each of the first light-emitting unit and the second light-emitting unit includes a first semiconductor layer and a second semiconductor layer, and An active layer is located between the first semiconductor layer and the second semiconductor layer; a trench is located between the first light-emitting unit and the second light-emitting unit, exposing the surface of the substrate; a first recess is located on the first light-emitting unit and exposed on the surface of the substrate. a first semiconductor layer on the first light-emitting unit; a second recessed portion located on the second light-emitting unit and exposing the first semiconductor layer located on the second light-emitting unit, wherein the first recessed portion and the second recessed portion are located between the trenches Two opposite sides; one or a plurality of connection electrodes each include a first connection end located on the first recessed portion and contacting the first semiconductor layer of the first light-emitting unit, and a second connection end covering the second recessed portion and electrically connected to The second semiconductor layer of the second light-emitting unit and a third connection terminal are located in the trench to connect the first connection terminal and the second connection terminal; and an insulating layer covers the first semiconductor layer of the second recessed portion and is located in the second below the connection end.

A light-emitting element includes a substrate with a surface; a first light-emitting unit and a second light-emitting unit are located on the substrate, each of the first light-emitting unit and the second light-emitting unit includes a first semiconductor layer and a second semiconductor layer, and An active layer is located between the first semiconductor layer and the second semiconductor layer; a trench is located between the first light-emitting unit and the second light-emitting unit, exposing the surface of the substrate; a first surrounding portion is located on the first light-emitting unit and exposed on the surface of the substrate. a first semiconductor layer on the first light-emitting unit; a second surrounding portion located on the second light-emitting unit and exposing the first semiconductor layer located on the second light-emitting unit; a plurality of connection electrodes located on the first light-emitting unit and the second light-emitting unit Each includes a first connection end located on the first surrounding part and contacting the first semiconductor layer of the first light-emitting unit, and a second connection end covering the second surrounding part and formed with the second semiconductor layer of the second light-emitting unit. Electrical connection, and a third connection terminal is located in the trench to connect the first connection terminal and the second connection terminal; a first lower electrode is located on the first surrounding portion and contacts the first semiconductor layer on the first light-emitting unit; and a plurality of A second lower electrode convex portion is located on the second surrounding portion and contacts the first semiconductor layer on the second light-emitting unit. Viewed from a top view of one of the self-luminous elements, a plurality of connecting electrodes and a plurality of second lower electrode convex portions The systems are arranged alternately with each other.

In order to make the description of the present invention more detailed and complete, please refer to the description of the following embodiments and the relevant illustrations. However, the embodiments shown below are used to illustrate the light-emitting element of the present invention, and the present invention is not limited to the following embodiments. In addition, the size, material, shape, relative arrangement, etc. of the constituent parts described in the embodiments described in this specification are not described as limiting, and the scope of the present invention is not limited thereto, but is merely explained. In addition, the size and positional relationship of components shown in each diagram may be exaggerated for clear explanation. Moreover, in the following description, in order to omit detailed explanation appropriately, components of the same or similar nature are shown with the same names and symbols.

FIG. 1 is a top view of forming a trench and a hole in a semiconductor stack according to an embodiment of the present invention. Figure 2 is a cross-sectional view along the tangent line A-A’ of Figure 1. The semiconductor stack includes a first semiconductor layer 201, an active layer 202, and a second semiconductor layer 203 sequentially formed on the surface of a substrate 10. One or a plurality of trenches 21 pass through the second semiconductor layer 203, the active layer 202 and the first semiconductor layer 201 to expose one or a plurality of surfaces 21s of the substrate 10, and separate the semiconductor stack into a plurality of light-emitting units 20, wherein a plurality of The light-emitting units 20 are separated from each other by trenches 21 .

In this embodiment, as shown in Figures 1 and 2, the light-emitting element 1 includes a first light-emitting unit 20a and a second light-emitting unit 20b, where the first light-emitting unit 20a and the second light-emitting unit 20b are trenches 21 are separated, and the surface 21s of the substrate 10 is exposed.

In another embodiment (not shown), the light-emitting element 1 includes a plurality of light-emitting units 20 arranged to form a rectangular array, and the plurality of light-emitting units 20 are separated from each other by a plurality of trenches 21, wherein the plurality of light-emitting units 20 The trenches 21 may have the same area and/or shape, or different areas and/or shapes. The plurality of trenches 21 are connected to each other to continuously expose the surface 21s of the substrate 10 .

In one embodiment, the light-emitting element 1 may have a polygonal shape, such as a triangle, a hexagon, a rectangle or a square. The light-emitting element 1 includes a substrate 10 with a plurality of outer side walls S located around one of the light-emitting elements 1 to form a polygonal shape, such as a triangle, a hexagon, a rectangle or a square. Viewed from the top view, the size of the light-emitting element 1 may be, for example, a square shape of 1000 μm × 1000 μm or 700 μm × 700 μm, or a rectangular shape of similar size, but is not particularly limited thereto.

The substrate 10 may be a growth substrate, including a gallium arsenide (GaAs) wafer used to epitaxially grow aluminum gallium indium phosphide (AlGaInP), or a sapphire (Al ₂ O ₃ ) used to grow indium gallium nitride (InGaN). ) wafer, gallium nitride (GaN) wafer or silicon carbide (SiC) wafer. In another embodiment, the substrate 10 can be a supporting substrate. The semiconductor stack originally grown on the growth substrate by epitaxial growth can be transferred to the aforementioned supporting substrate, and the growth substrate originally used for epitaxial growth can be used again according to the application. selectively removed if necessary.

The supporting substrate includes conductive materials, such as silicon (Si), aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), silicon carbide (SiC) or the above materials Alloys, or thermally conductive materials, such as diamond, graphite, or aluminum nitride. Moreover, although not shown in the figure, the side of the substrate 10 that is in contact with the semiconductor stack may have an increased roughened surface. The roughened surface may be a surface with an irregular shape or a surface with a regular shape, such as a plurality of hemispheres. A surface of a shape, a surface with multiple cone shapes, or a surface with multiple polygonal cone shapes.

In one embodiment of the present invention, metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD) or ion The electroplating method is used to form a semiconductor stack with optoelectronic properties, such as a light-emitting stack, on the substrate 10 . The physical vapor deposition method includes sputtering or evaporation.

In one embodiment of the present invention, the semiconductor stack may further include a buffer layer (not shown) located between the first semiconductor layer 201 and the substrate 10 to release material between the substrate 10 and the first semiconductor layer 201. The stress caused by lattice mismatch can reduce misalignment and lattice defects, thereby improving the epitaxial quality. The buffer layer may be a single layer or a structure including multiple layers. In one embodiment, PVD aluminum nitride (AlN) can be used as a buffer layer formed between the first semiconductor layer 201 and the substrate 10 to improve the epitaxial quality of the semiconductor stack. In one embodiment, the target used to form PVD aluminum nitride (AlN) is composed of aluminum nitride. In another embodiment, a target composed of aluminum is used, and aluminum nitride is formed by reacting with the aluminum target in a nitrogen source environment.

The wavelength of light emitted by the light-emitting element 1 is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack. The material of the semiconductor stack includes III-V group semiconductor materials, such as Al _x In _y Ga _(1-xy) N or Al _x In _y Ga _(1-xy) P, where 0≦x, y≦1; (x+ y)≦1. When the material of the semiconductor stack is AlInGaP series material, it can emit red light with a wavelength between 610 nm and 650 nm, or green light with a wavelength between 530 nm and 570 nm. When the material of the semiconductor stack is an InGaN series material, it can emit blue light with a wavelength between 400 nm and 490 nm. When the material of the semiconductor stack is AlGaN series or AlInGaN series material, it can emit ultraviolet light with a wavelength between 400 nm and 250 nm.

The first semiconductor layer 201 and the second semiconductor layer 203 can be cladding layers, which have different conductivity types, electrical properties, polarities, or are doped with elements to provide electrons or holes, such as a third The first semiconductor layer 201 is an n-type semiconductor, and the second semiconductor layer 203 is a p-type semiconductor. The active layer 202 is formed between the first semiconductor layer 201 and the second semiconductor layer 203. Electrons and holes are driven by a current to recombine in the active layer 202, converting electrical energy into light energy to emit light. The active layer 202 may be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum structure (multi-quantum). well, MQW). The material of the active layer 202 may be a neutral, p-type or n-type electrical semiconductor. The first semiconductor layer 201, the active layer 202, or the second semiconductor layer 203 may be a single layer or a structure including multiple layers.

As shown in FIG. 2 , selective etching is then performed on each light-emitting unit 20 to form one or a plurality of hole portions 200 , one or a plurality of surrounding portions 204 and one or a plurality of semiconductor platforms 205 on each light-emitting unit 20 . . The semiconductor platform 205 on each light-emitting unit 20 is surrounded by one or a plurality of surrounding parts 204. For example, the photoresist pattern of the hole portion 200 , the surrounding portion 204 and the semiconductor platform 205 is formed by coating a photoresist and then removing part of the photoresist through a conventional patterning process. Then, the photoresist pattern is used as an etching mask to perform an etching process to form the hole portion 200, the surrounding portion 204 and the semiconductor platform 205. Specifically, each semiconductor platform 205 is formed by removing part of the second semiconductor layer 203 and the active layer 202 to form a structure including the first semiconductor layer 201, the active layer 202, and the second semiconductor layer 203. Each of the hole portions 200 and the surrounding portions 204 is formed by removing part of the second semiconductor layer 203 and the active layer 202 to expose the first semiconductor layer 201 respectively. After the etching process, the remaining photoresist pattern is removed. In other words, the semiconductor platform 205 includes the first semiconductor layer 201 , the active layer 202 and the second semiconductor layer 203 . The hole portion 200 and the surrounding portion 204 include the first semiconductor layer 201 but do not include the second semiconductor layer 203 and the active layer 202 .

As shown in Figure 2, each semiconductor platform 205 includes an upper surface t1 and a lower surface b1, and the active layer 202 includes a first upper surface and a second lower surface, wherein the first upper surface of the active layer 202 is lower than the second surface. The surface is closer to the upper surface t1 of the semiconductor platform. There is a first distance between the upper surface t1 of the semiconductor platform 205 and the first upper surface of the active layer 202. The lower surface b1 of the semiconductor platform 205 and the second lower surface of the active layer 202 There is a second distance between them, and the second distance is greater than the first distance.

In one embodiment, when the semiconductor stack is transferred from the growth substrate to the support substrate, each semiconductor platform 205 includes an upper surface t1 and a lower surface b1, and the active layer 202 includes a first upper surface and a second lower surface. , where the upper surface t1 of the semiconductor platform 205 and the first upper surface of the active layer 202 are respectively farther from the supporting substrate than the lower surface b1 of the semiconductor platform and the second lower surface of the active layer 202. The upper surface t1 of the semiconductor platform 205 and the active layer 202 are respectively A first distance is included between the first upper surface of the layer 202 , a second distance is included between the lower surface b1 of the semiconductor platform 205 and the second lower surface of the active layer 20 , and the first distance is greater than the second distance.

Viewed from a top view of the light-emitting element 1, as shown in Figure 1, the shape of one or a plurality of holes 200 includes an ellipse, a circle, a rectangle or other arbitrary shapes. .

In one embodiment, as shown in FIG. 1 , each light-emitting unit 20 only includes one surrounding portion 204 . In this embodiment, the surrounding portion 204 is located at the outermost side of each light-emitting unit 20 and continuously surrounds the light-emitting unit 20. The outermost side of the light emitting unit 20 includes a continuously surrounding surrounding portion 204 . Viewed from a top view of the light-emitting element 1 , the shape of the surrounding portion 204 includes a polygon, such as a triangle, a hexagon, a rectangle or other arbitrary shapes. In other words, the shape of the surrounding portion 204 corresponds to the shape of each light-emitting unit 20 . The shape of each surrounding portion 204 is similar to the shape of each light-emitting unit 20 . In this embodiment, the shape of the surrounding portion 204 includes a rectangle, and the shape of each light-emitting unit 20 includes a rectangle. The surrounding portion 204 is located at the outermost side of each light-emitting unit 20, and the corners of the rectangular shape of the light-emitting unit 20 can be rounded to avoid localization of current. Concentrate on the corners of each light-emitting unit 20. The surrounding portion 204 continuously surrounds the second semiconductor layer 203 and the active layer 202 of each light-emitting unit 20 by exposing the surface of the outermost first semiconductor layer 201 of each light-emitting unit 20 .

In another embodiment (not shown), each light-emitting unit 20 includes a plurality of surrounding portions 204 . The shape of each plurality of surrounding portions 204 respectively includes a rectangle, an ellipse, or a circle, and the plurality of surrounding portions 204 are located at the outermost side of each light-emitting unit 20 to continuously surround the second semiconductor layer 203 and active layer of each light-emitting unit 20 . Layer 202. In order to prevent the current from being locally concentrated in the corners of each light-emitting unit 20, the semiconductor stack located at the corners of each light-emitting unit 20, that is, the second semiconductor layer 203 and the active layer 202 in the corners can be retained without being removed. A plurality of surrounding portions 204 are formed on multiple sides of each light-emitting unit 20 by removing the second semiconductor layer 203 and the active layer 202 located on multiple sides of each light-emitting unit 20 . One or more surrounding portions 204 are located on one of the plurality of sides of each light-emitting unit 20 . The number of surrounding portions 204 included on one side of each light-emitting unit 20 may be the same or different from the number of surrounding portions 204 included on the other side of the plurality of sides. Taking one of the light-emitting units 20 as an example, one side of the light-emitting unit 20 includes one or more surrounding parts 204. The other side of the light-emitting unit 20, such as its adjacent side or the opposite side, includes the surrounding parts 204, which may be one or more. Multiple, the number of surrounding parts 204 on both sides may be the same or different.

As shown in FIG. 1 , one or a plurality of hole portions 200 are located inside each light-emitting unit 20 and are surrounded by one or a plurality of surrounding portions 204 . In other words, one or a plurality of hole portions 200 are respectively surrounded by the second semiconductor layer 203 and the active layer 202 of each light-emitting unit 20 .

The number and arrangement position of the plurality of holes 200 are not limited, and they can be regularly arranged at certain intervals, so that the current can be evenly dispersed in the horizontal direction. The plurality of holes 200 can be arranged in a plurality of columns, and the holes 200 in any two adjacent columns or every two adjacent columns can be aligned or staggered with each other. The positions of subsequent contact layers and electrode layers can be determined according to the arrangement positions of the plurality of holes 200 .

In one embodiment of the present invention (not shown), the holes 200 in two adjacent rows are staggered from each other, and the distance between the holes 200 in the two adjacent rows is the same as the distance between the holes 200 in the same row. The spacing between them is the same, so that the plurality of hole portions 200 form the most densely packed and evenly distribute the current.

In one embodiment of the present invention (not shown), considering the positions of subsequent contact layers and electrode layers, the holes 200 in two adjacent columns are staggered from each other and are located between the holes 200 in two adjacent columns. The spacing is smaller than the spacing between the holes 200 located in the same row.

In one embodiment of the present invention (not shown), considering the positions of subsequent contact layers and electrode layers, the holes 200 in two adjacent columns are staggered from each other and are located between the holes 200 in two adjacent columns. The spacing is greater than the spacing between the holes 200 located in the same row.

As shown in Figures 1 and 2, the first light-emitting unit 20a includes a first semiconductor platform 205a. The first light-emitting unit 20a includes one or a plurality of first hole portions 200a to expose the inner surface 200as of the first semiconductor layer 201, wherein the plurality of first hole portions 200a are not connected to each other when viewed from a top view of one of the light-emitting elements. . The first light-emitting unit 20a includes a first surrounding portion 204a formed on multiple sides of the first light-emitting unit 20a to continuously expose the outer surface 204as of the first semiconductor layer 201, wherein the first surrounding portion 204a includes a first inner recess 2041a. and a plurality of first outer recesses 2042a. The first hole portion 200a is formed in the first semiconductor platform 205a, and the first surrounding portion 204a surrounds the first semiconductor platform 205a.

As shown in Figures 1 and 2, the second light-emitting unit 20b includes a second semiconductor platform 205b. The second light-emitting unit 20b includes one or a plurality of second hole portions 200b to expose the inner surface 200bs of the first semiconductor layer 201, wherein the plurality of second hole portions 200b are not connected to each other when viewed from a top view of one of the light-emitting elements. . The second light-emitting unit 20b includes a second surrounding portion 204b formed on multiple sides of the second light-emitting unit 20b to continuously expose the outer surface 204bs of the first semiconductor layer 201, wherein the second surrounding portion 204b includes a second inner recessed portion 2041b. and a plurality of second outer recesses 2042b. The second hole portion 200b is formed in the second semiconductor platform 205b, and the second surrounding portion 204b surrounds the second semiconductor platform 205b.

As shown in Figures 1 and 2, the trench 21 between the first light-emitting unit 20a and the second light-emitting unit 20b is located in the first recessed portion 2041a of the first light-emitting unit 20a and the second recessed portion 2041a of the second light-emitting unit 20b. between the inner concave portions 2041b.

As shown in FIG. 2, the first hole portion 200a is located in the first semiconductor platform 205a, and the first inner concave portion 2041a and the first outer concave portion 2042a are respectively located on both sides of the first semiconductor platform 205a. The second hole portion 200b is located in the second semiconductor platform 205b, and the second inner recessed portion 2041b and the second outer recessed portion 2042b are respectively located on both sides of the second semiconductor platform 205b.

The first hole portion 200a and the second hole portion 200b each include a first slope S1, which respectively has a first slope within a range relative to the horizontal extension surfaces of the inner surface 200as and the inner surface 200bs of the first semiconductor layer 201. A bevel angle, such as an internal angle between 10 degrees and 80 degrees. The first surrounding portion 204a and the second surrounding portion 204b each include a second slope S2, which respectively has a first slope within a range relative to the horizontal extension surface of the outer surface 204as and the outer surface 204bs of the first semiconductor layer 201. Two bevel angles, such as internal angles between 10 degrees and 80 degrees. If the angle is less than 10 degrees, a too low slope will reduce the area of the active layer 202, and the reduction in the area of the active layer 202 will result in a reduction in the brightness of the light-emitting element. If the angle is greater than 80 degrees, the subsequent insulating layer and metal layer may not be able to completely cover the sidewalls of the first semiconductor layer 201, the second semiconductor layer 203, and/or the active layer 202, resulting in cracking of the film layers.

In one embodiment, in order to maintain the symmetry of the structure and reduce mask alignment errors during the manufacturing process, the angle difference between the first bevel angle and the second bevel angle is less than 20 degrees, preferably less than 10 degrees, and more preferably less than 10 degrees. 5 degrees.

In one embodiment, the first semiconductor layer 201 of each light-emitting unit 20 includes a third slope S3, which has an oblique angle within a range relative to the outer surface 204as or the outer surface 204bs of the first semiconductor layer 201 , such as an angle of 10 degrees to 80 degrees.

In another embodiment, the third slope S3 included in the first semiconductor layer 201 has an angle close to 90 degrees with respect to the outer surface 204as or the outer surface 204bs of the first semiconductor layer 201, preferably 60 degrees. to an angle of 120 degrees, preferably an angle of 80 degrees to 110 degrees.

In one embodiment, the third slope S3 of the first semiconductor layer 201 is directly connected to an outer side wall S of the substrate 10 . The outer side wall S of the substrate 10 can be flush with the third slope S3 of the first semiconductor layer 201, or have an oblique angle within a range relative to the third slope S3 of the first semiconductor layer 201, preferably An angle of 60 degrees to 120 degrees, preferably an angle of 80 degrees to 110 degrees.

In another embodiment, as shown in FIG. 2 , by removing the first semiconductor layer 11 , the second semiconductor layer 12 and the active layer 13 , the light-emitting element 1 includes a cutting line 10 d to expose an upper surface 10 s of the substrate 10 , wherein the first surrounding portion 204a is located between the dicing lane 10d and the first semiconductor platform 205a, and the second surrounding portion 204b is located between the dicing lane 10d and the second semiconductor platform 205b. The third slope S3 has a third slope angle within a range relative to the horizontal extension surface of the upper surface 10s of the substrate 10, for example, the inner angle is between 10 degrees and 80 degrees, preferably less than 60 degrees, and more preferably Less than 40 degrees.

The outer side wall S of the substrate 10 can be perpendicular to the upper surface 10s exposed by the cutting lane 10d, or have a fourth bevel angle within a range relative to the upper surface 10s exposed by the cutting lane 10d, preferably 60 The angle is from 80 to 110 degrees, preferably from 80 to 110 degrees.

In another embodiment, in order to allow the subsequent insulating layer and metal layer to completely cover the third bevel S3, the angle difference between the third bevel angle and the second bevel angle is greater than 15 degrees, preferably greater than 25 degrees, and more preferably Greater than 35 degrees.

From the top view of the light-emitting element 1 , each of the plurality of light-emitting units 20 includes a polygon or a rectangle, and the plurality of light-emitting units 20 are arranged to form a rectangular array with a plurality of sides. The cutting tracks 10d surround a plurality of sides of the rectangular array composed of a plurality of light-emitting units 20, and continuously expose the upper surface 10s of the substrate 10.

The cutting track 10d is located at the outermost side of the light-emitting element 1. The top view shape of the cutting track 10d is the same as the shape of the rectangular array formed by the plurality of light-emitting units 20 arranged, for example, a rectangular or polygonal ring surrounds the outermost side of the rectangular array formed by the plurality of light-emitting units 20 arranged.

In one embodiment, the exposed upper surface 10s of the cutting track 10d is a rough surface. The rough surface may be a surface with an irregular shape or a surface with a regular shape, such as a surface with multiple hemispheric shapes, a surface with multiple cone shapes, or a surface with multiple polygonal cone shapes.

Figure 3 is a top view of forming a contact electrode and a reflective layer according to an embodiment of the present invention. Figure 4 is a cross-sectional view along the tangent line A-A’ in Figure 3. Figure 5 is a continuation of Figure 3, showing a top view of forming a first insulating layer, a contact electrode, a reflective layer and a second insulating layer according to an embodiment of the present invention. Figure 6 is a cross-sectional view along the tangent line A-A’ in Figure 5.

As shown in FIG. 5 , a first insulating layer 50 is formed on the substrate 10 and each light-emitting unit 20 . One or a plurality of first insulating layer openings 500 are formed on the first light-emitting unit 20a, the second light-emitting unit 20b and the trench 21 by selective etching to jointly expose the substrate 10 and the first semiconductor layer of the first light-emitting unit 20a. 201 and the first semiconductor layer 201 of the second light-emitting unit 20b. In one embodiment, one or a plurality of first insulating layer openings 500 formed in the trench 21 simultaneously expose the first semiconductor layer 201 in the first recessed portion 2041a and the second recessed portion 2041b.

As shown in FIGS. 5 and 6 , the first recess 2041a of the first light-emitting unit 20a forms one or a plurality of first openings 501a in the first insulation layer on one side adjacent to the trench 21 to expose the first light-emitting unit 20a. the first semiconductor layer 201.

As shown in Figure 5, one or a plurality of second openings 502a and 502b of the first insulating layer are formed on the second semiconductor layer 203 of the first light-emitting unit 20a and the second light-emitting unit respectively to expose the second semiconductor layer 203, contact Electrode 30 and/or reflective layer 40 .

As shown in FIG. 5 , one or a plurality of third openings 503a of the first insulating layer are respectively formed on the plurality of first outer recesses 2042a of the first light-emitting unit 20a to expose the first semiconductor layer 201 of the first light-emitting unit 20a. Another or a plurality of third openings 503b of the first insulating layer are respectively formed on the plurality of second outer recesses 2042b of the second light-emitting unit 20b to expose the first semiconductor layer 201 of the second light-emitting unit 20b.

As shown in Figure 5, a fourth opening 504a, 504b of the first insulating layer is formed on the first hole 200a of the first light-emitting unit 20a and the second hole 200b of the second light-emitting unit 20b respectively to expose the first semiconductor. Layer 201. The remaining area shown in Figure 5 is shielded by the first insulating layer 50.

In one embodiment, the first insulating layer 50 may be formed of a light-transmissive insulating material. For example, the material of the first insulating layer 50 includes SiO _x .

In one embodiment, the first insulating layer 50 may include two or more materials with different refractive indexes alternately stacked to form a Bragg reflector (DBR) structure. In one embodiment, the first insulating layer 50 can be stacked with layers such as SiO ₂ /TiO ₂ or SiO ₂ /Nb ₂ O ₅ to selectively reflect light of specific wavelengths and increase the light extraction efficiency of the light-emitting element. When the peak emission wavelength of the light-emitting element 1 is λ, the optical thickness of the first insulating layer 50 may be set to an integer multiple of λ/4. The peak wavelength refers to the wavelength with the strongest intensity in the luminescence spectrum of the light-emitting element 1 . On the basis of an integral multiple of the optical thickness λ/4, the thickness of the first insulating layer 50 may have a deviation of ±30%.

In one embodiment, the first insulating layer 50 is made of non-conductive material, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), Acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide ( Polyetherimide) or fluorocarbon polymer (Fluorocarbon Polymer), or inorganic materials, such as silicone or glass, or dielectric materials, such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ).

In one embodiment, the thickness of the first insulating layer 50 may range from 1,000 angstroms to 20,000 angstroms.

In one embodiment, the material of the first insulating layer 50 is selected from SiO ₂ , TiO ₂ , SiN _x and other materials. If the thickness of the first insulating layer 50 is less than 1000 angstroms, the thinner thickness may cause Insulating properties become weaker. Specifically, the first insulating layer 50 is formed on the etched first bevel S1 and the second bevel S2. The first insulating layer 50 formed to cover the bevel also has a specific slope. If the first insulating layer 50 is Thickness less than 1000 angstroms may cause film rupture.

In one embodiment, the material of the first insulating layer 50 is selected from SiO ₂ , TiO ₂ , _SiN of difficulty. However, the above embodiments do not rule out that other materials with good coverage extensibility or highly selective etching materials can avoid the above-mentioned problems caused by the first insulating layer 50 being too thin or too thick.

The first insulating layer 50 has one side surface, which is a slope relative to the horizontal extension surface of the inner surface 200as or the surface 204as of the first semiconductor layer 201 exposed through selective etching. This slope is relative to the horizontal extension surface exposed through selective etching. The inner surface 200as or the surface 204as of the first semiconductor layer 201 has an oblique angle between 10 degrees and 70 degrees in terms of a horizontal extension surface.

If the slope angle of the side surface of the first insulating layer 50 is less than 10 degrees, the substantial thickness of the first insulating layer 50 will be reduced. Therefore, there may be a problem that it is difficult to ensure insulation properties.

If the bevel angle of the side surface of the first insulating layer 50 is greater than 70 degrees, subsequent insulating layers and metal layers may not be completely covered, resulting in cracking of the film layer.

As shown in FIGS. 4 and 6 , a contact electrode 30 is formed on the second semiconductor layer 203 of each light-emitting unit 20 . Specifically, the contact electrode 30 is formed in one or a plurality of the second openings 502a and 502b of the first insulation layer. In other words, the contact electrode 30 is exposed by one or a plurality of the second openings 502 a and 502 b of the first insulating layer on each light-emitting unit 20 . Contact electrode 30 includes a transparent electrode. The material of the transparent electrode includes a translucent conductive oxide or a translucent metal. Transparent conductive oxides include indium tin oxide (ITO), zinc oxide (zinc oxide, ZnO), zinc indium tin oxide (ZITO), and indium zinc oxide (zinc indium oxide, ZIO) , zinc tin oxide (ZTO), gallium indium tin oxide (GITO), gallium indium oxide (GIO), or gallium zinc oxide (GZO). The light-transmissive conductive oxide may include various dopants, such as aluminum doped zinc oxide (AZO) or fluorine doped tin oxide (FTO). The translucent metal includes nickel (Ni) or gold (Au).

The thickness of the contact electrode 30 is not limited, but may have a thickness of approximately 0.1 nm to 100 nm. In one embodiment, the material of the contact electrode 30 is a translucent conductive oxide. If the thickness of the contact electrode 30 is less than 0.1 nm, the thickness will be too thin to effectively form ohmic contact with the second semiconductor layer 203 . Moreover, if the thickness of the contact electrode 30 is greater than 100 nm, the light emitted by the active layer 202 will be partially absorbed due to the thickness being too thick, thereby causing a problem of reduced brightness of the light-emitting element 1 . Since the contact electrode 130 has a thickness within the above range, the current can be smoothly dispersed in the horizontal direction, thereby improving the electrical performance of the light-emitting element. However, the above embodiments do not exclude other materials with lateral current diffusion.

The contact electrode 30 is formed on substantially the entire surface of the second semiconductor layer 203 of each light-emitting unit 20 , and forms a low-resistance contact, such as an ohmic contact, with the second semiconductor layer 203 of each light-emitting unit 20 . Therefore, current can flow through the contact electrode 30 . Diffuses uniformly through the second semiconductor layer 203 . In one embodiment, from the cross-sectional view of the self-luminous element, the contact electrode 30 includes an outermost side, which is separated from the second slope S2 of the light-emitting unit 20 by a horizontal distance of less than 20 μm, preferably less than 10 μm, and more preferably less than 5 μm. μm.

A reflective layer 40 is formed on the contact electrode 30 of each light-emitting unit 20 . The material of the reflective layer 40 includes metals such as aluminum (Al), silver (Ag), rhodium (Rh), platinum (Pt) or alloys of the above materials. The reflective layer 40 is used to reflect light and emit the reflected light toward the substrate 10 . The reflected light is generated by the active layer 202 of each light-emitting unit 20 .

In another embodiment, the step of forming the contact electrode 30 may be omitted. The reflective layer 40 is formed in one or a plurality of the second openings 502 a and 502 b of the first insulating layer of each light-emitting unit 20 , and the reflective layer 40 can form an ohmic contact with the second semiconductor layer 203 .

In one embodiment, when viewed from the cross-sectional view of the self-luminous element, as shown in Figures 4 and 6, the reflective layer 40 includes an outermost side that is separated from the second slope S2 of the light-emitting unit 20 by a horizontal distance of less than 20 μm. , preferably less than 10 μm, more preferably less than 5 μm.

In one embodiment, the reflective layer 40 may be a one- or multi-layer structure. The multi-layer structure may be a Bragg reflective structure.

In one embodiment, one surface of the reflective layer 40 is an inclined surface relative to the upper surface of the second semiconductor layer 203 , and the inclined surface may have an oblique angle of 10 degrees to 60 degrees relative to the surface of the second semiconductor layer 203 . The material of the reflective layer 40 is silver (Ag). If the slope angle of the reflective layer 40 is less than 10 degrees, the very gentle slope will reduce the reflection efficiency of the bottom light. In addition, it is difficult to ensure thickness uniformity with a bevel angle less than 10 degrees. If the bevel angle of the reflective layer 40 is greater than 60 degrees, the bevel angle greater than 60 degrees may cause subsequent film layers to crack. However, the above embodiments do not exclude other materials with high reflectivity.

The tilt angle adjustment of the reflective layer 40 can be achieved by changing the configuration of the substrate and the advancing direction of the metal atoms in the thermal deposition process. For example, the position of the substrate is adjusted so that the surface of the substrate is an inclined surface relative to the deposition direction of evaporation or sputtering.

In one embodiment, a barrier layer (not shown) is formed on the reflective layer 40 of each light-emitting unit 20 to cover the upper surface and side surfaces of the reflective layer 40 to prevent surface oxidation of the reflective layer 40 and thus deterioration of the reflective layer. Reflectivity of 40. The materials of the barrier layer include metal materials, such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), chromium (Cr), platinum (Pt), etc. Metals or alloys of the above materials. The barrier layer may be one or a multi-layer structure. The multi-layer structure is, for example, titanium (Ti)/aluminum (Al), and/or nickel titanium alloy (NiTi)/titanium tungsten alloy (TiW). In one embodiment of the present invention, the barrier layer includes a stacked structure of titanium (Ti)/aluminum (Al) and a stacked structure of nickel-titanium alloy (NiTi)/titanium-tungsten alloy (TiW), wherein titanium ( The stacked structure of Ti)/aluminum (Al) is located on the side away from the reflective layer 40, and the stacked structure of nickel titanium alloy (NiTi)/titanium tungsten alloy (TiW) is located on the side close to the reflective layer 40. In one embodiment of the present invention, the materials of the reflective layer 40 and the barrier layer preferably include metal materials other than gold (Au) or copper (Cu).

The stacked structure of the barrier layer is selected from nickel titanium alloy (NiTi)/titanium tungsten alloy (TiW)/platinum (Pt)/titanium (Ti)/aluminum (Al)/titanium (Ti)/aluminum (Al)/chromium (Cr) )/Platinum (Pt), the barrier layer may have an oblique angle of 10 to 60 degrees with respect to the surface of the second semiconductor layer 203 . In one embodiment, if the slope angle of the barrier layer is less than 10 degrees, the very gentle slope cannot completely cover the reflective layer 40 . In addition, it is difficult to ensure thickness uniformity with a bevel angle less than 10 degrees. If the bevel angle of the barrier layer is greater than 60 degrees, the bevel angle greater than 60 degrees may cause subsequent film layers to crack.

In one embodiment, the thickness of the reflective layer 40 or the barrier layer is preferably 100 nm to 1 μm. If the thickness of the reflective layer 40 or the barrier layer is less than 100 nm, the light emitted by the active layer 203 cannot be effectively reflected. Moreover, if the thickness of the reflective layer 40 or the barrier layer is greater than 1 μm, excessive manufacturing time will result in manufacturing losses.

In order to cover the upper surface and side surfaces of the reflective layer 40 , the barrier layer includes a bottom surface to contact the second semiconductor layer 203 and/or the contact electrode 30 .

As shown in Figure 5, a second insulating layer 60 is formed on the substrate 10 and each light-emitting unit 20, and a selective etching method is used to form a second insulating layer 60 on the first light-emitting unit 20a, the second light-emitting unit 20b and the trench 21. Or a plurality of second insulating layer openings 600 are used to jointly expose the substrate 10, the first semiconductor layer 201 of the first light-emitting unit 20a, and the first semiconductor layer 201 of the second light-emitting unit 20b. In one embodiment, one or a plurality of second insulating layer openings 600 formed adjacent to the trench 21 simultaneously expose the first semiconductor layer 201 in the first recessed portion 2041a and the second recessed portion 2041b.

As shown in FIGS. 5 and 6 , the first recessed portion 2041a of the first light-emitting unit 20a forms one or a plurality of first openings 601a in the second insulating layer adjacent to the trench 21 to expose the first semiconductor layer 201.

As shown in Figure 5, one or a plurality of second openings 602a and 602b of the second insulating layer are formed on the second semiconductor layer 203 of the first light-emitting unit 20a and the second light-emitting unit respectively to expose the second semiconductor layer 203 and the contact. Electrode 30 and/or reflective layer 40 .

As shown in FIG. 5 , from a top view of the light-emitting element 1 , the positions of the plurality of first openings 601 a of the second insulating layer and the plurality of second openings 602 b of the second insulating layer are aligned with each other.

As shown in FIG. 5 , one or a plurality of third openings 603 a of the second insulating layer are respectively formed on the plurality of first outer recesses 2042 a of the first light-emitting unit 20 a to expose the first semiconductor layer 201 of the first light-emitting unit 20 a. Another or a plurality of third openings 603b of the second insulating layer are respectively formed on the plurality of second outer recesses 2042b of the second light-emitting unit 20b to expose the first semiconductor layer 201 of the second light-emitting unit 20b.

As shown in Figure 5, a fourth opening 604a, 604b of the second insulating layer is formed on the first hole 200a of the first light-emitting unit 20a and the second hole 200b of the second light-emitting unit 20b respectively to expose the first semiconductor. Layer 201. The remaining area shown in Figure 5 is shielded by the second insulating layer 60.

The formation number and/or position of the second insulation layer first openings 601a of the second insulation layer 60 correspond to the first insulation layer first openings 501a of the first insulation layer 50. The number and/or position of the third openings 603a, 603b in the second insulating layer are respectively corresponding to the third openings 503a, 503b in the first insulating layer. The number and/or position of the fourth openings 604a, 604b in the second insulating layer are respectively corresponding to the fourth openings 504a, 504b in the first insulating layer.

The positions of the second openings 602a and 602b of the second insulating layer partially overlap with the positions of the second openings 502a and 502b of the first insulating layer. The number of the second openings 602a and 602b in the second insulating layer is different from the number of the second openings 502a and 502b in the first insulating layer. In one embodiment, a plurality of second openings 602a and 602b of the second insulating layer are respectively located in the second openings 502a and 502b of the first insulating layer. The size of the first openings 502a, 502b of the first insulation layer is larger than the size of any of the plurality of second openings 602a, 602b of the second insulation layer.

In one embodiment, the second insulating layer 60 may be formed of a light-transmissive insulating material. For example, the second insulating layer 60 includes SiOx.

In one embodiment, the second insulating layer 60 may include two or more materials with different refractive indexes alternately stacked to form a Bragg reflector (DBR) structure. For example, the second insulating layer 60 may include stacked SiO2/TiO2 or SiO2/Nb2O5 layers to selectively reflect light of specific wavelengths and increase the light extraction efficiency of the light-emitting element 1 . When the peak emission wavelength of the light-emitting element 1 is λ, the optical thickness of the second insulating layer 60 may be set to an integer multiple of λ/4. The peak wavelength refers to the wavelength with the strongest intensity in the luminescence spectrum of the light-emitting element 1 . The thickness of the second insulating layer 60 may have a deviation of ±30% based on an integral multiple of the optical thickness λ/4.

The second insulating layer 60 is made of non-conductive material, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), and acrylic resin (Acrylic Resin). , cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide) or fluorocarbon polymer Fluorocarbon Polymer, or inorganic materials, such as silicone or glass, or dielectric materials, such as aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgFx).

In one embodiment, the thickness of the second insulating layer 60 may range from 1,000 angstroms to 20,000 angstroms.

In one embodiment, if the material of the second insulating layer 60 is SiO2, TiO2, SiNx, etc., and if the thickness of the second insulating layer 60 is less than 1000 Angstroms, the thinner thickness may affect the insulating properties of the second insulating layer 60. become weaker. Specifically, the second insulating layer 60 is formed on the etched first bevel S1 and the second bevel S2. The second insulating layer 60 formed to cover the bevel also has a specific slope. If the second insulating layer 60 is Thickness less than 1000 angstroms may cause film rupture.

In one embodiment, the material of the second insulating layer 60 is selected from SiO2, TiO2, SiNx and other materials. If the thickness of the second insulating layer 60 exceeds 20,000 angstroms, it will increase the difficulty of selective etching on the second insulating layer 60. . However, the above embodiments do not rule out that other materials with good coverage extensibility or highly selective etching can avoid the above-mentioned problems caused by the second insulating layer 60 being too thin or too thick.

The second insulating layer 60 has a surface, which is a slope relative to the horizontal extension surface of the inner surface 200as or the outer surface 204as of the first semiconductor layer 201 exposed through selective etching. This slope is relative to the horizontal extension surface exposed through selective etching. The inner surface 200as or the outer surface 204as of the first semiconductor layer 201 has an oblique angle, ranging from 10 degrees to 70 degrees.

If the slope angle of the surface of the second insulating layer 60 is less than 10 degrees, the substantial thickness of the second insulating layer 60 will be reduced. Therefore, there may be a problem that it is difficult to ensure insulation properties.

If the inclination angle of the surface of the second insulating layer 60 is greater than 70 degrees, the subsequent insulating layer and metal layer may not be completely covered, resulting in cracking of the film layer.

Figure 7 is a top view of forming an upper electrode, a lower electrode and a connecting electrode according to an embodiment of the present invention. Figures 7A and 7B are partially enlarged views of Figure 7. Figure 8 is a cross-sectional view along the tangent line A-A’ in Figure 7. One or a plurality of connection electrodes 70 are formed between the first light-emitting unit 20a and the second light-emitting unit 20b. One or a plurality of connection electrodes 70 each include a first connection end 701 located on the first recess 2041a of the first light-emitting unit 20a, covering the first opening 601a of the second insulating layer, and through the first opening 601a of the second insulating layer. The first opening 501a of the first insulating layer is electrically connected to the first semiconductor layer 201 of the first light-emitting unit 20a; a second connection terminal 702 is located on the second semiconductor layer 203 of the second light-emitting unit 20b, and is connected through the second insulation The second opening 602b of the layer and the second opening 502b of the first insulating layer are electrically connected to the second semiconductor layer 203 of the second light-emitting unit 20b; and a third connection terminal 703 is located in the trench 21 and between the first connection terminal 701 and the second opening 502b of the first insulation layer. between the two connection terminals 702.

In one embodiment, as shown in FIG. 7A , the first connection end 701 of the connection electrode 70 includes a first connection portion 7011 located in the first opening 601a of the second insulating layer on the first light-emitting unit 20a. The second connection end 702 of the connection electrode 70 includes a second connection portion 7022 located in the second opening 602b of the second insulation layer on the second light emitting unit 20b.

In one embodiment, as shown in FIG. 7A , the first connection portion 7011 of the first connection terminal 701 located in the first opening 601a of the second insulating layer is directly connected to the first semiconductor layer 201 of the first light-emitting unit 20a. In contact, the second connection portion 7022 of the second connection end 702 located in the second opening 602b of the second insulating layer is in contact with the barrier layer, the reflective layer 40 or the contact electrode 30 .

In one embodiment of the present invention, as shown in FIG. 7A, from the top view of the light-emitting element 1, the third connection end 703 includes a third connection first end 7031 that is connected to the first end of the first light-emitting unit 20a. On the three inclined planes S3, and a third connection second end 7032 is connected across the third inclined plane S3 of the second light-emitting unit 20b. The third connection first end 7031 and/or the third connection second end 7032 includes a width of at least 15 μm or more, preferably 30 μm or more, and more preferably 50 μm or more.

In one embodiment, in order to uniformly inject the current from the first light-emitting unit 20a to the second light-emitting unit 20b, the total area of the current that can be injected into the second light-emitting unit 20b is increased, and the cross-sectional current of the second connection terminal 702 is reduced. density. As shown in Figures 7 and 7A, from the top view of the light-emitting element 1, the second opening 602b of the second insulating layer located in the second light-emitting unit 20b includes a first opening area larger than that located in the first light-emitting unit 20a. The first opening 601a of the second insulating layer has a second opening area. The first connecting portion 7011 of the first connecting end 701 includes a first width W1 that is smaller than the second width W2 included in the second connecting portion 7022 of the second connecting end 702 . The third connection second end 7032 of the third connection end 703 includes a third width W3 smaller than the width of the third connection first end 7031, and the third connection first end 7031 and the third connection second end 7032 include The width is a gradual change.

In another embodiment (not shown), in order to uniformly inject the current from the first light-emitting unit 20a to the second light-emitting unit 20b, the total area of the current that can be injected into the second light-emitting unit 20b is increased and the second light-emitting unit 20b is reduced. The cross-sectional current density of the connection terminal 702. The first connecting portion 7011 of the first connecting end 701 includes a first width W1 that is smaller than the second width W2 included in the second connecting portion 7022 of the second connecting end 702. The third width W3 included in the end 7032 is the same as the width included in the first end 7031 of the third connection.

In another embodiment (not shown), in order to distribute the current uniformly between the first connection terminal 701 and the first surrounding portion 204a, the first connection portion 7011 of the first connection terminal 701 includes a first width W1 greater than The second connecting portion 7022 of the second connecting end 702 includes a second width W2, and the third connecting end 703 includes a third width W3 that is greater than the second width W2 included in the second connecting end 702.

In another embodiment (not shown), in order to avoid uneven current density of the connecting electrode 70, the first connecting portion 7011 of the first connecting terminal 701 includes a first width W1 and a second width W1 of the second connecting terminal 702. The second width W2 included in the connecting portion 7022 is the same. The third connecting end 703 includes a third width W3 that is greater than the first width W1 included in the first connecting portion 7011 and/or is greater than the second width W2 included in the second connecting portion 7022 .

In one embodiment, one or a plurality of first upper electrodes 71a are respectively formed in one or a plurality of second openings 602a of the second insulating layer of the first light-emitting unit 20a, and are connected to the second semiconductor layer of the first light-emitting unit 20a. 203 constitutes an electrical connection.

A first lower electrode 72a covers the first inner concave portion 2041a and the plurality of first outer concave portions 2042a of the first light-emitting unit 20a. The first lower electrode 72a is directly connected to the first semiconductor layer 201 located in the first recess 2041a of the first light-emitting unit 20a through one or a plurality of second insulating layer openings 600 and one or a plurality of second insulating layer first openings 601a. get in touch with. The first lower electrode 72a is in direct contact with the first semiconductor layer 201 located in the plurality of first outer recesses 2042a through one or a plurality of third openings 603a of the second insulating layer, and is in direct contact with the first semiconductor layer 201 of the first light emitting unit 20a. Make an electrical connection. The first lower electrode 72a is in direct contact with the first semiconductor layer 201 of the first hole 200a through a fourth opening 604a of the second insulating layer, and is electrically connected to the first semiconductor layer 201 of the first light emitting unit 20a. Viewed from the top view of the light-emitting element 1 , a plurality of second insulating layer openings 600 and a plurality of connection electrodes 70 are alternately arranged with each other. The first lower electrode 72a extends along the second slope S2 of the first light-emitting unit 20a and covers the first semiconductor platform 205a to reflect the light emitted by the active layer 202 of the first light-emitting unit 20a.

The second insulating layer opening 600, the second insulating layer first opening 601a, and the second insulating layer third opening 603a expose the first semiconductor layer 201 and the self-luminous element 1 located on the first surrounding portion 204a of the first light-emitting unit 20a. From a view point of view, the second insulation layer opening 600, the second insulation layer first opening 601a and the second insulation layer third opening 603a include different sizes.

The second insulating layer 60 is located between the first upper electrode 71a and the first lower electrode 72a to avoid contact between the first upper electrode 71a and the first lower electrode 72a to form a short circuit. A portion of the second insulating layer 60 is located under the first lower electrode 72 a extending to cover the first semiconductor platform 205 a to prevent the first lower electrode 72 a from contacting the barrier layer, the reflective layer 40 and/or the contact electrode 30 .

The first surrounding portion 204a on the first light-emitting unit 20a includes a first inner concave portion 2041a and a plurality of first outer concave portions 2042a to form a rectangle and is located around the first light-emitting unit 20a. Compared with the plurality of first outer concave portions 2042a, The recessed portion 2042a and the first inner recessed portion 2041a are adjacent to one side of the trench 21 . From the top view of the light-emitting element 1, as shown in FIG. 7, a plurality of second insulating layer openings 600 and a plurality of second insulating layer first openings 601a are alternately arranged to expose the first light-emitting unit 20a. First semiconductor layer 201. In a direction parallel to one side of the first recessed portion 2041a, the second insulating layer opening 600 includes a width greater than or smaller than the width of the second insulating layer first opening 601a to evenly disperse the current near the connection electrode 70.

As shown in FIG. 7A, the first lower electrode 72a is formed in the opening 600 of the second insulating layer, extends to cover the second insulating layer 60, and is connected to the first connection located on the first opening 601a of the second insulating layer. The first connection part 7011 of the terminal 701.

Viewed from the top view of the light-emitting element 1, as shown in FIG. 7, one or a plurality of first upper electrodes 71a located on the first light-emitting unit 20a are respectively surrounded by first lower electrodes 72a.

In one embodiment, from a top view of the self-luminous element 1, as shown in FIG. 7, one or a plurality of first upper electrodes 71a located on the first light-emitting unit 20a respectively include a first upper surface area larger than the first upper electrode 71a. The lower electrode 72a includes a first lower surface area.

In another embodiment (not shown), from the top view of the light-emitting element 1, one or a plurality of first upper electrodes 71a located on the first light-emitting unit 20a respectively include a first upper surface area smaller than the first lower electrode 71a. Electrode 72a includes a first lower surface area.

In another embodiment (not shown), from the top view of the light-emitting element 1, one or a plurality of first upper electrodes 71a located on the first light-emitting unit 20a respectively include a first upper surface area that is the same as the first upper electrode 71a. The lower electrode 72a includes a first lower surface area.

A second lower electrode 72b covers the second inner concave portion 2041b and the plurality of second outer concave portions 2042b of the second light-emitting unit 20b. The second lower electrode 72b may directly contact the first semiconductor layer 201 located in the second recess 2041b through one or a plurality of second insulating layer openings 600. The second lower electrode 72b can be in direct contact with the first semiconductor layer 201 located in the plurality of second outer recesses 2042b through one or a plurality of third openings 603b of the second insulating layer, and with the first semiconductor layer of the second light emitting unit 20b. 201 constitutes an electrical connection. The second lower electrode 72b can directly contact the first semiconductor layer 201 located in the second hole portion 200b through the fourth opening 604b of the second insulating layer, and form an electrical connection with the first semiconductor layer 201 of the second light-emitting unit 20b. Viewed from the top view of the light-emitting element 1 , a plurality of second insulating layer openings 600 and a plurality of connection electrodes 70 are alternately arranged with each other. The second lower electrode 72b extends along the second slope S2 of the second light-emitting unit 20b and covers the second semiconductor platform 205b to reflect the light emitted by the active layer 202.

As shown in FIG. 8 , the second insulating layer 60 is located below the second lower electrode 72 b to prevent the second lower electrode 72 b from contacting the barrier layer, the reflective layer 40 and/or the contact electrode 30 .

In one embodiment, as shown in Figure 7, from the top view of the light-emitting element 1, the second lower electrode 72b located on the second light-emitting unit 20b includes a second lower surface area larger than that located on the first light-emitting unit 20a. The first lower surface area included in the first lower electrode 72a.

In another embodiment, as shown in Figure 7, from the top view of the self-luminous element 1, the second lower electrode 72b located on the second light-emitting unit 20b includes a second lower surface area larger than that of the first light-emitting unit. The first upper surface area included in each first upper electrode 71a on 20a.

In another embodiment, as shown in Figure 7, from the top view of the self-luminous element 1, the second lower electrode 72b located on the second light-emitting unit 20b includes a second lower surface area larger than that of the first light-emitting unit. The sum of the first upper surface areas included in the plurality of first upper electrodes 71a on 20a.

As shown in FIG. 7 , the trench 21 is located between the first recessed portion 2041a of the first light-emitting unit 20a and the second recessed portion 2041b of the second light-emitting unit 20b. The first insulating layer opening 500 and the second insulating layer opening 600 expose the surface 21s of the substrate 10, the first semiconductor layer 201 located in the first recessed portion 2041a, and the first semiconductor layer 201 located in the second recessed portion 2041b. In other words, the first insulating layer opening 500 and the second insulating layer opening 600 formed adjacent to the trench 21 simultaneously expose the first semiconductor layer 201 of the first recessed portion 2041a and the second recessed portion 2041b. The first lower electrode 72a includes a portion located in the first insulation layer opening 500 and the second insulation layer opening 600, and is in direct contact with the first semiconductor layer 201 of the first recessed portion 2041a. The second lower electrode 72b includes a portion located in the first insulating layer opening 500 and the second insulating layer opening 600, and is in direct contact with the first semiconductor layer 201 of the second recessed portion 2041b. The first lower electrode 72 a and the second lower electrode 72 b are separated from each other by the trench 21 .

As shown in FIG. 7B, the second lower electrode 72b includes one or a plurality of second lower electrode recesses 721b to respectively accommodate one or a plurality of second connection terminals 702; and one or a plurality of second lower electrode protrusions 722b respectively. Located between two adjacent second connection ends 702. The second lower electrode protrusion 722b includes a width W4 that is greater than or less than the width of the second connection end 702 . In order to uniformly inject the current of the second lower electrode 72b into the first semiconductor layer 201 of the second light-emitting unit 20b, the second lower electrode convex portion 722b further includes one or a plurality of second lower electrode extension portions 724b located in the second inner recess. 2041b on. The second lower electrode extension portion 724b extends into the second insulation layer opening 600 and is in direct contact with the first semiconductor layer 201 of the second recessed portion 2041b. In order to increase the area into which current can be injected, the second lower electrode extension portion 724b includes a width W5 that is larger than the width W4 of the second lower electrode protrusion 722b.

In one embodiment, as shown in FIG. 7 , when viewed from a top view of the self-luminous element 1 , the width of the second lower electrode protrusion 722 b is smaller than the width of the second connection end 702 .

In another embodiment (not shown), when viewed from a top view of the self-luminous element 1, the width of the second lower electrode protrusion 722b is greater than the width of the second connection end 702.

As shown in FIG. 7 , from a top view of the self-luminous element 1 , a plurality of second lower electrode protrusions 722b and a plurality of second connection terminals 702 are alternately arranged to inject current into the second light-emitting unit evenly. The first semiconductor layer 201 and the second semiconductor layer 203 of 20b. The plurality of second lower electrode protrusions 722b includes a number different from the number of the plurality of second connection terminals 702. For example, the number of the plurality of second lower electrode protrusions 722b is greater or less than the plurality of second connections. The number contained in end 702.

The first lower electrode 72a located on the first light-emitting unit 20a is directly connected to the outer surface 204as of the first semiconductor layer 201 of the first light-emitting unit 20a. The second lower electrode 72b located on the second light-emitting unit 20b is directly connected to the outer surface 204bs of the first semiconductor layer 201 of the second light-emitting unit 20b. As shown in FIG. 8, when the first lower electrode 72a or the second lower electrode 72b completely covers the outer surface 204as or the outer surface 204bs of the first semiconductor layer 201, the first lower electrode 72a or the second lower electrode 72b respectively includes the first lower electrode 72a or the second lower electrode 72b. The lower electrode outer side wall 72as and a second lower electrode outer side wall 72bs are directly connected to the third slope S3 of the first semiconductor layer 201. In one embodiment, when the first lower electrode 72a or the second lower electrode 72b partially covers the outer surface 204as or the outer surface 204bs of the first semiconductor layer 201, the first lower electrode 72a or the second lower electrode 72b includes The lower electrode outer wall 72as or the second lower electrode outer wall 72bs is separated from the third slope S3 of the first semiconductor layer 201 by a distance to partially expose the outer surface 204as or the outer surface 204bs of the first semiconductor layer 201 (not shown in the figure) .

In one embodiment, the first upper electrode 71a located on the first light-emitting unit 20a has an inclined side surface to reduce the risk of peeling off the reflective layer 40 or the barrier layer, and to increase the coverage of subsequent laminations. The first lower electrode 72a located on the first light-emitting unit 20a and the second lower electrode 72b located on the second light-emitting unit 20b respectively have an inclined side surface to reduce the risk of peeling from the first semiconductor layer 201 and increase the subsequent stacking time. coverage. The inclined side surface of the first upper electrode 71a has an included angle between 30 degrees and 75 degrees with the surface of the reflective layer 40 or the barrier layer. The inclined side surface of the first lower electrode 72a and/or the second lower electrode 72b and the surface of the first semiconductor layer 201 have an included angle between 30 degrees and 75 degrees.

The first upper electrode 71a, the first lower electrode 72a and/or the second lower electrode 72b include metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni) or platinum (Pt) and other metals or alloys of the above materials. The first upper electrode 71a, the first lower electrode 72a and/or the second lower electrode 72b may be composed of a single layer or multiple layers. For example, the first upper electrode 71a, the first lower electrode 72a and/or the second lower electrode 72b may include a Ti/Au layer, a Ti/Pt/Au layer, a Cr/Au layer, a Cr/Pt/Au layer, or Ni/Au. layer, Ni/Pt/Au layer or Cr/Al/Cr/Ni/Au layer.

The thickness of the first upper electrode 71a, the first lower electrode 72a and/or the second lower electrode 72b is preferably 0.5 μm to 3.5 μm.

In one embodiment, the first upper electrode 71a includes a top surface lower than the top surface of the first lower electrode 72a. In other words, there is a step difference between the top surface of the first upper electrode 71a and the top surface of the first lower electrode 72a, where the step difference is between 2000 angstroms and 20000 angstroms.

In one embodiment, the top surface of the first lower electrode 72a and the top surface of the second lower electrode 72b include a step difference, wherein the step difference is less than 2000 angstroms, preferably less than 1000 angstroms, and more preferably less than 500 angstroms.

In one embodiment, the top surface of the first lower electrode 72a and the top surface of the second lower electrode 72b are substantially flush.

Figure 9 is a top view of forming a third insulating layer according to an embodiment of the present invention. Figure 10 is a cross-sectional view along the tangent line A-A’ in Figure 9. A third insulating layer 80 is formed on the substrate 10 and each light-emitting unit 20 , and one or more first openings 801 of the third insulating layer and one or more first openings 801 are formed on each light-emitting unit 20 by selective etching. The second opening 802 of the three insulation layers. One or a plurality of first openings 801 of the third insulating layer respectively expose one or a plurality of first upper electrodes 71a of the first light-emitting unit 20a. One or a plurality of second openings 802 in the third insulating layer expose the second lower electrode 72b of the second light-emitting unit 20b. The remaining area is shielded by the third insulating layer 80 .

In one embodiment, as shown in FIG. 9 , from the top view of the light-emitting element 1 , one or a plurality of the first openings 801 of the third insulating layer located in the first light-emitting unit 20 a respectively include a width smaller than that located in the second One or a plurality of the third insulating layer second openings 802 of the light-emitting unit 20b include a width, wherein the plurality of third insulating layer first openings 801 include a width that is the same or different from each other, and/or a plurality of third insulating layer first openings 801 include a width. The widths of the second openings 802 of the insulation layer may be the same or different from each other.

In another embodiment (not shown), from the top view of the self-luminous element 1, one or a plurality of the first openings 801 of the third insulating layer located in the first light-emitting unit 20a respectively include a width larger than that located in the second light-emitting unit 20a. One or a plurality of the third insulating layer second openings 802 of the unit 20b include a width, wherein the plurality of third insulating layer first openings 801 include a width that may be the same or different from each other, and/or a plurality of third insulating layers The second openings 802 of the layers may have the same or different widths from each other.

In one embodiment, the light-emitting element includes the cutting line 10d located at the outermost side of the light-emitting element 1 . The third insulating layer 80 covers the exposed upper surface 10s of the substrate 10. The third insulating layer 80 includes a third insulating sidewall 80s that is directly connected to the outer sidewall S of the substrate 10 or separated by a distance to expose a portion of the substrate 10. Surface 10s.

In another embodiment, the third slope S3 of the first semiconductor layer 201 is directly connected to an outer wall of the substrate 10 . The third insulating layer 80 covers the outer surface 204as or the outer surface 204bs of the first semiconductor layer 201, wherein the third insulating sidewall 80s included in the third insulating layer 80 is directly connected to the third slope S3 of the first semiconductor layer 201 or is The outer surface 204as or the outer surface 204bs of the first semiconductor layer 201 is partially exposed at a distance.

In one embodiment, the third insulating layer 80 may be formed of an insulating material with light transmittance. For example, the third insulating layer 80 includes SiO _x .

In another embodiment, the third insulating layer 80 may include two or more materials with different refractive indexes alternately stacked to form a Bragg reflector (DBR) structure. In one embodiment, the third insulating layer 80 may include stacked SiO ₂ /TiO ₂ or SiO ₂ /Nb ₂ O ₅ layers to selectively reflect light of specific wavelengths and increase the light extraction efficiency of the light-emitting element. When the peak emission wavelength of the light-emitting element 1 is λ, the optical thickness of the third insulating layer 80 may be set to an integer multiple of λ/4. The peak wavelength refers to the wavelength with the strongest intensity in the luminescence spectrum of the light-emitting element 1 . The thickness of the third insulating layer 80 may have a deviation of ±30% based on an integer multiple of λ/4.

In one embodiment, the third insulating layer 80 is formed of non-conductive material, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), Acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide ( Polyetherimide) or fluorocarbon polymer (Fluorocarbon Polymer), or inorganic materials, such as silicone or glass, or dielectric materials, such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ).

In one embodiment, the thickness of the third insulating layer 80 may range from 2,000 angstroms to 60,000 angstroms.

In one embodiment, the material of the third insulating layer 80 is selected from SiO ₂ , TiO ₂ , SiN _x and other materials. If the thickness of the third insulating layer 80 is less than 2000 angstroms, the thinner thickness may cause the Insulating properties become weaker. Specifically, the third insulating layer 80 is formed on the etched first bevel S1 and the second bevel S2. The third insulating layer 80 formed to cover the bevel also has a specific slope. If the third insulating layer 80 is Thickness less than 2000 Angstroms may cause film rupture.

In one embodiment, if the material of the third insulating layer 80 is SiO ₂ , TiO ₂ , _SiN Difficulty of etching. However, the above embodiments do not rule out that other materials with good coverage extensibility or highly selective etching can avoid the above-mentioned problems caused by the first insulating layer 50 being too thin or too thick.

The third insulating layer 80 includes a third insulating sidewall 80s, which is horizontal relative to the inner surface 200as, 200bs, the outer surface 204as, 204bs of the first semiconductor layer 201 exposed through selective etching or the exposed upper surface 10s of the substrate 10 The extended surface is an inclined surface, which is a horizontal extended surface relative to the inner surfaces 200as, 200bs, outer surfaces 204as, 204bs of the first semiconductor layer 201 exposed through selective etching or the upper surface 10s exposed by the substrate 10. In other words, it has a bevel angle between 10 degrees and 70 degrees.

In one embodiment, if the slope angle of the third insulating sidewall 80s of the third insulating layer 80 is less than 10 degrees, the substantial thickness of the third insulating layer 80 will be reduced. Therefore, there may be a problem that it is difficult to ensure insulation properties.

In one embodiment, if the inclination angle of the third insulating sidewall 80s of the third insulating layer 80 is greater than 70 degrees, the subsequent insulating layer and the metal layer may not be completely covered, resulting in cracking of the film layer.

As shown in Figures 9 and 10, the formation positions of one or more first openings 801 of the third insulating layer on the first light-emitting unit 20a respectively correspond to one or more second openings 602a of the second insulating layer. , and overlaps with the second opening 502a of the first insulation layer.

As shown in Figures 9 and 10, one or more second openings 802 of the third insulating layer located on the second light-emitting unit 20b overlap with the second openings 502b of the first insulating layer located below, and are overlapped with the second openings 802 of the first insulating layer located below. The second openings 602b of the insulation layer do not overlap each other.

Figure 11 is a top view of forming a first electrode pad and a second electrode pad according to an embodiment of the present invention. Figure 12 is a cross-sectional view along the tangent line A-A' of Figure 11. Figure 13 is a cross-sectional view along the tangent line B-B' of Figure 11. Figure 14 is a cross-sectional view along the tangent line C-C' of Figure 11. The light-emitting element 1 includes one or a plurality of first electrode pads 901 to respectively cover one or a plurality of the first openings 801 of the third insulating layer, and to respectively contact one or a plurality of the first upper electrodes 71a. The first electrode pad 901 is electrically connected to the second semiconductor layer 203 on the first light-emitting unit 20a through the reflective layer 40 and/or the contact electrode 30.

The light-emitting element 1 includes one or a plurality of second electrode pads 902 respectively covering one or a plurality of the second openings 802 of the third insulating layer and contacting the second lower electrode 72b. The second electrode pad 902 is electrically connected to the first semiconductor layer 201 on the second light emitting unit 20b through the second lower electrode 72b formed in the second hole part 200b and the second surrounding part 204b.

The current injected through the first electrode pad 901 and the second electrode pad 902 connects the first connection terminal 701 and the second connection terminal 702 of the electrode 70 so that the first light-emitting unit 20a and the second light-emitting unit 20b are connected in series.

The upper surface of the first electrode pad 901 or the second electrode pad 902 may be planar or non-planar. When the upper surface of the first electrode pad 901 or the second electrode pad 902 is non-planar, the upper surface of the first electrode pad 901 or the second electrode pad 902 has a first opening 801 of the third insulating layer and a third opening of the third insulating layer. The surface contours of the two openings 802 correspond to surface contours, such as strip-shaped, circular or stepped surfaces. As shown in FIG. 11 , the upper surface of the first electrode pad 901 or the second electrode pad 902 may include at least one recessed portion and at least one protruding portion surrounding the recessed portion. The position of the recessed portion corresponds to the position where the first opening 801 of the third insulating layer and the second opening 802 of the third insulating layer are formed, and the recessed portion is located in the first opening 801 of the third insulating layer and the second opening 802 of the third insulating layer. . The protruding portion is located outside the first opening 801 of the third insulating layer and the second opening 802 of the third insulating layer, and the protruding portion is located on an upper surface of the third insulating layer. There is a stepped surface between the protruding part and the recessed part, wherein the stepped surface includes a step difference between 200 angstroms and 60,000 angstroms, preferably between 1,000 angstroms and 30,000 angstroms, and more preferably between 2,000 angstroms and 20,000 angstroms. between. The recessed portion and the protruding portion may be formed in a circular shape or a rectangular shape as shown in FIG. 1 .

In another embodiment of the present invention (not shown), the first electrode pad 901 and the second electrode pad 902 are a thin pad structure, each including a thickness smaller than that of the third insulating structure 80 . The first electrode pad 901 and the second electrode pad 902 include metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn) , nickel (Ni), platinum (Pt) and other metals or alloys of the above materials. The first electrode pad 901 and the second electrode pad 902 may be composed of a single layer or multiple layers. For example, the first electrode pad 901 and the second electrode pad 902 may include a Ti/Au layer, a Ti/Pt/Au layer, a Cr/Au layer, a Cr/Pt/Au layer, a Ni/Au layer, and a Ni/Pt/Au layer. Or Cr/Al/Cr/Ni/Au layer.

In one embodiment of the present invention, the first electrode pad 901 includes a dimension that is the same as or different from a dimension of the second electrode pad 902, and the dimension may be a width or an area. For example, the top view area of the first electrode pad 901 or the second electrode pad 902 may be more than 0.8 times and less than 1 times the value obtained by adding the top view areas of the first electrode pad 901 and the second electrode pad 902 .

In one embodiment of the present invention (not shown), the first electrode pad 901 or the second electrode pad 902 respectively includes an inclined side surface, so the side cross-sectional area of the first electrode pad 901 or the second electrode pad 902 can be along the The thickness direction changes. For example, the side view cross-sectional area of the side of the first electrode pad 901 or the second electrode pad 902 that is far away from the semiconductor stack is smaller than the side view of the other side of the first electrode pad 901 or the second electrode pad 902 that is closer to the semiconductor stack. The cross-sectional area is small.

In one embodiment of the present invention (not shown), when the light-emitting element 1 is mounted on the packaging substrate in the form of a flip chip, in order to increase the contact area between the first electrode pad 901 and the second electrode pad 902 and the packaging substrate, the The side cross-sectional area of one side of the first electrode pad 901 or the second electrode pad 902 of the semiconductor stack is larger than the side cross-sectional area of the other side of the first electrode pad 901 or the second electrode pad 902 of the semiconductor stack. .

The first electrode pad 901 or the second electrode pad 902 has a thickness between 1 and 100 μm, preferably between 1.5 and 6 μm.

There is a gap between the first electrode pad 901 and the second electrode pad 902. The gap includes a shortest distance of about 10 μm or more, and a longest distance of about 250 μm or less. Within the above range, by reducing the distance between the first electrode pad 901 and the second electrode pad 902, the top view area of the first electrode pad 901 and the second electrode pad 902 can be increased, thereby improving the heat dissipation of the light-emitting element 1. efficiency, and avoid short circuit between the first electrode pad 901 and the second electrode pad 902 .

Figure 15 is a schematic diagram of a light emitting device 2 according to an embodiment of the present invention. The light-emitting element 1 in the aforementioned embodiment is mounted on the first pad 511 and the second pad 512 of the packaging substrate 51 in the form of a flip chip. The first gasket 511 and the second gasket 512 are electrically insulated by an insulating portion 53 containing insulating material. In flip-chip mounting, the side of the growth substrate opposite to the surface where the electrode pad is formed is set upward as the main light extraction surface. In order to increase the light extraction efficiency of the light-emitting device 2, a reflective structure 54 can be provided around the light-emitting element 1.

Figure 16 is a schematic diagram of a light emitting device 3 according to an embodiment of the present invention. The light-emitting device 3 is a bulb including a lampshade 602, a reflector 604, a light-emitting module 610, a lamp holder 612, a heat sink 614, a connecting part 616 and an electrical connection component 618. The light-emitting module 610 includes a carrying part 606, and a plurality of light-emitting units 608 located on the carrying part 606, where the plurality of light-emitting bodies 608 can be the light-emitting elements 1 or the light-emitting devices 2 in the aforementioned embodiments.

Each embodiment listed in the present invention is only used to illustrate the present invention and is not intended to limit the scope of the present invention. Any obvious modifications or changes made by anyone to the present invention shall not depart from the spirit and scope of the present invention.

1:Light-emitting component

2:Lighting device

3:Lighting device

10:Substrate

10d: cutting lane

10s: upper surface

20:Light-emitting unit

20a: First light emitting unit

20b: Second light-emitting unit

21:Ditch

21s: surface

200: Hole

200a: First hole part

200as: inner surface

200b: Second hole part

200bs: inner surface

201: First semiconductor layer

202:Active layer

203: Second semiconductor layer

204: Surround Department

204a: First surround part

204as: outer surface

2041a: First inner recess

2042a: First outer recess

204b:Second surround part

204bs:Outer surface

2041b: First inner recess

2042b: First outer concave part

205:Semiconductor Platform

205a: First semiconductor platform

205b: Second semiconductor platform

30: Contact electrode

40: Reflective layer

50: First insulation layer

500: First insulation layer opening

501a: first opening of first insulation layer

502a, 502b: second opening of first insulation layer

503a, 503b: The third opening of the first insulation layer

504a, 504b: The fourth opening of the first insulation layer

60: Second insulation layer

600: Second insulation layer opening

601a: first opening of the second insulation layer

602a, 602b: second opening of the second insulation layer

603a, 603b: The third opening of the second insulation layer

604a, 604b: The fourth opening of the second insulation layer

70: Connect the electrode

701: First connection end

7011: First connection part

702: Second connection terminal

7022: Second connection part

703: Third connection terminal

7031: The first end of the third connection

7032: Third connection second end

71a: First upper electrode

72a: First lower electrode

72as: outer wall of first lower electrode

72b: Second lower electrode

72bs: Second lower electrode outer wall 721b: Second lower electrode recess

722b: Second lower electrode protrusion

724b: Second lower electrode extension

80:Third insulation layer

801: The first opening of the third insulation layer

802: The second opening of the third insulation layer

80s: Third insulating side wall

901: First electrode pad

902: Second electrode pad

51:Package substrate

511:First gasket

512:Second gasket

53:Insulation Department

54: Reflective structure

602:Lampshade

604:Reflector

606: Bearing part

608: Luminous body

610:Light-emitting module

612: Lamp holder

614:Heat sink

616:Connection Department

618: Electrical connection components

b1: lower surface

t1: upper surface

S: lateral wall

S1: first slope

S2: Second slope

S3: The third slope

FIG. 1 is a top view of forming a trench and a hole in a semiconductor stack according to an embodiment of the present invention.

Figure 2 is a cross-sectional view along the tangent line A-A’ of Figure 1.

Figure 3 is a top view of a contact electrode and a reflective layer formed on a semiconductor stack according to an embodiment of the present invention.

Figure 4 is a cross-sectional view along the tangent line A-A’ in Figure 3.

Figure 5 is a top view of forming a first insulating layer and a second insulating layer according to an embodiment of the present invention.

Figure 6 is a cross-sectional view along the tangent line A-A’ in Figure 5.

FIG. 7 is a top view of an upper electrode, a lower electrode and a connecting electrode formed on a semiconductor stack according to an embodiment of the present invention.

Figure 7A is an enlarged view of part of Figure 7.

Figure 7B is an enlarged view of part of Figure 7.

Figure 8 is a cross-sectional view along the tangent line A-A’ in Figure 7.

Figure 9 is a top view of a third insulating layer formed on a semiconductor stack according to an embodiment of the present invention.

Figure 10 is a cross-sectional view along the tangent line A-A’ in Figure 9.

FIG. 11 is a top view of a first electrode pad and a second electrode pad formed on a semiconductor stack according to an embodiment of the present invention.

Figure 12 is a cross-sectional view along the tangent line A-A' of Figure 11.

Figure 13 is a cross-sectional view along the tangent line B-B' of Figure 11.

Figure 14 is a cross-sectional view along the tangent line C-C' of Figure 11.

Figure 15 is a schematic diagram of a light emitting device 2 according to an embodiment of the present invention.

Figure 16 is a schematic diagram of a light emitting device 3 according to an embodiment of the present invention.

without

1:Light-emitting component

10:Substrate

10s: upper surface

20:Light-emitting unit

20a: First light emitting unit

20b: Second light-emitting unit

21:Ditch

21s: Surface

200: Hole

200as: inner surface

200bs: inner surface

201: First semiconductor layer

202:Active layer

203: Second semiconductor layer

2041a: First inner recess

2041b: Second concave part

2042a: First outer recess

2042b: Second outer concave part

205:Semiconductor Platform

205a: First semiconductor platform

205b: Second semiconductor platform

30: Contact electrode

40: Reflective layer

50: First insulation layer

502a: second opening of first insulation layer

502b: second opening of first insulation layer

60: Second insulation layer

602a: Second opening of the second insulation layer

602b: Second opening of the second insulation layer

70: Connect the electrode

701: First connection end

702: Second connection terminal

703: Third connection terminal

71a: First upper electrode

72a: First lower electrode

72b: Second lower electrode

80:Third insulation layer

801: The first opening of the third insulation layer

802: The second opening of the third insulation layer

901: First electrode pad

902: Second electrode pad

Claims (10)

A light-emitting component, including: A substrate includes a surface; A first light-emitting unit and a second light-emitting unit are located on the substrate. The first light-emitting unit and the second light-emitting unit each include a first semiconductor layer, a second semiconductor layer, and an active layer located on the first semiconductor layer. between the second semiconductor layer and the second semiconductor layer; A trench is located between the first light-emitting unit and the second light-emitting unit and exposes the surface of the substrate; A first surrounding part includes a first recessed part located on the first light-emitting unit, the first surrounding part surrounds the first light-emitting unit and exposes the first semiconductor layer located on the first light-emitting unit; A second surrounding part includes a second recessed part located on the second light-emitting unit, the second surrounding part surrounds the second light-emitting unit and exposes the first semiconductor layer located on the second light-emitting unit, wherein the An inner recess and the second inner recess are located on two opposite sides of the ditch; Each of the plurality of connection electrodes includes a first connection end located on the first recessed portion and electrically connected to the first semiconductor layer of the first light-emitting unit, and a second connection end located on the second light-emitting unit and electrically connected to the first light-emitting unit. The second semiconductor layer of the two light-emitting units and a third connection terminal are located in the trench to connect the first connection terminal and the second connection terminal; A first lower electrode is located on the first surrounding portion and the second semiconductor layer of the first light-emitting unit; and A second lower electrode includes a plurality of second lower electrode convex portions located on the second surrounding portion and contacting the first semiconductor layer located on the second concave portion, wherein when viewed from above one of the light-emitting elements, a plurality of The connecting electrodes and the plurality of second lower electrode protrusions are arranged alternately with each other. The light-emitting element as described in item 1 of the patent application further includes a first upper electrode located on the second semiconductor layer of the first light-emitting unit, wherein from the top view of the light-emitting element, the first upper electrode The electrodes are surrounded by the first lower electrode. The light-emitting element described in item 2 of the patent application further includes an insulating layer including a first opening located below the first connection end and a second opening located below the second connection end, wherein the insulating layer The first opening is covered by the first lower electrode, and from a side view of the light-emitting element, part of the insulating layer is located between the second semiconductor layer and the first lower electrode, In the light-emitting element described in claim 3 of the patent application, when viewed from a top view of the light-emitting element, the second opening includes an opening area that is larger than an opening area of the first opening. As for the light-emitting element described in claim 4 of the patent application, the insulating layer further includes a plurality of third openings located on the second surrounding portion and covering the second lower electrode. The light-emitting element described in item 2 of the patent application further includes a first electrode pad located on the first light-emitting unit and in contact with the first upper electrode, and a second electrode pad located on the second light-emitting unit and in contact with the second lower electrode. As in the light-emitting element described in claim 4 of the patent application, the second lower electrode includes a plurality of second lower electrode recesses to accommodate the plurality of connection electrodes. As for the light-emitting element described in claim 1 of the patent application, the second connecting end includes a second width that is greater than the first width included in the first connecting end. As for the light-emitting element described in claim 1 of the patent application, the second connection end includes a second width that is smaller than the first width included in the first connection end. As for the light-emitting element described in claim 1 of the patent application, the second connecting end includes a second width that is the same as the first width included in the first connecting end.