TW202339305A - Optoelectronic semiconductor device - Google Patents

Abstract

An optoelectronic semiconductor device is provided, including: a base; a stack of semiconductor layer located on the base; an adhesive layer located between the base and the stack of semiconductor layer; and a release layer located between the adhesive layer and the base and in direct contact with the base. The release layer includes an inorganic insulating material and has a thickness of 30Å to 1000Å.

Description

Optoelectronic semiconductor components

The present disclosure relates to an optoelectronic semiconductor device, and in particular to a micro optoelectronic semiconductor device.

Semiconductor components are used in a wide range of applications, and research and development on related materials continues. For example, III-V semiconductor materials containing Group III and Group V elements can be used in various optoelectronic semiconductor components such as light-emitting wafers (such as light-emitting diodes or laser diodes), light-absorbing wafers (photodetectors) or solar cells) or non-luminous wafers (such as power components of switches or rectifiers), which can be used in lighting, medical, display, communications, sensing, power systems and other fields.

With the advancement of technology, the size of optoelectronic semiconductor components is gradually becoming smaller. In recent years, due to breakthroughs in the production size of light-emitting diodes (LEDs), micro-LED displays, which are produced by arranging light-emitting diodes in an array, are gradually gaining attention in the market. . Compared with organic light-emitting diode (OLED) displays, micro-light-emitting diode displays are more power-saving, have better reliability, longer service life and better contrast performance , and can be viewed in sunlight. With the development of science and technology, there are still many technical research and development needs for optoelectronic semiconductor components. Although existing optoelectronic semiconductor devices have generally met various needs, they are not satisfactory in all aspects and require further improvement.

Some embodiments of the present disclosure provide an optoelectronic semiconductor device, including: a substrate; a semiconductor stack located on the substrate; an adhesive layer located between the substrate and the semiconductor stack; and a dissociation layer located between the adhesive layer and the substrate and with the substrate Direct contact; where the dissociation layer includes inorganic insulating materials and has a thickness of 30Å to 1000Å.

The following disclosure provides numerous embodiments, or examples, for implementing different elements of the provided subject matter. Specific examples of each component and its configuration are described below to simplify the description of the embodiments of the present disclosure. Of course, these are only examples and are not intended to limit the embodiments of the present disclosure. For example, if the description mentions that a first element is formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, or may include an additional element formed between the first and second elements. , so that they are not in direct contact. In addition, embodiments of the present disclosure may use repeated element symbols in various examples. Such repetition is for the sake of simplicity and clarity and is not intended to represent the relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially related terms may be used here, such as "under", "below", "below", "above", "above", and similar terms may be used here so that Describe the relationship between one element or component and other elements or components as shown in the figure. These spatial terms are intended to cover the various orientations of the device in use or operation, in addition to the orientation depicted in the diagrams. For example, if the device in the picture is turned over, elements described as "lower than" or "beneath" other elements or features would then be described as "above" the other elements or features. Therefore, the exemplary term "below" can have both the orientations of "above" and "below". When the device is rotated 90° or at any other orientation, the spatially relative descriptors used herein may be interpreted similarly to the rotated orientation.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It should be understood that these terms, such as those defined in commonly used dictionaries, should be interpreted to have a meaning consistent with the relevant technology and the background or context of the present disclosure, and should not be interpreted in an idealized or overly formal manner. Unless otherwise defined in the embodiments of this disclosure.

The composition of each layer, dopant, and defects included in the semiconductor device disclosed in this disclosure can be analyzed by any suitable method, such as: secondary ion mass spectrometer (SIMS), transmission electron microscope (transmission electron microscopy (TEM) or scanning electron microscope (SEM); the thickness of each layer can also be analyzed by any suitable method, such as: transmission electron microscopy (TEM) or scanning electron microscope (scanning electron microscope, SEM).

Generally speaking, micro-LEDs can be mass-transferred through a laser-liftoff (LLO) process to separate the semiconductor stack of the micro-LEDs from the substrate. There needs to be a sacrificial layer between the semiconductor stack and the substrate in the micro light-emitting diode as a sacrificial layer for the laser lift-off process. Since forming the ohmic contact structure during the micro light-emitting diode process requires a high-temperature process (for example: 300°C to 500°C), the sacrificial layer needs to be a material that can undergo a laser lift-off process and can withstand the high-temperature process. Conventional technology Semiconductor materials (such as GaN) or organic materials (such as benzocyclobutene (BCB)) are commonly used to bond the semiconductor stack to the substrate and serve as dissociators for subsequent laser-liftoff (LLO) processes. layer.

However, when the dissociation layer is a semiconductor material, epitaxial defects often occur during the crystal growth period, resulting in a low bonding process yield. When the dissociation layer is an organic material, it is often unable to withstand high temperatures, resulting in poor quality of the high-temperature alloy process. The rate is not high. According to some embodiments of the present disclosure, the dissociation layer formed by the inorganic insulating material can be processed by laser lift-off and can withstand high-temperature processes. In addition, no epitaxial defects are generated, so the yield of the bonding process can be improved. This further improves the luminous efficiency of optoelectronic semiconductor components.

Referring to Figures 1A and 1B together, Figure 1A is a top view of an optoelectronic semiconductor element according to an embodiment of the present disclosure, and Figure 1B is an optoelectronic semiconductor element 10 along A-A of Figure 1A 'Profile of the line segment. In this embodiment, the optoelectronic semiconductor device 10 includes a substrate 100, a dissociation layer 200, an adhesive layer 300 and a semiconductor stack 400. As shown in Figure 1B, the semiconductor stack 400 is located on the substrate 100, the adhesive layer 300 is located between the semiconductor stack 400 and the substrate 100, and the dissociation layer 200 is located between the adhesive layer 300 and the substrate 100 and directly contacts the substrate 100. In other words , the semiconductor stack 400 and the substrate 100 are bonded to each other through the adhesive layer 300 and the dissociation layer 200 .

It should be understood that when the optoelectronic semiconductor element 10 is formed, it is first formed on another growth substrate (not shown) by, for example, metal-organic chemical vapor deposition (MOCVD), hydride vapor deposition, etc. Epitaxy (hydride vapor phase epitaxy, HVPE), molecular beam epitaxy (MBE) or liquid-phase epitaxy (LPE), vapor phase epitaxy (VPE), or other suitable epitaxial growth processes to form the semiconductor stack 400, and then the growth substrate is inverted and bonded to the substrate 100 through the adhesive layer 300, and then the growth substrate is removed. Therefore, in various embodiments of the present disclosure, the upper and lower order of elements in various schematic diagrams does not represent their actual formation order.

In some embodiments, as shown in FIG. 1B , the semiconductor stack 400 includes a first semiconductor structure 410 , a second semiconductor structure 420 , and an active region 430 . The active region 430 is located between the first semiconductor structure 410 and the second semiconductor structure 420 . between two semiconductor structures 420. The semiconductor stack 400 can be divided into a first platform portion 400A, a second platform portion 400C, a first platform portion 400B, a second platform portion 400D, and a third platform portion 400E. The first platform part 400B is located between the first platform part 400A and the second platform part 400C. The second platform part 400D and the third platform part 400E are respectively located on the opposite sides of the first platform part 400B. The first platform part 400A is located on the third platform part 400B. Between the first platform part 400B and the second platform part 400D, the second high platform part 400C is located between the first platform part 400B and the third platform part 400E. Viewed from a top view, the first high platform portion 400A and the second high platform portion 400C are surrounded by a platform portion (for example: the first platform portion 400B, and/or the second platform portion 400D, and/or the third platform portion 400E), and the A platform part 400B is surrounded by a first high platform part 400A and a second high platform part 400C. The top surface 400a1 of the first platform portion 400A and the top surface 400a1 of the second platform portion 400C are coplanar, and the top surface 400a2 of the first platform portion 400B is lower than the active area 430. The thickness of the plateau portions 400A and 400C is greater than the thickness of the platform portions 400B, 400D and 400E. In other embodiments, the second semiconductor structure 420 has a lower surface 420a away from the first semiconductor structure 410, and the lower surface 420a has a roughened structure (not shown). The roughened structure may be regular roughening or irregular roughening. Thereby, the light extraction efficiency of the optoelectronic semiconductor element 10 is increased.

In some embodiments, the substrate 100 is a transparent material, and "transparent" as described herein means that the material has high transmittance for the wavelength used in the subsequent laser lift-off process. Specifically, the substrate 100 has a transmittance of 80% to 99.99% for a wavelength of 200 nm to 700 nm, for example, the transmittance is greater than 95%. The substrate 100 may be sapphire, glass, epoxy, quartz, acrylic resin, or other transparent materials. In yet another embodiment, the substrate 100 is sapphire. In one embodiment, the substrate 100 has a first upper surface 100a facing the semiconductor stack 400, the adhesive layer 300 includes a second upper surface 300a facing the semiconductor stack 400, and the first upper surface 100a includes a patterned pattern ( (not shown), so that the dissociation layer 200 can have a corresponding surface topography according to the pattern pattern of the substrate 100, and the second upper surface 300a is a flat surface. The semiconductor stack 400 can be increased through the flat second upper surface 300a. Adhesion to the substrate 100.

The above-mentioned optoelectronic semiconductor device 10 can be a micro light emitting diode (Micro LED), and has a length L and a width W in a top view (FIG. 1A). In other words, the semiconductor stack 400 (or the second semiconductor structure 420) has length L and width W. The above-mentioned length L is not greater than 150 microns, for example, it is 20 microns to 150 microns, for example: 20 microns to 60 microns, or 60 microns to 150 microns. The above-mentioned width W is not greater than 100 microns, for example, 10 microns to 100 microns, for example: 10 microns to 30 microns, 30 microns to 75 microns.

The dissociation layer 200 is an inorganic insulating material that can withstand subsequent high-temperature processes (350°C to 500°C) and has a band gap between 3eV and 6eV, for example: 3.5eV to 5.5eV, 4eV to 5.2eV. Thereby, the dissociation layer 200 has a high absorption rate for the UV light band (for example: 200nm to 400nm) used in the laser lift-off process, so as to effectively separate the substrate 100 and the semiconductor stack 400 without damaging the semiconductor stack during the separation process. 400 causes damage, thereby improving process yield. Specifically, the above-mentioned dissociation layer 200 material may have an absorption coefficient greater than or equal to 10 ² cm ^-1 for a wavelength of 200 nm to 300 nm, such as an absorption coefficient of 1x10 ² cm ^-1 to 1x10 ⁵ cm ^-1 . In this embodiment, the dissociation layer 200 may be silicon nitride (SiN _x ), aluminum nitride (AlN), silicon oxynitride (SiNO), indium tin oxide glass (ITO), or a combination thereof. In some embodiments, the dissociation layer 200 may be an amorphous material.

In some embodiments, as shown in Figure 1B, the dissociation layer 200 has a thickness T ranging from 30Å to 1000Å, such as 50Å to 500Å, 60Å to 300Å, or 80Å to 200Å. If the thickness T of the dissociation layer 200 is less than 30Å, it may be difficult to control the uniformity of the process, resulting in a lower bonding yield. If the thickness T of the dissociation layer 200 is greater than 1000Å, the subsequent separation process of the semiconductor stack 400 and the substrate 100 may not be effectively separated, and part of the dissociation layer 200 may remain in the semiconductor stack 400 after the laser lift-off process. on, causing component damage and affecting yield.

In some embodiments, since the dissociation layer 200 of the present disclosure is an inorganic insulating material, a deposition process can be used to form the dissociation layer 200 on the substrate 100 and avoid the aforementioned epitaxy caused when the dissociation layer is a semiconductor material. Defects in turn lead to lower yields in the bonding process. The above deposition processes include chemical vapor deposition (CVD), subatmospheric chemical vapor deposition (SACVD), flowable chemical vapor deposition (FCD), spin coating, and/or other suitable processes.

In some embodiments, the first and second semiconductor structures 410 and 410 may be formed by in-situ doping during epitaxial growth and/or by implanting with dopants after epitaxial growth. Doping of the second semiconductor structure 420. The first semiconductor structure 410 may include a first dopant to have a first conductivity type, and the second semiconductor structure 420 may include a second dopant to have a second conductivity type. The first semiconductor structure 410 and the second semiconductor structure 420 have different conductivity types, that is, the first conductivity type and the second conductivity type are different. The first conductivity type is, for example, p-type and the second conductivity type is, for example, n-type. Alternatively, the first conductivity type is, for example, n-type and the second conductivity type is, for example, p-type. When the optoelectronic semiconductor element is a light-emitting element, under operation, the first semiconductor structure 410 and the second semiconductor structure 420 respectively provide holes and electrons or provide electrons or holes respectively to combine in the active region 430 to emit light. In an embodiment, the first dopant or the second dopant may be magnesium (Mg), zinc (Zn), silicon (Si), carbon (C) or tellurium (Te).

In the embodiment of the present disclosure, the first semiconductor structure 410, the second semiconductor structure 420, and the active region 430 may include III-V semiconductor materials, such as aluminum (Al), gallium (Ga), arsenic (As), phosphorus ( P) or indium (In). Specifically, in the embodiment of the present disclosure, the III-V group semiconductor material may be a binary compound semiconductor (such as GaAs, GaP, or GaN), a ternary compound semiconductor (such as InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN), or quaternary compound semiconductors (such as AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP).

In the embodiment of the disclosure, the semiconductor stack 400 may include multiple quantum wells (MQWs) (not shown), emitting infrared light with a peak wavelength of 700 nanometers to 1700 nanometers or a peak wavelength of 610 nanometers. Meters to 700 nanometers of red light, blue or deep blue light with a peak wavelength between 400 nm and 490 nm, or green light with a peak wavelength between 490 nm and 550 nm.

In this embodiment, the optoelectronic semiconductor device 10 further includes an intermediate structure 900 located between the semiconductor stack 400 and the adhesive layer 300. The intermediate structure 900 can be used to optimize the adhesion between the semiconductor stack 400 and the adhesive layer 300, and/ Or increase the probability that the light from the semiconductor stack 400 to the substrate 100 is reflected back away from the substrate 100. The material of the intermediate structure 900 can be a conductive material or a non-conductive material. Specifically, the intermediate structure 900 can be an inorganic insulating material (for example, nitride _Silicon ( _SiN (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO) or indium zinc oxide (IZO)). In one embodiment, the intermediate structure 900 includes a distributed bragg reflector structure (DBR), which is formed by alternately stacking two or more materials with different refractive indexes. In this embodiment, the intermediate structure 900 and the dissociation layer 200 are made of the same material, and the thickness of the intermediate structure 900 is greater than the thickness of the dissociation layer 200 .

As mentioned above, although the semiconductor stack 400 is shown as being located above the substrate 100 in FIG. 1B, in one embodiment, the semiconductor stack 400 and the adhesive layer 300 are actually formed on another growth substrate first. After being mounted (not shown), it is then inverted and bonded to the substrate 100 . In other words, the first semiconductor structure 410, the active region 430, the second semiconductor structure 420, the intermediate structure 900 and a part of the adhesive layer 300 are sequentially formed on the growth substrate, and the dissociation layer 200 and another part of the adhesive layer are formed on the substrate 100. 300, the substrate 100 and the semiconductor stack 400 are connected through the adhesive layer 300 on both sides, and then the growth substrate is removed.

After the semiconductor stack 400 is connected to the substrate 100 through the adhesive layer 300 and the dissociation layer 200, a portion of the semiconductor stack 400 can be etched through an etching process to expose the second semiconductor structure 420 for subsequent electrical connection. The etching process can be, for example, Dry etching process, wet etching process, or a combination thereof. For example, the dry etching process may include plasma etching (PE), reactive ion etching (RIE), inductively coupled plasma reactive ion etching (ICP-RIE); The wet etching process can use acidic solutions or alkaline solutions. In addition, the above-mentioned etching process defines the semiconductor stack 400 as a platform portion (400B, 400D, and 400E) and a high platform portion (400A and 400C). The platform portions 400B, 400D, and 400E only include the second semiconductor structure 420. The high platform portion 400A and 400C include a first semiconductor structure 410, an active region 430, and a second semiconductor structure 420. In this embodiment, the width of the semiconductor stack 400 is smaller than the substrate 100 , and a portion of the intermediate structure 900 is exposed. In other words, the semiconductor stack 400 does not cover a portion of the intermediate structure 900 . In other embodiments, part of the intermediate structure 900, the bonding layer 300 or the dissociation layer 200 can be removed through the above etching process to expose part of the bonding layer 300, the dissociation layer 200 or the substrate 100.

Continuing to refer to FIG. 1B , the optoelectronic semiconductor device 10 selectively includes an insulating layer 500 , and the insulating layer 500 conformably covers the semiconductor stack 400 to protect the semiconductor stack 400 . The insulating layer 500 has a first opening 510 and a second opening 520 respectively on the first elevated portion 400A and the first platform portion 400B of the semiconductor stack 400 . In the embodiment of the present disclosure, the insulating layer 500 may include an oxide insulating material, a non-oxide insulating material, or a combination of the foregoing. For example, the oxide insulating material may include silicon oxide (SiO _x ); the non-oxide insulating material may include silicon nitride (SiN _x ), benzocyclobutene (BCB), cycloolefin copolymer (cycloolefin copolymer) , COC) or fluorocarbon polymer, calcium fluoride (CaF ₂ ) or magnesium fluoride (MgF ₂ ). In one embodiment, the insulating layer 500 may have a reflective function and include a distributed bragg reflector structure (DBR), which is formed by alternately stacking two or more semiconductor materials with different refractive indexes, such as silicon nitride ( SiN _x ), aluminum oxide (AlO _x ), silicon oxide (SiO _x ), magnesium fluoride (MgF _x ), titanium oxide (TiO ₂ ) or niobium oxide (Nb ₂ O ₅ ).

Continuing to refer to FIG. 1B , the optoelectronic semiconductor device 10 selectively includes a first contact structure 610 and a second contact structure 620 . The first contact structure 610 and the second contact structure 620 may be respectively located in the first opening 510 and the second opening 520 of the insulation layer 500 . In this embodiment, the first contact structure 610 has a first width W1, and the second contact structure 620 has a second width W2 that is greater than or equal to the first width W1. The width W3 of the first opening 510 is greater than the first width W1, so when the first contact structure 610 is located on the first semiconductor structure 410, part of the top surface 400a1 of the semiconductor stack 400 will be exposed, that is, part of the semiconductor stack 400 will be exposed. The top surface 400a1 of the layer 400 is not covered by the first contact structure 610; similarly, the width W4 of the second opening 520 is greater than the second width W2, so when the second contact structure 620 is located on the second semiconductor structure 420, part of the The top surface 400a2 of the semiconductor stack 400 will be exposed, that is, part of the top surface 400a2 of the semiconductor stack 400 will be exposed and not covered by the second contact structure 620. The first contact structure 610 is directly in contact with and electrically connected to the first semiconductor structure 410 , and the second contact structure 620 is in direct contact with and electrically connected to the second semiconductor structure 420 . The first contact structure 610 and the second contact structure 620 can form ohmic contacts with the first semiconductor structure 410 and the second semiconductor structure 420 respectively, thereby reducing the forward voltage (Vf) of the optoelectronic semiconductor device 10 .

The first opening 510 and the second opening 520 can be produced by etching part of the insulating layer 500 through an etching process. The first opening 510 and the second opening 520 respectively expose the first contact structure 610 and part of the first opening 500 . Semiconductor structure 410, second contact structure 620 and second semiconductor structure 420. The above etching process may be a dry etching process or a wet etching process. In the embodiment of the present disclosure, the first contact structure 610 and the second contact structure 620 may each include metal materials, alloy materials, metal oxide materials, etc. Metal materials such as germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), nickel (Ni) or copper (Cu); the alloy material may include an alloy of at least two of the above metals, for example Germanium gold nickel (GeAuNi), beryllium gold (BeAu), germanium gold (GeAu), or zinc gold (ZnAu); metal oxide materials can include indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO) , cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO) or oxide Indium zinc (IZO), etc. In one embodiment, the first contact structure 610 and the second contact structure 620 are GeAu alloy and BeAu alloy respectively.

The first opening 510 and the second opening 520 may have the same or different shapes, and the first contact structure 610 and the second contact structure 620 may also have the same or different shapes, such as circular, square or polygonal. The shape of the first opening 510 and the shape of the first contact structure 610 can be selected to be the same or different shapes, and/or the shape of the second opening 520 and the shape of the second contact structure 620 can be selected to be the same or different shapes. .

Continuing to refer to FIG. 1B , the optoelectronic semiconductor element 10 includes a first electrode 710 and a second electrode 720 . The first electrode 710 is located on the insulating layer 500 and the first contact structure 610 and is electrically connected to the first semiconductor structure 410 through the first contact structure 610. The first electrode 710 covers part of the top surface 400a1 of the semiconductor stack 400. ; The second electrode 720 compliantly covers the insulating layer 500 and the second contact structure 620, and is electrically connected to the second semiconductor structure 420 through the second contact structure 620, and the second electrode 720 completely covers the semiconductor stack 400 Top surface 400a2. In this embodiment, the top surface 710a of the first electrode 710 is coplanar with the top surface 720a of the second electrode 720 located above the first elevated portion 400A and the second elevated portion 400C. The first electrode 710 and the second electrode 720 can be used to electrically connect the optoelectronic semiconductor element 10 with an external power source. The current can be conducted in the optoelectronic semiconductor device 10 through the first electrode 710 and the second electrode 720 and drive the carriers (electrons and holes) in the semiconductor stack 400 to recombine and emit light. The light can be emitted toward the substrate 100 or It is emitted in a direction away from the base 100 .

In the embodiment of the present disclosure, the materials of the first electrode 710 and the second electrode 720 may be the same or different, and each may include a metal oxide material, a metal or an alloy. Metal oxide materials include indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO) ), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO) or indium zinc oxide (IZO). Examples of metals include germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), nickel (Ni), indium (In), and tin. (Sn), silver (Ag) or copper (Cu). The alloy may include at least two selected from the group consisting of the above metals, such as gold tin (AuSn), tin silver copper alloy, tin alloy, gold indium (AuIn), germanium gold nickel (GeAuNi), beryllium gold (BeAu ), germanium gold (GeAu), zinc gold (ZnAu).

In some embodiments, a deposition process may be used to form the first electrode 710 and the second electrode 720, which will not be described in detail here. In one embodiment, a planarization process (eg, chemical mechanical planarization (CMP) process) may be performed so that the top surface 710a of the first electrode 710 and the top surface 720a of the second electrode 720 are coplanar, so that A flat surface is provided so that the first electrode 710 and the second electrode 720 can be connected to external circuits at the same level, thereby improving yield and reliability.

Figure 2 is a cross-sectional view of an optoelectronic semiconductor device 20 according to yet another embodiment of the present disclosure. The optoelectronic semiconductor element 20 has a structure similar to that of the optoelectronic semiconductor element 10 (FIG. 1B). The difference is that the optoelectronic semiconductor element 20 has a reflective layer 800 located between the semiconductor stack 400 and the dissociation layer 200. Specifically, the reflective layer 800 is located between the bonding layer 400 and the dissociation layer 200. between layer 300 and dissociation layer 200. The reflective layer 800 can reflect the light emitted from the active area 430 so that the light emits out of the optoelectronic semiconductor element 20 in a direction away from the substrate 100, thereby improving the luminous efficiency. In the embodiment of the present disclosure, the reflective layer 800 may include semiconductor materials, such as III-V semiconductor materials; metal materials, including but not limited to copper (Cu), aluminum (Al), tin (Sn), gold (Au), Or silver (Ag); or the above alloy materials. In other embodiments, the reflective layer 800 may also include a distributed bragg reflector structure (DBR), which is formed by alternately stacking two or more semiconductor materials or insulating materials with different refractive indexes, such as AlAs/GaAs, AlGaAs∕GaAs, InGaP∕GaAs, SiO ₂ /TiO ₂ are alternately stacked. In some embodiments, after forming the dissociation layer 200 on the substrate 100, the reflective layer 800 is formed on the dissociation layer 200, and then the semiconductor stack 400 is connected to the substrate 100 by bonding the reflective layer 800 and the adhesive layer 300; Alternatively, the adhesive layer 300 and the reflective layer 800 are sequentially formed on the semiconductor stack 400, and the dissociation layer 200 is formed on the substrate 100. Subsequently, the semiconductor stack 400 and the substrate 100 are connected by bonding the reflective layer 800 and the dissociation layer 200. .

Figure 3A is a top view of an optoelectronic semiconductor device according to yet another embodiment of the present disclosure. Figure 3B is a cross-sectional view along line A-A’ in Figure 3A. The optoelectronic semiconductor element 30 has a structure similar to the optoelectronic semiconductor element 20 (FIG. 2), but the difference is that the optoelectronic semiconductor element 30 does not have the second platform portion 400D and the third platform portion 400E.

As shown in FIGS. 3A and 3B , the semiconductor stack 400 can be divided into a first platform portion 400A, a second platform portion 400C, and a first platform portion 400B. The first platform portion 400B is located between the first platform portion 400A and the first platform portion 400C. Between the second elevated portions 400C, the first elevated portion 400A and the second elevated portion 400C are respectively located on opposite sides of the first platform portion 400B. Compared with the optoelectronic semiconductor device 20 of the embodiment shown in Figure 2, since this embodiment does not have the second platform portion 400D and the third platform portion 400E, the device area can be further reduced to obtain a smaller size optoelectronic semiconductor. Element 30.

In summary, the optoelectronic semiconductor device of the present disclosure provides a dissociation layer 200 that is highly resistant to high-temperature processes, has no epitaxial defects, and can be used with subsequent laser lift-off processes. Specifically, the dissociation layer 200 of the present disclosure is an inorganic insulating material, which can effectively remove the substrate 100 through the laser lift-off process without damaging the optoelectronic semiconductor components, thereby improving the process yield.

The components of several embodiments are summarized above so that those with ordinary skill in the technical field to which this disclosure belongs can more easily understand the concepts of the embodiments of this disclosure. Those with ordinary skill in the technical field of this disclosure should understand that they can design or modify other processes and structures based on the embodiments of this disclosure to achieve the same purposes and/or advantages as the embodiments introduced here. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and they can be used without departing from the spirit and scope of the present disclosure. Make all kinds of changes, substitutions and substitutions.

10: Optoelectronic semiconductor components 20: Optoelectronic semiconductor components 30: Optoelectronic semiconductor components 100:Base 100a: First upper surface 200: dissociation layer 300: Adhesive layer 300a: Second upper surface 400: Semiconductor stack 400a1: Top surface 400a2: Top surface 400A: The first high platform 400B: First platform department 400C: The second highest platform 400D: Second platform department 400E: Third platform department 410: First semiconductor structure 420: Second semiconductor structure 430:Active zone 500: Insulation layer 510: First opening 520: Second opening 610: First contact structure 620: Second contact structure 710: first electrode 710a: Top surface 720: Second electrode 720a: Top surface 800: Reflective layer 900: Intermediate structure L: length T:Thickness W: Width AA’: line segment W1: first width W2: second width W3, W4: Width

Embodiments of the present disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are for illustration only. In fact, the dimensions of various elements may be arbitrarily enlarged or reduced to clearly illustrate the features of the embodiments of the present disclosure. FIG. 1A is a top view of an optoelectronic semiconductor device according to an embodiment of the present disclosure. Figure 1B is a cross-sectional view along line A-A' in Figure 1A according to an embodiment of the present disclosure. Figure 2 is a cross-sectional view of an optoelectronic semiconductor device according to another embodiment of the present disclosure. Figure 3A is a top view of an optoelectronic semiconductor device according to yet another embodiment of the present disclosure. Figure 3B is a cross-sectional view along line A-A' in Figure 3A according to yet another embodiment of the present disclosure.

10: Optoelectronic semiconductor components

100:Base

100a: First upper surface

200: dissociation layer

300: Adhesive layer

300a: Second upper surface

400: Semiconductor stack

400a1: Top surface

400a2: Top surface

400A: The first high platform

400B: First platform department

400C: The second highest platform

400D: Second platform department

400E: Third platform department

410: First semiconductor structure

420: Second semiconductor structure

430:Active zone

500: Insulation layer

510: First opening

520: Second opening

610: First contact structure

620: Second contact structure

710: first electrode

710a: Top surface

720: Second electrode

720a: Top surface

900: Intermediate structure

T:Thickness

AA’: line segment

W1: first width

W2: second width

W3, W4: Width

Claims (10)

An optoelectronic semiconductor component, including: a base; a semiconductor stack located on the substrate; an adhesive layer between the substrate and the semiconductor stack; and a dissociation layer located between the adhesive layer and the substrate and in direct contact with the substrate; The dissociation layer includes an inorganic insulating material and has a thickness of 30Å to 1000Å. The optoelectronic semiconductor element according to claim 1, wherein the inorganic insulating material is silicon dioxide, silicon nitride, aluminum nitride or a combination thereof. The optoelectronic semiconductor element according to claim 1, wherein the dissociation layer has an absorption coefficient greater than or equal to 10 ² cm ^-1 for a wavelength of 200 nm to 300 nm. The optoelectronic semiconductor component according to claim 1, wherein the semiconductor stack has 10 to 1000 of a width. The optoelectronic semiconductor device according to claim 1, wherein the semiconductor stack is configured to emit red light or infrared light. The optoelectronic semiconductor component as described in claim 1 further includes: A reflective layer is located between the semiconductor stack and the dissociation layer. The optoelectronic semiconductor component as claimed in claim 1, wherein the semiconductor stack includes: a first semiconductor structure; a second semiconductor structure located beneath the first semiconductor structure; and An active region is located between the first semiconductor structure and the second semiconductor structure. The optoelectronic semiconductor device as claimed in claim 7, wherein the semiconductor stack has a first elevated portion, a second elevated portion and a platform portion, wherein the platform portion is located between the first elevated portion and the second elevated portion. and expose the second semiconductor structure. The optoelectronic semiconductor device according to claim 8, further comprising a first contact structure located on the first elevated portion, and a second contact structure located on the platform portion. The optoelectronic semiconductor element according to claim 9, further comprising an insulating layer located on the semiconductor stack, and having a first opening located on the first high platform portion, and a second opening located on the platform portion. , the first contact structure is located in the first opening and the second contact structure is located in the second opening.

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