TWI833439B - Light-emitting device and manufacturing method thereof - Google Patents

Abstract

A light emitting device is disclosed. The light emitting device includes: a support substrate; a semiconductor stack located on the support substrate and including a first type semiconductor layer, a second type semiconductor layer, an active layer located between the first type semiconductor layer and the second type semiconductor layer, and an undoped semiconductor layer located on the first type semiconductor layer; and a first electrode located on the undoped semiconductor layer and the first type semiconductor layer, wherein the first type semiconductor layer includes a first region and a second region, the undoped semiconductor layer is located on the first region, the second region is not covered by the undoped semiconductor layer, the undoped semiconductor layer includes a first rough structure, the first type semiconductor layer includes a second rough structure in the second region, and the first electrode contacts with the second rough structure.

Description

Light-emitting element and manufacturing method thereof

This application relates to a light-emitting element, and more specifically, to a light-emitting element that improves brightness.

Light-emitting diodes (LEDs) in solid-state light-emitting components have low power consumption, low heat production, long life, small size, fast response speed, and good optoelectronic properties, such as stable luminescence wavelength, so they have been widely used. Used in household devices, indicator lights and optoelectronic products, etc.

A conventional light emitting diode includes a substrate, an n-type semiconductor layer, an active layer and a p-type semiconductor layer formed on the substrate, and p and n-electrodes formed on the p-type/n-type semiconductor layer respectively. When the light-emitting diode is energized through the electrode and is forward biased at a specific value, the holes from the p-type semiconductor layer and the electrons from the n-type semiconductor layer are combined in the active layer to emit light. However, as light-emitting diodes are used in different optoelectronic products, the brightness specifications of light-emitting diodes are also improved. How to improve their brightness is one of the research and development goals of those in the technical field.

This application discloses a wafer carrier, including a supporting substrate; a semiconductor stack is provided on the supporting substrate, including a first-type semiconductor layer, a second-type semiconductor layer, and an active layer located on the first-type semiconductor layer and the second-type semiconductor layer. The undoped semiconductor layer is disposed between the undoped semiconductor layer and the first type semiconductor layer; and the first electrode is disposed on the undoped semiconductor layer and the first type semiconductor layer; wherein the first type semiconductor layer includes a first region and a second region, the undoped semiconductor layer is disposed on the first region, the second region is not covered by the undoped semiconductor layer, the undoped semiconductor layer has a first rough structure and the first type semiconductor layer has a second roughness in the second region structure, the first electrode contacts the second rough structure.

This application discloses a method for manufacturing a light-emitting element, which includes providing a growth substrate; sequentially forming a buffer layer, an undoped semiconductor layer, a first-type semiconductor layer, an active layer and a second-type semiconductor layer on the growth substrate; sequentially forming Reflective metal layer and barrier layer on the second type semiconductor layer; providing a supporting substrate; forming a connection layer to connect the barrier layer and the supporting substrate; removing the growth substrate and buffer layer; patterning the undoped semiconductor layer to form the first roughness Structure; forming an insulating layer on the undoped semiconductor layer; patterning the insulating layer and the undoped semiconductor layer to form a recessed area to expose the upper surface of the first type semiconductor layer; and forming a first electrode to fill the recessed area to contact the upper surface. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings to enable those skilled in the art to fully understand the spirit of the present invention. The present invention is not limited to the following embodiments, but can be implemented in other forms. In this specification, there are some identical symbols, which represent components with the same or similar structures, functions, and principles, and those with general knowledge in the industry can deduce them based on the teachings of this specification. For the sake of simplicity in the description, components with the same symbols will not be repeated.

FIG. 1 shows a schematic cross-sectional view of a light-emitting element 1 according to an embodiment of the present application. The light-emitting element 1 includes a support substrate 100 , a semiconductor stack 110 is formed on the support substrate 100 and includes an upper surface S and a first surface S1 away from the support substrate 100 , and a patterned dielectric layer 120 is formed on the semiconductor stack 110 facing the support substrate 100 On the other surface, the reflective metal layer 130 covers the patterned dielectric layer 120, and the barrier layer 132 covers the reflective metal layer 130 and the patterned dielectric layer 120. In one embodiment, the barrier layer 132 can cover the reflective metal layer. At the edge of 130 , a cross-sectional width of the barrier layer 132 may be slightly wider than that of the semiconductor stack 110 . The connection layer 134 covers the barrier layer 132 and is connected to the supporting substrate 100. The insulating layer 140 and the first electrode 150 are formed on the semiconductor stack 110.

As shown in FIG. 1 , in this embodiment, the semiconductor stack 110 includes an undoped semiconductor layer 112 , a first-type semiconductor layer 114 , an active layer 116 , and a second-type semiconductor layer 118 . Stacked in sequence from top to bottom, the first type semiconductor layer 114 includes the upper surface S of the semiconductor stack 110 , and the undoped semiconductor layer 112 is formed on the first type semiconductor layer 114 . The undoped semiconductor layer 112 has a first surface. S1, the first type semiconductor layer 114 includes a first region R1 covered by the undoped semiconductor layer 112 and a second region R2 not covered by the undoped semiconductor layer 112, wherein the second region R2 has the first type semiconductor layer 114 The first electrode 150 is formed on the first type semiconductor layer 114 and the undoped semiconductor layer 112 and contacts the upper surface S of the first type semiconductor layer 114. The insulating layer 140 can cover the shape of the semiconductor stack 110. On the first surface S1 of the undoped semiconductor layer 112 and covering the side surface of the undoped semiconductor layer 112 and the side surface of the semiconductor stack 110 , the lower end of the insulating layer 140 is connected to the patterned dielectric layer 120 .

In one embodiment, the first type semiconductor layer 114 and the second type semiconductor layer 118, such as a cladding layer or a confinement layer, have different conductive types, electrical properties, polarities or uses. Doping elements that provide electrons or holes. For example, the first type semiconductor layer 114 is an n-type semiconductor, and the second type semiconductor layer 118 is a p-type semiconductor. The active layer 116 is formed between the first type semiconductor layer 114 and the second type semiconductor layer 118 . Electrons and holes are combined in the active layer 116 driven by current to convert electrical energy into light energy to emit light. The wavelength of light emitted by the light-emitting element 1 or the semiconductor stack 110 can be adjusted by changing the physical properties and chemical composition of one or more layers in the semiconductor stack 110 . The material of the semiconductor stack 110 may include a III-V semiconductor material of Al _x In _y Ga _(1-xy) N or Al _x In _y Ga _(1-xy) P, where 0≤x, y≤1; x+ y≤1. When the material of the semiconductor stack 110 is AlInGaP series, it can emit red light with a wavelength between 610 nm and 650 nm or yellow light with a wavelength between 550 nm and 570 nm. When the material of the semiconductor stack 110 is the InGaN series, it can emit blue light or deep blue light with a wavelength between 400 nm and 490 nm or green light with a wavelength between 490 nm and 550 nm. When the material of the semiconductor stack 110 is AlGaN series, UV light with a wavelength between 400 nm and 250 nm can be emitted. The active layer 116 may be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MQW). ). The material of active layer 116 may be i-type, p-type or n-type semiconductor. The material of the undoped semiconductor layer 112 may include GaN, AlGaN, or AIN.

As shown in FIG. 1 , in this embodiment, the first surface S1 of the undoped semiconductor layer 112 has a first rough structure P1, and the upper surface S of the first type semiconductor layer 114 has a second rough structure P2. The structure P1 and the second rough structure P2 may respectively include angular cones, cones, domes and other shapes. The angular cones may include polygonal cones such as triangular pyramids and quadrangular pyramids. The cones may include right cones or/and elliptical cones. The domes may include regular cones. For the dome or/or elliptical dome, the shapes of the first rough structure P1 and the second rough structure P2 may be different or the same, and the sizes of the first rough structure P1 and the second rough structure P2 may be different or the same. In one embodiment, the insulating layer 140 has a concave and convex surface S2 conforming to the first rough structure P1. The undoped semiconductor layer 112 covers the first regions R1 on both sides of the first-type semiconductor layer 114 and does not cover the middle second region R2 on the first-type semiconductor layer 114. The light-emitting element 1 has a recessed region corresponding to the second region R2. G, the first electrode 150 is formed on the second region R2 and part of the first region R1. The first electrode 150 has a recess C corresponding to the second region R2. The insulating layer 140 is located on the first region and formed on the first electrode 150 and Between the undoped semiconductor layers 112, the first electrode 150 covers a part of the insulating layer 140. In one embodiment, the first electrode 150 has an uneven surface corresponding to the first region R1 and the second region R2, respectively conforming to the first rough structure P1 and the second rough structure P2.

In one embodiment, the material of patterned dielectric layer 120 may include an insulating oxide, nitride, silicon oxide, titanium oxide, aluminum oxide, magnesium fluoride or silicon nitride. The material of the insulating layer 140 may include silicon nitride or silicon oxide. The material of the patterned dielectric layer 120 may be different from the material of the insulating layer 140 . In one embodiment, the material of the patterned dielectric layer 120 may be titanium dioxide (TiO ₂ ), and the material of the insulating layer 140 may be silicon dioxide (SiO ₂ ) or silicon nitride (SiN _x or Si ₃ N ₄ ). The material of the first electrode 150 may include silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt), ruthenium ( Ru), tungsten (W) or an alloy or laminate of the above materials. The material of the reflective metal layer 130 may include silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt), ruthenium (Ru) or alloys or laminates of the above materials. In one embodiment, the light-emitting element 1 may include a transparent conductive layer (not shown) formed between the patterned dielectric layer 120 and the reflective metal layer 130 . The material of the transparent conductive layer may include graphene, indium tin oxide (ITO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc oxide (ZnO) or indium zinc oxide (IZO). The material of the barrier layer 132 may include chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn), or alloys or laminates of the above materials. In one embodiment, when the barrier layer 132 is a metal stack, the barrier layer 132 is formed by alternately stacking two or more layers of metal, such as Cr/Pt, Cr/Ti, Cr/TiW, Cr /W, Cr/Zn, Ti/Pt, Ti/W, Ti/TiW, Ti/Zn, Pt/TiW, Pt/W, Pt/Zn, TiW/W, TiW/Zn, or W/Zn, etc. The material of the connection layer 134 may include gold (Au), titanium (Ti), chromium (Cr), tungsten (W), zinc (Zn), platinum (Pt), or alloys or laminates of the above materials. In one embodiment, when the connection layer 134 is a metal stack, the connection layer 134 is formed by alternately stacking two or more layers of metal, such as Ti/Au, Cr/Pt, Cr/Ti, Cr/TiW. , Cr/W, Cr/Zn, Ti/Pt, Ti/W, Ti/TiW, Ti/Zn, Pt/TiW, Pt/W, Pt/Zn, TiW/W, TiW/Zn, or W/Zn, etc. . The material of the support substrate 100 may include a conductive substrate or an insulating substrate; the material of the conductive substrate may include a metal material or a semiconductor material, where the metal material includes copper (Cu), gold (Au), nickel (Ni), molybdenum (Mo), tungsten Copper (Cu-W) or alloys or laminates of the above materials, semiconductor materials include Si, Ge, GaAs, ZnO, SiC, or SiSe. The material of the insulating substrate may include sapphire (Sapphire) or aluminum nitride (AlN). In one embodiment, when the supporting substrate 100 is a conductive substrate, the supporting substrate 100 can be used as an electrode to provide electric energy to the light-emitting element 1, or a second electrode (not shown) can be formed on a side of the supporting substrate 100 away from the semiconductor stack 110. On the surface. When the supporting substrate 100 is an insulating substrate, a portion of the first-type semiconductor layer 114 and the active layer 116 can be removed through a yellow light development process to expose a portion of the second-type semiconductor layer 118 or the reflective metal layer 130. A second electrode (not shown) is formed thereon and is electrically connected to the second type semiconductor layer 118 .

2A to 2K show schematic cross-sectional views at various stages in the manufacturing method of the light-emitting element 2 according to an embodiment of the present application. In the embodiments shown in FIGS. 2A to 2K , the structure and materials of the light-emitting element 2 and the light-emitting element 1 shown in FIG. 1 are substantially the same, so the details will not be described again. The following process steps of the light-emitting element 2 are also applicable to the related embodiments of the above-mentioned light-emitting element 1, and therefore will not be described again here.

As shown in FIG. 2A , first, a buffer layer 211 , an undoped semiconductor layer 212 , a first-type semiconductor layer 214 , an active layer 216 and a second-type semiconductor layer 218 are sequentially formed on the growth substrate 201 . The growth substrate 201 may include Gallium arsenide (GaAs) substrate used to grow gallium indium phosphide (AlGaInP), and gallium phosphide (GaP) substrate, or sapphire (Sapphire) used to grow indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN) Al2O3) substrate, gallium nitride (GaN) substrate, silicon carbide (SiC) substrate, and aluminum nitride (AlN) substrate. The growth substrate 201 may be a patterned substrate, that is, the growth substrate 201 has a patterned structure. In one embodiment, the patterned structure slows down or suppresses the dislocation caused by lattice mismatch between the growth substrate 201 and the semiconductor stack 210, thereby improving the epitaxial quality of the semiconductor stack 210. In one embodiment, the method of forming the semiconductor stack 210 on the growth substrate 201 includes metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE) or ion plating. , such as sputtering or evaporation, etc. The buffer layer 211 can reduce the above-mentioned lattice mismatch and suppress dislocation, thereby improving the epitaxial quality. The material of the buffer layer 211 may include GaN, AlGaN or AIN. In one embodiment, the buffer layer 211 includes multiple sub-layers (not shown), and the sub-layers include the same material or different materials. In one embodiment, the buffer layer 211 includes two sub-layers, wherein the growth method of the first sub-layer is sputtering, and the growth method of the second sub-layer is MOCVD. In one embodiment, the buffer layer 211 further includes a third sub-layer. The growth method of the third sub-layer is MOCVD, and the growth temperature of the second sub-layer is higher or lower than the growth temperature of the third sub-layer. In one embodiment, the first, second and third sub-layers include the same material or different materials, such as AlN, GaN, AlGaN. In one embodiment, the buffer layer 211 includes two sub-layers, AlN and GaN. The AlN sub-layer can be grown by sputtering, and the GaN sub-layer can be grown by MOCVD. In one embodiment, both the AlN sublayer and the GaN sublayer are grown by MOCVD. Next, continuing to refer to FIG. 2A , a patterned dielectric layer 220 , a reflective metal layer 230 and a barrier layer 232 are sequentially formed on the second type semiconductor layer 218 .

As shown in FIG. 2B , the support substrate 200 can be connected to the semiconductor stack 210 through the connection layer 234 . The barrier layer 232 can be between the connection layer 234 and the reflective metal layer 230 . The connection layer 234 can be between the barrier layer 234 and the reflective metal layer 230 . between layer 232 and support substrate 200 . In one embodiment, the connection layer 234 connecting the barrier layer 232 and the supporting substrate 200 can be bonded through a high temperature and high pressure process. Next, as shown in FIGS. 2C-2D , after the support substrate 200 is connected to the semiconductor stack 210 , the growth substrate 201 can be removed to expose the buffer layer 211 . The buffer layer 211 exposed after the growth substrate 201 is removed will form a patterned surface due to the patterned structure of the growth substrate 201 being transferred to the surface of the buffer layer 211 . The method of removing the growth substrate 201 includes laser lift off (LLO) or grinding, wherein grinding may include chemical mechanical polishing/planarization (CMP). The material of the support substrate 200 may include a conductive substrate or an insulating substrate; the material of the conductive substrate may include a metal material or a semiconductor material, where the metal material includes copper (Cu), gold (Au), nickel (Ni), molybdenum (Mo), tungsten Copper (Cu-W) or alloys or laminates of the above materials, semiconductor materials include Si, Ge, GaAs, ZnO, SiC, or SiSe. The material of the insulating substrate may include sapphire (Sapphire) or aluminum nitride (AlN). In one embodiment, when the supporting substrate 200 is a conductive substrate, the supporting substrate 200 can be used as an electrode to provide electric energy to the light-emitting element 1, or a second electrode (not shown) can be formed on a side of the supporting substrate 200 away from the semiconductor stack 210. On the surface. When the supporting substrate 200 is an insulating substrate, a portion of the first-type semiconductor layer 214 and the active layer 216 can be removed through a yellow light development process to expose a portion of the second-type semiconductor layer 218 or the reflective metal layer 230, and then exposed A second electrode (not shown) is formed thereon and is electrically connected to the second type semiconductor layer 218 .

As shown in FIG. 2E , the buffer layer 211 is removed to expose the undoped semiconductor layer 212 . The method of removing the buffer layer 211 may include dry etching or wet etching, where dry etching is, for example, inductively coupled plasma. , ICP) etching, reactive ion etching (RIE), etc. The etching liquid for wet etching is, for example, hydrofluoric acid (HF), phosphoric acid (HPO ₃ ), sulfuric acid (H ₂ SO ₄ ), potassium hydroxide ( KOH) etc. In one embodiment, before removing the buffer layer 211, the patterned structure on the surface of the buffer layer 211 may be polished first. The polishing method may include grinding, dry etching, etc., wherein the grinding may include chemical mechanical polishing/planarization. mechanical polishing/planarization (CMP), dry etching may include inductively coupled nuclear plasma etching, reactive ion etching, etc., which can reduce the height difference on the surface of the buffer layer 211. For example, the height difference is between 0 and 0.5 μm, so as to reduce subsequent The etching process produces over-etching. In one embodiment, the surface of the undoped semiconductor layer 212 exposed by removing the buffer layer 211 becomes a non-flat surface due to the etching process of removing the buffer layer 211 .

Next, as shown in FIG. 2F , the undoped semiconductor layer 212 is patterned from the surface to form a first rough structure P1, wherein the surface of the first rough structure P1 constitutes the first surface S1 of the patterned undoped semiconductor layer 212, And the first surface S1 is a roughened surface. The light extraction rate can be improved through the first rough structure P1. Methods for patterning the undoped semiconductor layer 212 may include dry etching and/or wet etching. Dry etching is, for example, inductively coupled nuclear plasma etching, reactive ion etching, etc., and the etching liquid for wet etching is, for example, hydrofluoric acid or phosphoric acid. , sulfuric acid, potassium hydroxide, etc. In one embodiment, before patterning the undoped semiconductor layer 212, the thickness of the undoped semiconductor layer 212 can be thinned first. The thinning method can include grinding, dry etching, etc. The dry etching can be, for example, inductively coupled nuclear power generation. Slurry etching, reactive ion etching, etc., polishing such as chemical mechanical polishing/planarization, etc., in one embodiment, the thickness of the undoped semiconductor layer 212 after patterning is about 0.5 to 2.5 μm. The thickness of the undoped semiconductor layer 212 after thinning and patterning is approximately 0.1 to 0.7 times the thickness of the first electrode 250 in FIG. 2J . In one embodiment, the thickness of the undoped semiconductor layer 212 is approximately 0.12 times to 0.63 times the thickness of an electrode 250. By adjusting the height difference of the undoped semiconductor layer 212, when the first electrode 250 is formed on the undoped semiconductor layer 212 and the first type semiconductor layer 214, the coverage of the first electrode 250 can be improved, thereby improving subsequent electrical conductivity. Reliability of sexual connections.

As shown in FIG. 2G , a die separation area is formed by patterning the semiconductor stack 210 and removing part of the semiconductor stack 210 to expose the patterned dielectric layer 220 , wherein the die separation area defines the periphery of the light emitting element 2 . The method of patterning the semiconductor stack 210 may include dry etching or wet etching. The dry etching is, for example, inductively coupled nuclear plasma etching, reactive ion etching, etc., and the etching liquid for the wet etching is, for example, hydrofluoric acid, phosphoric acid, sulfuric acid, or hydrogen. Potassium oxide, etc. In one embodiment, the thickness of the exposed patterned dielectric layer 220 is smaller than the thickness of the unexposed patterned dielectric layer 220 . Next, as shown in FIG. 2H , an insulating layer 240 is formed on the undoped semiconductor layer 212 . The insulating layer 240 covers the first surface S1 of the undoped semiconductor layer 212 and the side surfaces of the semiconductor stack 210 , and the insulating layer 240 can The uneven surface S2 is formed according to the first rough structure P1 of the undoped semiconductor layer 212. The insulating layer 240 may be formed by plasma-enhanced chemical vapor deposition (PECVD).

As shown in FIG. 2I , the insulating layer 240 and the undoped semiconductor layer 212 are patterned to form a recessed region G to expose the upper surface S of the first type semiconductor layer 214 , wherein the first type semiconductor layer 214 has an insulated layer 240 and an undoped semiconductor layer 212 . The first region R1 covered by the doped semiconductor layer 212 and the second region R2 not covered by the insulating layer 240 and the undoped semiconductor layer 212, and the second region R2 corresponds to the recessed area G, pattern the aforementioned insulating layer 240 and the undoped semiconductor layer 212. The method of heterosemiconductor layer 212 may include dry etching or wet etching. Dry etching is, for example, inductively coupled nuclear plasma etching, reactive ion etching, etc., and the etching liquid for wet etching is, for example, hydrofluoric acid, phosphoric acid, sulfuric acid, or potassium hydroxide. wait. The thickness of the first type semiconductor layer 214 in the first region R1 is approximately 0.1 to 0.6 times the thickness of the first electrode 250 , preferably 0.12 times to 0.5 times. The thickness of the first type semiconductor layer 214 in the second region R2 is approximately 0.1 to 0.6 times the thickness of the first electrode 250 . It is 0.1 times to 0.5 times the thickness of the first electrode 250 , preferably 0.12 times to 0.45 times, wherein the thickness of the first type semiconductor layer 214 in the second region R2 is smaller than the thickness of the first type semiconductor layer 214 in the first region R1 . In one embodiment, the thickness of the first type semiconductor layer 214 in the first region R1 is approximately 0.5 to 2 μm, and the thickness of the first type semiconductor layer 214 in the second region R2 is approximately 0.5 to 1.8 μm.

As shown in FIG. 2J , a first electrode 250 is formed to fill the recessed region G to contact the upper surface S of the first type semiconductor layer 214 , wherein the first electrode 250 covers part of the insulating layer 240 on the first region R1 and is undoped. The semiconductor layer 212, and the first electrode 250 has a recess C in the corresponding recessed region G (ie, the second region R2). The method of forming the first electrode 250 may include sputtering or/and electron-beam evaporation. gun evaporation). In one embodiment, before forming the first electrode 250, the photoresist openings can be defined by a photolithography process, and then the first electrode 250 can be formed by sputtering or/and evaporation. After patterning the insulating layer 240 and not Before forming the recessed region G in the doped semiconductor layer 212, a photoresist opening can also be defined by a yellow photolithography process. The photoresist opening used to form the first electrode 250 is larger than the light used to pattern the insulating layer 240 and the undoped semiconductor layer 212. By blocking the opening, the first electrode 250 can completely cover the first type semiconductor layer 214, which can improve the anti-humidity effect. Finally, the support substrate 200 and the stacked layer thereon are cut along the wafer separation area and divided into individual wafers to form the light-emitting element 2 as shown in FIG. 2K .

FIG. 3 shows a cross-sectional view of the light-emitting element 3 according to an embodiment of the present application. In the embodiment of FIG. 3 , the structure, materials, and process steps of the light-emitting element 3 are substantially the same as those of the light-emitting element 1 shown in FIG. 1 and the light-emitting element 2 shown in FIG. 2K , and therefore will not be described again. The difference is that in addition to covering part of the upper surface S1 of the undoped semiconductor layer 312 and the side surfaces of the semiconductor stack 310, the insulating layer 340 of the light-emitting element 3 is also formed on the first electrode 350 and covers the upper surface of the first electrode 350. side surface.

However, the above embodiments are only illustrative to illustrate the principle and effect of the present application, and are not used to limit the present application. Anyone with ordinary knowledge in the technical field to which this application belongs can make modifications and changes to the above embodiments without violating the technical principles and spirit of this application. All changes and modifications made equally to the shape, structure, characteristics and spirit described in the patentable scope of this application shall be included in the patentable scope of this application.

1, 2, 3: Light-emitting components 100, 200, 300: Support base plate 201:Growth substrate 211:Buffer layer 112, 212, 312: Undoped semiconductor layer 114, 214, 314: first type semiconductor layer 116, 216, 316: active layer 118, 218, 318: second type semiconductor layer 120, 220, 320: Patterned dielectric layer 130, 230, 330: Reflective metal layer 132, 232, 332: barrier layer 134, 234, 334: connection layer 140, 240, 340: Insulation layer 150, 250, 350: first electrode C:dent G: concave area P1: First rough structure P2: Second rough structure R1: first area R2: Second area S: upper surface S1: first surface S2: Concave-convex surface

﹝Figure 1﹞ shows a schematic cross-sectional view of a light-emitting element 1 according to an embodiment of the present application. ﹝ FIGS. 2A to 2K ﹞ show schematic cross-sectional views at various stages in the manufacturing method of the light-emitting element 2 according to an embodiment of the present application. ﹝Figure 3﹞ shows a schematic cross-sectional view of the light-emitting element 3 according to an embodiment of the present application.

1:Light-emitting component

100:Support base plate

110: Semiconductor stack

112: Undoped semiconductor layer

114: First type semiconductor layer

116:Active layer

118: Second type semiconductor layer

120:Patterned dielectric layer

130: Reflective metal layer

132:Barrier layer

134: Connection layer

140:Insulation layer

150: first electrode

C:dent

G: concave area

P1: First rough structure

P2: Second rough structure

R1: first area

R2: Second area

S: upper surface

S1: first surface

S2: Concave-convex surface

Claims (9)

A light-emitting element includes: a first-type semiconductor layer including a first region and a second region; a second-type semiconductor layer; and an active layer located between the first-type semiconductor layer and the second-type semiconductor layer. between; a rough structure including an undoped semiconductor layer disposed on the first region of the first-type semiconductor layer, and the undoped semiconductor layer is not disposed on the second region; and a first electrode disposed on the second region; wherein the rough structure further includes the second region of the first-type semiconductor layer. The light-emitting element as described in item 1 of the patent application, wherein in the rough structure, the undoped semiconductor layer includes a first surface with a first rough structure, and the second region of the first-type semiconductor layer Includes a second surface with a second rough structure. As described in claim 2 of the patent application, the light-emitting element, wherein the first rough structure and/or the second rough structure includes a pyramid or a cone. As for the light-emitting element described in claim 2 of the patent application, the second surface is closer to the active layer than the first surface. As for the light-emitting element described in claim 1, wherein the thickness of the first-type semiconductor layer in the second region is smaller than the thickness of the first-type semiconductor layer in the first region. The light-emitting element described in item 1 of the patent application, wherein the first electrode is disposed on the undoped semiconductor layer and the second region, and the light-emitting element further includes an insulating layer disposed on the undoped semiconductor layer and the second region. between the first electrodes, and the first electrode covers a part of the insulating layer, or the insulating layer The insulating layer is disposed on the undoped semiconductor layer and the first electrode, and the insulating layer covers a part of the first electrode. In the light-emitting element described in claim 6 of the patent application, the insulating layer covers one side surface of the semiconductor stack. The light-emitting element described in claim 1 of the patent application further includes an insulating layer disposed on the rough structure, wherein the insulating layer has a concave and convex surface conforming to the rough structure. As described in claim 1 of the patent application, the first electrode has a recess corresponding to the second area.

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