TW202339272A - Semiconductor device - Google Patents

Abstract

The disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate, at least one first metal oxide semiconductor, at least one second metal oxide semiconductor, a first doped well region, a second doped well region and a deep-doped well region. The first metal oxide semiconductor and the second metal oxide semiconductor are located on the semiconductor substrate. The first doped well region is located in the semiconductor substrate, and the second metal oxide semiconductor is located in the first doped well region. The second doped well region is located in the semiconductor substrate, and the first metal oxide semiconductor and the first doped well region are located in the second doped well region. The deep-doped well region is located between the second doped well region and the semiconductor substrate, so that the deep-doped well region simultaneously covers the first metal oxide semiconductor and the second metal oxide semiconductor above it.

Description

Semiconductor device

This case relates to a semiconductor device, specifically a semiconductor device having a shared Deep N-type Well (DNW) region.

In the structure of the conventional semiconductor device 60, as shown in FIG. 1, when an N-type metal oxide semiconductor (NMOS) 64 and a P-type metal oxide semiconductor (PMOS) 66 are formed on the P-type substrate 62, the deep N-type well region 68 is usually used to isolate the P-well (P-Well) 70 and the P-type substrate 62 to prevent the N-type metal oxide semiconductor 64 from being interfered by noise.

Moreover, in the conventional technology, as shown in FIG. 2 , in the semiconductor device 60 , a plurality of N-type metal oxide semiconductors are gathered together to form a first N-type metal oxide semiconductor region 72 and a second N-type metal oxide semiconductor region 72 . region 74, and when a plurality of P-type metal oxide semiconductors are gathered together to form a first P-type metal oxide semiconductor region 76 and a second P-type metal oxide semiconductor region 78, and are arranged in order from top to bottom into the first N Type metal oxide semiconductor region 72 , first P-type metal oxide semiconductor region 76 , second N-type metal oxide semiconductor region 74 and second P-type metal oxide semiconductor region 78 . Among them, the first N-type metal oxide semiconductor region 72 is disposed in the first deep N-type well region 68', and the second N-type metal oxide semiconductor region 74 is disposed in the second deep N-type well region 68". However, In compliance with the Design Rule Check (DRC) rules, there are fixed specifications and dimensions between the first deep N-type well area 68' and the second deep N-type well area 68", and due to the wiring relationship, the first deep N-type well area 68' The N-type well area 68' and the second deep N-type well area 68" must be separated, and the distance between the two must be maintained at a larger interval. Increasing the application of the deep N-type well area 68 also increases the use of the overall area. .

This application provides a semiconductor device, including a semiconductor substrate, at least a first metal oxide semiconductor, at least a second metal oxide semiconductor, a first doping well region, a second doping well region and a deep doping well region. The first metal oxide semiconductor and the second metal oxide semiconductor are located on the semiconductor substrate; the first doping well region is located in the semiconductor substrate, and the second metal oxide semiconductor is located in the first doping well region; the second doping well region is located in In the semiconductor substrate, the first metal oxide semiconductor and the first doping well region are located in the second doping well region; the deep doping well region is located between the second doping well region and the semiconductor substrate.

In some embodiments, the semiconductor substrate is a P-type semiconductor substrate.

In some embodiments, the first metal oxide semiconductor is an N-type metal oxide semiconductor, and the second metal oxide semiconductor is a P-type metal oxide semiconductor.

In some embodiments, the first doping well region is an N-type well, and the second doping well region is a P-type well.

In some embodiments, the deep doped well region is a deep N-type well region.

In some embodiments, the first metal oxide semiconductor includes a first gate structure located on the semiconductor substrate, an N-type source doping region and an N-type drain doping region located in the second doping well region. region and a P-type base doped region.

In some embodiments, the second metal oxide semiconductor includes a second gate structure located on the semiconductor substrate, a P-type source doping region and a P-type drain doping region located in the first doping well region. region and an N-type base doped region.

In some embodiments, the semiconductor device further includes a capacitor structure located on the semiconductor substrate and corresponding to the deep doped well region below, so that the deep doped well region covers the capacitor structure.

In some embodiments, the semiconductor device further includes a resistive structure located on the semiconductor substrate and corresponding to the deep doped well region below, so that the deep doped well region covers the resistive structure.

In some embodiments, the semiconductor device further includes a capacitor structure and a resistor structure located on the semiconductor substrate and corresponding to the deep doped well region below, so that the deep doped well region also covers the capacitor structure and the resistor structure.

This application further provides a semiconductor device, which includes a semiconductor substrate, at least one N-type metal oxide semiconductor region, at least one P-type metal oxide semiconductor region, and a deep N-type well region. The N-type metal oxide semiconductor region and the P-type metal oxide semiconductor region are respectively located on the semiconductor substrate; the deep N-type well region is formed in the semiconductor substrate and is located between the semiconductor substrate and the N-type metal oxide semiconductor region and the P-type metal oxide semiconductor region. , so that the deep N-type well region covers the N-type metal oxide semiconductor region and the P-type metal oxide semiconductor region.

In some embodiments, the semiconductor device further includes a capacitor structure region located on the semiconductor substrate and corresponding to the deep N-type well region below, so that the deep N-type well region covers the capacitor structure region.

In some embodiments, the semiconductor device further includes a resistive structure region located on the semiconductor substrate and corresponding to the deep N-type well region below, so that the deep N-type well region covers the resistive structure region.

In some embodiments, the semiconductor device further includes a capacitor structure region and a resistor structure region located on the semiconductor substrate and corresponding to the deep N-type well region below, so that the deep N-type well region covers the capacitor structure region and the resistor structure region.

In some embodiments, when there are a plurality of N-type metal oxide semiconductor regions and a plurality of P-type metal oxide semiconductor regions, the N-type metal oxide semiconductor regions and the P-type metal oxide semiconductor regions are sequentially arranged at intervals.

To sum up, since the deep N-shaped well area has fixed rules and dimensions, effective layout will be of great help in reducing the area. This case proposes a semiconductor device that conforms to the standard cell mode configuration to use a shared deep doping well region (deep N-type well region) to cover the first metal oxide semiconductor (N-type metal oxide semiconductor, NMOS) and The second metal oxide semiconductor (P-type metal oxide semiconductor, PMOS) even covers the capacitor structure and resistor structure, so that the deep doping well area can fully cover all components without additional separation, and the wiring length is shorter and can also be reduced height and area. Based on this, under the condition that the size and area of the chip (chip) is shrinking day by day, this case helps to reduce the use of area to achieve an improvement in area utilization.

Preferred embodiments are provided below for detailed description. However, the embodiments are only used as examples and will not limit the scope of the present case. In addition, some components or structures are omitted in the drawings of the embodiments to clearly illustrate the technical features of the present invention. The same reference numbers will be used throughout the drawings to refer to the same or similar elements.

FIG. 3 is a structural cross-sectional view of a semiconductor device according to an embodiment of the present invention. Please refer to FIG. 3. A semiconductor device 10 includes a semiconductor substrate 12, at least a first metal oxide semiconductor 14, at least a second metal oxide semiconductor 16, a first doping well region 18, a second doping well region 20 and a deep doping well region 22. In this embodiment, the semiconductor substrate 12 is a P-type semiconductor substrate. In this semiconductor device 10 , the first metal oxide semiconductor 14 is located on the semiconductor substrate 12 , and the second metal oxide semiconductor 16 is also located on the semiconductor substrate 12 and is located on one side of the first metal oxide semiconductor 14 . The first doping well region 18 is located in the semiconductor substrate 12 , and the second metal oxide semiconductor 16 is located in the first doping well region 18 , the second doping well region 20 is located in the semiconductor substrate 12 , and the first metal oxide semiconductor 14 And the first doping well region 18 is located in the second doping well region 20, the deep doping well region 22 is located between the second doping well region 20 and the semiconductor substrate 12, the first metal oxide semiconductor 14 and the second metal The oxide semiconductor 16 is located above the deep doping well region 22 at the same time, so that the deep doping well region 22 simultaneously covers the first metal oxide semiconductor 14 and the second metal oxide semiconductor 16 above it.

Among them, the first metal oxide semiconductor 14 is an N-type metal oxide semiconductor (NMOS), and the second metal oxide semiconductor 16 is a P-type metal oxide semiconductor (PMOS). The first doping well region 18 is an N-well (N-well), and the second doping well region 20 is a P-type well (P-well). The deep doping well region 22 is a deep N-well region (Deep N-well).

As shown in FIG. 3 , the first metal oxide semiconductor 14 basically includes a first gate structure 141 , an N-type source doped region 142 , an N-type drain doped region 143 and a P-type base doped region. 144. The first gate structure 141 is located on the semiconductor substrate 12, and the N-type source doping region 142 and the N-type drain doping region 143 are located in the second doping well region 20 and on both sides of the first gate structure 141. The P-type base doped region 144 is located in the second doped well region 20 and adjacent to the N-type source doped region 142 . The second metal oxide semiconductor 16 basically includes a second gate structure 161, a P-type source doping region 162, a P-type drain doping region 163 and an N-type base doping region 164. The second gate structure 161 is located on the semiconductor substrate 12, and the P-type source doping region 162 and the P-type drain doping region 163 are located in the first doping well region 18 and on both sides of the second gate structure 161. The N-type base doped region 164 is located in the first doped well region 18 and adjacent to the P-type source doped region 162 .

In one embodiment, the semiconductor device 10 further includes a capacitor structure (not shown in the figure). The capacitor structure is located on the semiconductor substrate 12 and corresponds to the deep doping well region 22 below, so that the deep doping well region 22 covers the top thereof. capacitor structure. In one embodiment, the semiconductor device 10 further includes a resistive structure (not shown in the figure). The resistive structure is located on the semiconductor substrate 12 and corresponds to the deep doping well region 22 below, so that the deep doping well region 22 can cover it. Resistor structure above. In another embodiment, the semiconductor device 10 may further include a capacitor structure and a resistor structure at the same time. The capacitor structure and the resistor structure are both located on the semiconductor substrate 12 and correspond to the deep doping well region 22 below, so that the deep doping well region 22 It can cover the capacitive structure and resistive structure above it at the same time. Therefore, the common deep doping well region 22 can cover the first metal oxide semiconductor 14 , the second metal oxide semiconductor 16 , the capacitor structure or/and the resistance structure at the same time.

Figure 4 is a schematic diagram of the layout structure of a semiconductor device according to an embodiment of the present invention. Please refer to Figure 4. As shown in Figure 4, a semiconductor device 10 includes a semiconductor substrate 12 and at least one N-type metal oxide semiconductor region 30, 32 (herein referred to as the third An N-type metal oxide semiconductor region 30 and a second N-type metal oxide semiconductor region 32 are taken as an example, but this case is not limited to this number), at least one P-type metal oxide semiconductor region 34, 36 (herein, the first P-type metal oxide semiconductor region is P-type metal oxide semiconductor region 34 and a second P-type metal oxide semiconductor region 36 (for example, but this case is not limited to this number) and a deep N-type well region 38 . In this embodiment, the semiconductor substrate 12 is a P-type semiconductor substrate.

As shown in FIG. 4 , in the semiconductor device 10 , the first N-type metal oxide semiconductor region 30 , the second N-type metal oxide semiconductor region 32 , the first P-type metal oxide semiconductor region 34 and the second P-type metal oxide semiconductor region The regions 36 are respectively located on the semiconductor substrate 12 and are arranged at intervals, that is, they are arranged from top to bottom as the first N-type metal oxide semiconductor region 30, the first P-type metal oxide semiconductor region 34, and the second N-type metal oxide semiconductor region 34. The metal oxide semiconductor region 32 and the second P-type metal oxide semiconductor region 36 . The deep N-type well region 38 is formed in the semiconductor substrate 12 and is located between the semiconductor substrate 12 and the first N-type metal oxide semiconductor region 30, the first P-type metal oxide semiconductor region 34, the second N-type metal oxide semiconductor region 32 and Between the second P-type metal oxide semiconductor regions 36, the commonly used deep N-type well region 38 simultaneously covers the first N-type metal oxide semiconductor region 30, the first P-type metal oxide semiconductor region 34, the second N-type well region 38 above it. P-type metal oxide semiconductor region 32 and a second P-type metal oxide semiconductor region 36 .

In order to clearly show the deep N-type well region 38, it can simultaneously cover the first N-type metal oxide semiconductor region 30, the first P-type metal oxide semiconductor region 34, the second N-type metal oxide semiconductor region 32 and the second P-type well region 30 above it. type metal oxide semiconductor region 36. In the semiconductor device 10 shown in FIG. 4, in this case, only the oxide diffusion layer 40 and the polycrystalline silicon layer 42 are drawn above the deep N-type well region 38 as a component layout diagram, and the other component layers are omitted. .

Please refer to both FIG. 3 and FIG. 4 . Each first N-type metal oxide semiconductor region 30 and each second N-type metal oxide semiconductor region 32 respectively include a plurality of N-type metal oxide semiconductors (i.e., first metal oxide semiconductors). Semiconductor 14) and the corresponding second doped well region 20, as shown in Figure 3, each N-type metal oxide semiconductor at least includes a first gate structure 141, an N-type source doping region 142, and an N-type drain Doped region 143 and P-type base doped region 144 and other structures. Each first P-type metal oxide semiconductor region 34 and each second P-type metal oxide semiconductor region 36 also respectively include a plurality of P-type metal oxide semiconductors (ie, second metal oxide semiconductors 16) and corresponding first doped metal oxide semiconductors. As shown in FIG. 3 , each P-type metal oxide semiconductor at least includes a second gate structure 161 , a P-type source doping region 162 , a P-type drain doping region 163 and an N-type base doping region. Complex area 164 and other structures.

In one embodiment, FIG. 5 is a schematic diagram of the layout structure of a semiconductor device according to another embodiment of the present invention. Please refer to FIG. 5 . The semiconductor device 10 further includes a capacitor structure region 44 and a resistor structure region 46 . The capacitor structure region 44 is located on the semiconductor substrate 12 and corresponds to the deep N-type well region 38 below. The resistor structure region 46 Also located on the semiconductor substrate 12 and corresponding to the deep N-type well region 38 below, the deep N-type well region 38 not only covers the first N-type metal oxide semiconductor region 30, the first P-type metal oxide semiconductor region 34, the second N-type well region 38 In addition to the P-type metal oxide semiconductor region 32 and the second P-type metal oxide semiconductor region 36, it also covers the capacitor structure region 44 and the resistance structure region 46.

Among them, in order to clearly show the deep N-type well region 38, it can simultaneously cover the first N-type metal oxide semiconductor region 30, the first P-type metal oxide semiconductor region 34, the second N-type metal oxide semiconductor region 32, the second P-type metal oxide semiconductor region 30 and the first P-type metal oxide semiconductor region 34 above it. Type metal oxide semiconductor region 36, capacitance structure region 44 and resistance structure region 46. In the semiconductor device 10 shown in FIG. 5, in this case only the oxide diffusion layer 40, the polycrystalline silicon layer 42, and the like are drawn above the deep N-type well region 38. Resistor Protection Oxide (RPO) 48 and metal layer 50 are used as component layout diagrams, and other component layers are omitted.

In another embodiment, the semiconductor device 10 may further have a separate capacitor structure region 44 or a resistor structure region 46 design according to the actual circuit design. In other words, the semiconductor device 10 may also only include the capacitor structure region 44 , so that the deep N-type well region 38 also covers the capacitor structure region 44 . Alternatively, the semiconductor device 10 only includes the resistive structure region 46 , so that the deep N-type well region 38 also covers the resistive structure region 46 .

In one embodiment, the present invention is explained based on the actual layout structure of the semiconductor device 10. Please refer to FIG. 2 and FIG. 4 at the same time to demonstrate the effects that the present invention can achieve by comparing the differences between the conventional technology and the present invention. . As shown in Figure 2, the conventional semiconductor device 60 uses the first deep N-type well region 68' and the second deep N-type well region 68", so the entire layout height is 17.61 µm and the layout area is 449.05 µm ^2. In contrast to this case, As shown in Figure 4, the semiconductor device 10 of this case uses a shared deep N-type well area 38, the entire layout height is 12.34 μm, and the layout area is 314.67 μm ^2. Compared with the conventional semiconductor device 60, the semiconductor device 10 of this case has The height is reduced by 5.27 µm and the area is reduced by 14.7%, so the layout area can be effectively reduced, which is in line with the future trend of increasing concentration.

In another embodiment, the present case is illustrated with the actual layout structure of the semiconductor device 10 including the capacitor structure region 44 and the resistor structure region 46. Please refer to FIG. 6 to compare the differences between the conventional technology and the present case. , to show the effect that this case can achieve. As shown in FIG. 6 , the conventional semiconductor device 60 on the left uses the first deep N-type well region 68 ′ and the second deep N-type well region 68 ″, so the entire layout height is 30.48 μm and the layout area is 762 μm ² . On the other hand, In this case, as shown on the right side of FIG. 6 , the semiconductor device 10 of this case uses a common deep N-type well region 38 , and the deep N-type well region 38 simultaneously covers the first N-type metal oxide semiconductor region 30 and the first P-type metal oxide semiconductor region 30 . The entire layout height of the semiconductor region 34, the second N-type metal oxide semiconductor region 32, the second P-type metal oxide semiconductor region 36, the capacitor structure region 44 and the resistance structure region 46 is 23.655 µm, and the layout area is 590 µm ² . Compared with Compared with the conventional semiconductor device 60, the height of the semiconductor device 10 in this case is reduced by 6.825 μm, and the area is reduced by 12.9%. Therefore, the layout occupied area can be effectively reduced, which is in line with the future trend of increasing integration.

To sum up, this case proposes a semiconductor device that conforms to the standard cell mode configuration and utilizes a shared deep doping well region (deep N-type well region) to cover the first metal oxide semiconductor (N-type metal oxide Semiconductor) and the second metal oxide semiconductor (P-type metal oxide semiconductor), even covering the capacitor structure and resistor structure, so that the deep doping well area can fully cover all components without additional separation, and the wiring length is shorter. Reduce height and area. Based on this, under the condition that the size and area of the chip (chip) is shrinking day by day, this case helps to reduce the use of area to achieve an improvement in area utilization.

The above-mentioned embodiments are only for illustrating the technical ideas and characteristics of this case. Their purpose is to enable those familiar with this technology to understand the contents of this case and implement them accordingly. However, they cannot be used to limit the patent scope of this case. That is, generally speaking, according to this case Equal changes or modifications made to the spirit disclosed should still be covered by the patent application scope of this case.

10:Semiconductor device 12:Semiconductor substrate 14:First metal oxide semiconductor 141: First gate structure 142:N-type source doped region 143:N-type drain doped region 144:P-type base doped region 16: Second metal oxide semiconductor 161: Second gate structure 162:P-type source doped region 163:P-type drain doped region 164:N-type base doped region 18: First doping well area 20: Second doping well area 22: Deep doping well area 30: First N-type metal oxide semiconductor region 32: Second N-type metal oxide semiconductor region 34: First P-type metal oxide semiconductor region 36: Second P-type metal oxide semiconductor region 38: Deep N-type well area 40: Oxidation diffusion layer 42:Polycrystalline silicon layer 44: Capacitor structure area 46:Resistance structure area 48: Resistance protection oxide layer 50:Metal layer 60:Semiconductor device 62:P type substrate 64:N-type metal oxide semiconductor 66:P-type metal oxide semiconductor 68: Deep N-type well area 68’: The first deep N-type well area 68”: The second deepest N-type well area 70:P type well 72: First N-type metal oxide semiconductor region 74: Second N-type metal oxide semiconductor region 76: First P-type metal oxide semiconductor region 78: Second P-type metal oxide semiconductor region

FIG. 1 is a cross-sectional structural view of a conventional semiconductor device. FIG. 2 is a schematic diagram of the layout structure of a conventional semiconductor device. FIG. 3 is a structural cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 4 is a schematic diagram of the layout structure of a semiconductor device according to an embodiment of the present invention. FIG. 5 is a schematic diagram of the layout structure of a semiconductor device according to another embodiment of the present invention. FIG. 6 is a schematic diagram of the layout structure of a conventional semiconductor device and the semiconductor device of this invention.

10:Semiconductor device

12:Semiconductor substrate

14:First metal oxide semiconductor

141: First gate structure

142:N-type source doped region

143:N-type drain doped region

144:P-type base doped region

16: Second metal oxide semiconductor

161: Second gate structure

162:P-type source doped region

163:P-type drain doped region

164:N-type base doped region

18: First doping well area

20: Second doping well area

22: Deep doping well area

Claims (10)

A semiconductor device including: a semiconductor substrate; At least one first metal oxide semiconductor is located on the semiconductor substrate; At least a second metal oxide semiconductor is located on the semiconductor substrate; A first doping well region is located in the semiconductor substrate, and the second metal oxide semiconductor is located in the first doping well region; A second doping well region is located in the semiconductor substrate, and the first metal oxide semiconductor and the first doping well region are located in the second doping well region; and A deep doping well region is located between the second doping well region and the semiconductor substrate. The semiconductor device according to claim 1, wherein the semiconductor substrate is a P-type semiconductor substrate. The semiconductor device of claim 2, wherein the first metal oxide semiconductor is an N-type metal oxide semiconductor, and the second metal oxide semiconductor is a P-type metal oxide semiconductor. The semiconductor device of claim 3, wherein the first doping well region is an N-type well, and the second doping well region is a P-type well. The semiconductor device of claim 4, wherein the deep doped well region is a deep N-type well region. The semiconductor device of claim 5, wherein the first metal oxide semiconductor includes a first gate structure located on the semiconductor substrate, and an N-type source doped region located in the second doped well region , an N-type drain doped region and a P-type base doped region. The semiconductor device of claim 5, wherein the second metal oxide semiconductor includes a second gate structure located on the semiconductor substrate, and a P-type source doping region located in the first doping well region , a P-type drain doped region and an N-type base doped region. The semiconductor device of claim 1 further includes a capacitor structure located on the semiconductor substrate and corresponding to the deep doped well region below, so that the deep doped well region covers the capacitor structure. The semiconductor device of claim 1 further includes a resistive structure located on the semiconductor substrate and corresponding to the deep doped well region below, so that the deep doped well region covers the resistive structure. A semiconductor device including: a semiconductor substrate; At least one N-type metal oxide semiconductor region is located on the semiconductor substrate; At least one P-type metal oxide semiconductor region is located on the semiconductor substrate; and A deep N-type well region is formed in the semiconductor substrate and is located between the semiconductor substrate and the N-type metal oxide semiconductor region and the P-type metal oxide semiconductor region, so that the deep N-type well region covers the N-type metal oxide semiconductor region and the P-type metal oxide semiconductor region.

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