TW202338173A - High-hardness substrate and fabricating method thereof achieving the effect of greatly reducing the polishing time - Google Patents

Abstract

Disclosed is a fabricating method for a high hardness substrate, including the following steps: providing a crystal ingot; dividing the crystal ingot into a plurality of wafers; performing double-sided grinding on the surface of each wafer; performing copper disc polishing on the wafers; performing dry etching on a surface of one side of each wafer; performing chemical-mechanical polishing on the surface of each wafer; cleaning these wafers to obtain a plurality of high-hardness substrates. A dry etching process is performed before a chemical-mechanical polishing process is performed on the wafer, such that the depth of damage on the surface of the wafer can be reduced, further the thickness requirement for subsequent wafer thinning through chemical-mechanical polishing is reduced, and the effect of greatly reducing the polishing time is achieved.

Description

High-hardness substrate and manufacturing method thereof

The present invention relates to the field of semiconductor manufacturing; in particular, it refers to a substrate and a manufacturing method thereof.

It is known that conventional substrates are manufactured through manufacturing steps such as ingot slicing and segmentation, mechanical grinding, copper disc polishing, chemical mechanical polishing (CMP) and cleaning.

Since the ingot is mechanically processed for slicing and dividing, many defects such as line marks will be generated on the surface of the substrate. In order to keep the surface of the substrate smooth, it is necessary to remove defects on the surface of the substrate through mechanical grinding and copper disc polishing processes. Then, Chemical mechanical polishing is performed to remove surface defects such as surface damage caused by mechanical processing.

However, when the substrate is a high-hardness substrate, the removal rate of chemical mechanical polishing is not high. The removal rate refers to measuring the thickness change of the material before polishing and after polishing, and dividing the thickness change by polishing Time, that is to say, when the substrate is a high-hardness substrate, it takes a lot of time to remove a certain thickness of material, which leads to a problem of inefficiency. Accordingly, how to maintain the flatness of the substrate surface and improve the removal rate is an urgent need problem solved.

In view of this, the object of the present invention is to provide a method for manufacturing a high-hardness substrate that can maintain the surface flatness of the substrate and improve the removal rate.

In order to achieve the above objectives, the present invention provides a method for manufacturing a high-hardness substrate, which includes the following steps:

Provide a wafer ingot; divide the wafer ingot into a plurality of wafers; perform double-sided grinding on the surface of each wafer; perform copper disc polishing on the wafers; perform dry etching on one surface of one side of each wafer ; Perform chemical mechanical polishing on the surface of each wafer; Clean the wafers to obtain a plurality of high-hardness substrates.

The present invention also provides a high-hardness substrate produced by the above method.

The effect of the present invention is that by performing a dry etching process before chemical mechanical polishing of the wafer, the depth of damage on the surface of the wafer can be reduced, thereby reducing the thickness requirement of subsequent wafers that need to be thinned by chemical mechanical polishing. The quantity is reduced, thereby achieving the effect of greatly reducing the polishing time; in addition, for high-hardness substrates, the removal rate of dry etching is higher than that of chemical mechanical polishing, that is to say, compared with the conventional complete Using chemical mechanical polishing to thin the wafer, the present invention combines dry etching with chemical mechanical polishing to thin the wafer, which can greatly reduce the man-hours required for wafer thinning, thereby improving the wafer thinning efficiency. The effect.

In order to illustrate the present invention more clearly, the preferred embodiments are described in detail below along with the drawings. Please refer to FIG. 1 , which is a flow chart of a method for manufacturing a high-hardness substrate according to a preferred embodiment of the present invention. The manufacturing method of the high-hardness substrate includes the following steps:

Step S201: Provide a crystal ingot; the crystal ingot can be a sapphire, ceramic or diamond crystal ingot grown by the CZ method.

Step S202: Divide the ingot into a plurality of wafers. In this embodiment, the ingot is divided into a plurality of wafers by a wire saw. The wafers are sapphire with an a-axis direction or an r-axis direction. , ceramic or diamond wafer.

Step S203, perform double-sided grinding on the surface of each wafer; the double-sided grinding is physical mechanical grinding. In this embodiment, the front and back sides of each wafer are mechanically ground at the same time. In other cases, In embodiments, the front and back sides of each wafer may also be mechanically polished respectively.

Step S204, perform copper disk polishing on the wafers; in this embodiment, copper disk polishing is performed on the front and back sides of each wafer respectively.

Step S205, dry etching is performed on one surface of each side of the wafer; the dry etching uses gas as the main etching medium and uses plasma energy to drive the reaction, where the plasma has physical effects on the etching process. Chemical effects. First, the plasma will decompose the etching gas molecules to produce highly active molecules that can quickly etch away the material. In addition, the plasma will also ionize these chemical components to make them charged. When the wafer is placed on the negatively charged cathode When the wafer is on, the positively charged ions will be attracted by the cathode and accelerate towards the cathode, and then hit the wafer surface, thereby etching.

It should be noted that in this embodiment, the dry etching is inductively coupled plasma (ICP) etching, and the etching gas used includes Ar, Cl ₂ , BCl ₃ , O ₂ , H ₂ , and CF ₄ , CHF ₃ , C ₂ F ₆ , C ₃ F ₆ , C ₄ F ₈ , CHF ₃ , SF ₆ , NF ₃ or a combination of the aforementioned etching gases. The etching temperature is controlled between 100 and 200∘C. The etching time is controlled between 15 and 50 minutes, whereby the thickness removal rate of the dry etching is greater than 4.0 μm/hr. In this embodiment, the thickness removal rate of the dry etching is between 6.0 μm/hr and 10.0 between μm/hr.

Please coordinate with Figures 2 and 3. Figure 2 is a photo before dry etching on the wafer surface. It can be seen that the wafer surface is uneven and the surface roughness Ra is greater than 3.5nm, while Figure 3 is a photo of the same wafer. The photo of the same surface after dry etching shows that the wafer surface is flat and the surface roughness Ra is less than 2nm. In addition, please refer to Figure 4 and Figure 5. Figure 4 is before dry etching on the wafer surface. The surface topography measurement results show that the surface topography of the wafer surface is irregularly distributed. Figure 4 shows the surface topography measurement results after dry etching on the same surface of the same wafer. It can be seen that the surface topography of the wafer surface is irregularly distributed. The high and low topography is distributed in a concentric circle, and its high and low distribution gradually changes from the center of the wafer to the radial direction, which has the technical effect of avoiding warpage and facilitating subsequent processing.

Step S206: Perform chemical mechanical polishing (CMP) on the surface of each wafer. In this embodiment, step S205 includes dry etching on the front and back sides of each wafer, and step S206 includes Chemical mechanical polishing is performed on the front and back of each wafer; the thickness removal rate of chemical mechanical polishing of ^each wafer is between 0.3 μm/hr and Between 0.5μm/hr.

In other embodiments, steps S205 and S206 may also include dry etching on at least one side of each wafer, and then performing chemical mechanical polishing on the front and back of each wafer, or steps S205 and S206 may also include performing dry etching on at least one side of each wafer. Dry etching and chemical mechanical polishing are performed on the same side of each wafer.

Step S207: Clean the wafers to obtain a plurality of high-hardness substrates; Step S207 includes cleaning the wafers with SC1 and SC2.

In summary, by performing a dry etching process before chemical mechanical polishing of the wafer, the present invention can reduce the depth of damage on the surface of the wafer, thereby reducing the thickness of subsequent wafers that need to be thinned by chemical mechanical polishing. The demand is reduced, thereby achieving the effect of greatly reducing the polishing time; in addition, for high-hardness wafers, the thickness removal rate of dry etching is higher than that of chemical mechanical polishing, that is to say, the thickness removal rate is relatively high. Compared with the conventional process that completely uses chemical mechanical polishing to thin the wafer, the present invention uses dry etching combined with chemical mechanical polishing to thin the wafer, which can greatly reduce the man-hours required for thinning high-hardness wafers, thereby achieving Improve wafer thinning efficiency.

Furthermore, the high-hardness substrate produced by the manufacturing method of the high-hardness substrate provided by the present invention not only has a smooth surface, but also has a concentrically distributed high and low shape on the dry-etched wafer surface, which has the ability to avoid warping and Conducive to the technical effect of subsequent processing.

The above are only the best possible embodiments of the present invention. Any equivalent changes made by applying the description and patent scope of the present invention should be included in the patent scope of the present invention.

[Invention] S201, S202, S203, S204, S205, S206, S207: steps

FIG. 1 is a flow chart of a method for manufacturing a high-hardness substrate according to a preferred embodiment of the present invention. Figure 2 is a photo of the wafer surface before dry etching according to the present invention. Figure 3 is a photo of the wafer surface after dry etching according to the present invention. Figure 4 shows the surface morphology measurement results of the wafer surface of the present invention before dry etching. Figure 5 shows the surface morphology measurement results of the wafer surface of the present invention after dry etching.

S201, S202, S203, S204, S205, S206, S207: steps

Claims (12)

A method for manufacturing a high-hardness substrate, including the following steps: Provide a crystal ingot; Divide the ingot into multiple wafers; Double-sided grinding is performed on the surface of each wafer; Perform copper disc polishing on the wafers; Perform dry etching on one surface of one side of each wafer; chemically mechanically polish the surface of each wafer; The wafers are cleaned to obtain a plurality of high-hardness substrates. The method for manufacturing a high-hardness substrate as claimed in claim 1, wherein the dry etching is Inductively Coupled Plasma (ICP) etching. The manufacturing method of a high-hardness substrate as described in claim 2, wherein the etching gas used in the dry etching includes Ar, Cl ₂ , BCl ₃ , O ₂ , H ₂ , CF ₄ , CHF ₃ , C ₂ F ₆ , and C ₃ One of F ₆ , C ₄ F ₈ , CHF ₃ , SF ₆ , NF ₃ or a mixture of the aforementioned etching gases. The method for manufacturing a high-hardness substrate as described in claim 2, wherein the dry etching temperature is controlled at 100 to 200∘C. The method for manufacturing a high-hardness substrate as described in claim 2, wherein the dry etching time is controlled between 15 and 50 minutes. The method for manufacturing a high-hardness substrate as claimed in claim 1, wherein the thickness removal rate of the dry etching is greater than 4.0 μm/hr. The method for manufacturing a high-hardness substrate as described in claim 6, wherein the thickness removal rate of the dry etching is between 6.0 μm/hr and 10.0 μm/hr. The method for manufacturing a high-hardness substrate as described in claim 1, wherein the surface roughness Ra of the surface of each wafer before dry etching is greater than 3.5nm; the surface roughness of the surface of each wafer after dry etching Ra is less than 2nm and the high and low morphology is distributed in a concentric circle. The method for manufacturing a high-hardness substrate as claimed in claim 1, wherein the wafers are sapphire, ceramic or diamond wafers with a-axis or r-axis. The method for manufacturing a high-hardness substrate as described in claim 1, wherein the thickness removal rate of each wafer by chemical mechanical polishing is between 0.3 μm/hr and 0.5 μm/hr. The manufacturing method of a high-hardness substrate as described in claim 1 includes dry etching on the front and back of each wafer, and chemical-mechanical polishing on the front and back of each wafer. A high-hardness substrate produced by the method for producing a high-hardness substrate described in any one of claims 1 to 11.