TW202336944A - Method of manufacturing package substrate for mounting semiconductor element - Google Patents

Abstract

To provide a method of manufacturing a package substrate for mounting a semiconductor element whereby it is possible to suppress damage when separating a core resin layer or during processing steps subsequent to separation. A first wiring conductor 12 through a (n+2)th wiring conductor 15B and a first insulating resin layer 13A through a (n+1)th insulating resin layer 15A are laminated on a first metal layer 11B that comprises a separation means in a first laminate 11 obtained by laminating a core resin layer 11A and the first metal layer 11B, a solder resist layer 16A is formed thereupon, and then at least the core resin layer is separated by the separation means.

Description

Method for manufacturing package substrate for mounting semiconductor elements

The present invention relates to a method of manufacturing a semiconductor element mounting packaging substrate on which a semiconductor element is mounted.

In recent years, the functionality and miniaturization of semiconductor packages widely used in electronic equipment, communication equipment, personal computers, etc. have been accelerated. Along with this, there is a demand for thinner printed wiring boards and semiconductor element mounting packaging substrates in semiconductor packages. As a thinned printed wiring board and a semiconductor element mounting package substrate, for example, a so-called coreless substrate is known, in which a metal layer and an insulating layer are laminated on a core resin layer, and the core resin layer is peeled off (for example, refer to patent Document 1). [Prior technical literature] [Patent Document]

[Patent Document 1] International Publication No. WO2020/121651

[Technical problem to be solved by the invention]

However, such a coreless substrate has the following problem: as the thickness of the metal layer and the insulating layer becomes thinner, the metal layer and the insulating layer may be damaged when the core resin layer is peeled off or during the processing steps after peeling off.

The present invention is based on the above problems, and aims to provide a method for manufacturing a semiconductor element mounting package substrate that can suppress damage when peeling off the core resin layer or during processing steps after peeling off. [Technical means]

The present invention is described below. [1] A method of manufacturing a packaging substrate for mounting semiconductor components, which includes: The first laminated body preparation step is to prepare a first laminated body having a core resin layer and a first metal layer provided on at least one side of the core resin layer and equipped with a peeling mechanism; The first wiring forming step is to apply at least one of electroplating and electroless plating on the first metal layer to form a first wiring conductor; The second laminate forming step includes sequentially laminating a first insulating resin layer and a second metal layer on the surface of the first wiring conductor on which the first laminate is provided to form a second laminate; In a second wiring forming step, a non-through hole is formed in the first insulating resin layer to reach the first wiring conductor, and at least one of electroplating and electroless plating is applied to the surface on which the non-through hole is formed to form the second wiring. conductor; In the wiring lamination step, after the aforementioned second wiring forming step, the (m+1)th insulating resin layer and the (m+2)th metal are further sequentially layered on the surface of the (m+1)th wiring conductor provided with the (m+1)th laminate. layer to form the (m+2)th laminated body forming step of forming the (m+2)th laminated body, and forming a non-through hole in the aforementioned (m+1)th insulating resin layer reaching the aforementioned (m+1)th wiring conductor, and forming the aforementioned non-through hole The surface of the through hole is subjected to at least one of electroplating and electroless plating to form the (m+2)-th wiring conductor in the (m+2) wiring forming step. These two steps are sequentially repeated n times to form a second insulating resin layer to The (n+1)th insulating resin layer, and the third wiring conductor to the (n+2)th wiring conductor (m and n are integers above 1, but m≦n); The solder resist layer forming step is to form a solder resist layer on the (n+1)th insulating resin layer and the (n+2)th wiring conductor in such a manner that the (n+2)th wiring conductor is partially exposed to form a solder resist layer formation body; as well as In the core resin layer peeling step, at least the core resin layer is peeled off from the solder resist layer forming body in the peeling mechanism to form a core resin layer removed body. [2] The method of manufacturing a semiconductor element mounting package substrate according to item [1], wherein the thickness of the core resin layer is 1 μm or more. [3] The method of manufacturing a semiconductor element mounting package substrate according to item [1], wherein the thickness of the first metal layer is 100 μm or less. [4] The method of manufacturing a semiconductor element mounting package substrate according to item [1], wherein the thickness of the first metal layer from the end surface on the side of the first wiring conductor to the peeling mechanism is 6 μm or more. [5] The method of manufacturing a semiconductor element mounting package substrate according to item [1], wherein the thickness of the first laminated body is 20 μm or more and 1000 μm or less. [6] The method of manufacturing a semiconductor element mounting package substrate according to item [1], wherein the thicknesses of the first to (n+1)th insulating resin layers are each from 0.1 μm to 100 μm. [7] The method for manufacturing a package substrate for mounting a semiconductor element as described in item [1], wherein the method for manufacturing a packaging substrate for mounting a semiconductor element includes a support substrate lamination step, which is performed after the solder resist layer forming step, and the core resin Before the layer peeling step, a support substrate having a thermoplastic resin layer is laminated on the surface of the solder resist layer on which the solder resist layer formation body is provided. [Effects of the invention]

According to the present invention, after the solder resist layer is formed on the (n+1)th insulating resin layer and the (n+2)th wiring conductor in such a manner that the (n+2)th wiring conductor is partially exposed, at least the core resin layer is peeled off by the peeling mechanism. The first to (n+2)th wiring conductors and the first to (n+1)th insulating resin layer can be reinforced by the solder resist layer, and such damage can be suppressed. Therefore, the package substrate for mounting a semiconductor element can be manufactured satisfactorily.

In addition, if at least the core resin layer 11A is peeled off after forming a solder resist layer and laminating a support substrate thereon, the first to (n+2)th wiring conductors 12 to 15B and the first insulating resin layer 13A can be more strongly reinforced. to the (n+1)th insulating resin layer 15A.

Furthermore, as long as the thickness of the first metal layer from the end surface on the side of the first wiring conductor to the peeling mechanism is 6 μm or more, the first wiring conductor can be more strongly reinforced when the peeling mechanism peels off at least the core resin layer. n+2) wiring conductors, and the first to (n+1)th insulating resin layers.

Modes for implementing the present invention (hereinafter referred to as "embodiments") will be described in detail below. However, the invention is not limited thereto, and various modifications are possible without departing from the gist of the invention.

[First implementation type] 1 to 3 are diagrams illustrating each step of a method of manufacturing a semiconductor element mounting package substrate according to the first embodiment. This method of manufacturing a package substrate for mounting a semiconductor element includes, for example, each of the steps described below (a first laminated body preparation step, a first wiring forming step, a second laminated body forming step, a second wiring forming step, a wiring lamination step, a resistor laminating step). Welding layer formation step, and core resin layer peeling step).

<First laminated body preparation step> First, for example, as shown in FIG. 1(A) , as a base substrate when forming a semiconductor element mounting package substrate, a core resin layer 11A and a surface side provided on at least one side of the core resin layer 11A and having a peel-off surface are prepared. The first laminated body 11 of the first metal layer 11B of the mechanism (first laminated body preparation step). In addition, FIG. 1 shows a case where the first metal layer 11B is provided on one surface side of the core resin layer 11A. Although not shown in the figure, the first metal layer 11B may also be provided on both sides of the core resin layer 11A.

(Core resin layer 11A) The core resin layer 11A is not particularly limited. For example, it may be composed of a prepreg in which a base material such as glass cloth is impregnated with an insulating resin material (insulating material) such as a thermosetting resin, or an insulating film material. The thickness of the core resin layer 11A can be appropriately set as needed and is not particularly limited. For example, it is ideally 1 μm or more. The reason is that if the thickness of the core resin layer 11A is less than 1 μm, the insulating resin layer formed in subsequent steps may be poorly formed.

"Prepreg" is a material in which a base material is impregnated or coated with an insulating material such as a resin composition. The base material is not particularly limited, and conventional base materials used for various electrically insulating material laminates can be suitably used. Examples of materials constituting the base material include inorganic fibers such as E glass, D glass, S glass, or Q glass; organic fibers such as polyimide, polyester, or tetrafluoroethylene; and mixtures thereof. The base material is not particularly limited, and base materials having shapes such as woven fabric, non-woven fabric, roving, strand felt, surface felt, etc. can be suitably used. The material and shape of the base material can be selected depending on the use and performance of the target molded article, and can be used alone or two or more types of materials and shapes as needed.

The thickness of the base material is not particularly limited as long as the thickness of the core resin layer 11A is within the above range. In addition, as the base material, a base material that has been surface-treated with a silane coupling agent or the like or a base material that has been mechanically opened can be used. These base materials are suitable in terms of heat resistance, moisture resistance, and processability.

The insulating material is not particularly limited, and a conventional resin composition used as an insulating material for a semiconductor element mounting package substrate can be appropriately selected and used. As the base of the resin composition, a thermosetting resin having excellent heat resistance and chemical resistance can be used. The thermosetting resin is not particularly limited, and examples thereof include polyimide resin, phenol resin, epoxy resin, cyanate ester resin, maleimide resin, modified polyphenylene ether, and bismaleimide resin. Azine resin, isocyanate resin, benzocyclobutene resin, and vinyl resin. One type of these thermosetting resins may be used alone, or two or more types may be mixed and used.

The polyimide resin is not particularly limited, and commercially available products can be appropriately selected and used. For example, a solvent-soluble polyimide resin or a block copolymerized polyimide resin synthesized by the manufacturing method described in Japanese Patent Application Laid-Open No. 2005-15629 can be used. Examples of the block copolymer polyimide resin include the block copolymer polyimide resin described in International Publication No. WO2010-073952. Specifically, the block copolymerized polyimide resin is not particularly limited as long as it is a copolymerized polyimide resin with the following structure alternately repeated: in the imine oligomer composed of the first structural unit The end of the structure A is bonded to the amide imine oligomer made of the second structural unit, and the end of the amide imine oligomer made of the second structural unit is bonded to the structure A made of the first structural unit. Structure B of acyl imine oligomer bond. In addition, the second structural unit is different from the first structural unit. These block copolymer polyimide resins can be formed by reacting tetracarboxylic dianhydride and diamine in a polar solvent to form imine oligomers, and then further adding tetracarboxylic dianhydride and another diamine. Amine, or another tetracarboxylic dianhydride and diamine, are synthesized by sequential polymerization reaction of imidization. One type of these polyimide resins may be used alone, or two or more types may be mixed and used.

The phenol resin is not particularly limited as long as it has one or more (ideally 2 to 12, more preferably 2 to 6, still more preferably 2 to 4, still more preferably 2 or 3, still more preferably 2) per molecule. As the compound or resin with phenolic hydroxyl group, commonly known phenol resin can be used. Examples include: bisphenol A type phenol resin, bisphenol E type phenol resin, bisphenol F type phenol resin, bisphenol S type phenol resin, phenol novolac resin, bisphenol A novolac type phenol resin, glycidyl ester type Phenol resin, aralkyl novolac type phenol resin, biphenyl aralkyl type phenol resin, cresol novolak type phenol resin, multifunctional phenol resin, naphthol resin, naphthol novolak resin, multifunctional naphthol resin, Anthracene type phenol resin, naphthalene skeleton modified novolak type phenol resin, phenol aralkyl type phenol resin, naphthol aralkyl type phenol resin, dicyclopentadiene type phenol resin, biphenyl type phenol resin, alicyclic phenol Resins, polyol-type phenol resins, phosphorus-containing phenol resins, and hydroxyl-containing silicone resins. One type of these phenolic resins may be used alone, or two or more types may be mixed and used.

Among thermosetting resins, epoxy resin is suitable as an insulating material because it has excellent heat resistance, chemical resistance, and electrical properties and is relatively cheap. As long as the epoxy resin has more than one (ideally 2 to 12, more preferably 2 to 6, still more preferably 2 to 4, still more preferably 2 or 3, still more preferably 2) epoxy groups in one molecule, The compound or resin is not particularly limited, and examples thereof include bisphenol A-type epoxy resin, bisphenol F-type epoxy resin, bisphenol S-type epoxy resin, alicyclic epoxy resin, and aliphatic chain epoxy. Resin, phenol novolak type epoxy resin, cresol novolak type epoxy resin, bisphenol A novolak type epoxy resin, diphenol diepoxypropyl etherate, naphthodiol diepoxypropyl ether compounds, diglycidyl etherates of phenols, diglycidyl etherates of alcohols, and these alkyl substitutes, halides, and hydrides. One type of these epoxy resins may be used alone, or two or more types may be mixed and used. In addition, the hardener used with the epoxy resin can be used without any limitation as long as it can harden the epoxy resin. Examples thereof include: polyfunctional phenols, polyfunctional alcohols, amines, imidazole compounds, acid anhydrides, organic Phosphorus compounds, and these halides. One type of these epoxy resin hardeners can be used alone, or two or more types can be mixed and used.

Cyanate ester resin is a resin that generates a cured product having a triazine ring as a repeating unit by heating, and the cured product has excellent dielectric properties. Therefore, it is suitable in situations where high-frequency characteristics are particularly required. The cyanate ester resin has at least one channel per molecule in the molecule (ideally 2 to 12, more preferably 2 to 6, still more preferably 2 to 4, still more preferably 2 or 3, still more preferably 2 ) Compounds or resins with aromatic moieties substituted by cyanooxy (cyanate group) are not particularly limited, and examples include: 2,2-bis(4-cyanooxyphenyl)propane, bis(4-cyano) Oxyphenyl)ethane, 2,2-bis(3,5dimethyl-4-cyanooxyphenyl)methane, 2,2-(4-cyanooxyphenyl)-1,1,1 , 3,3,3-hexafluoropropane, α,α'-bis(4-cyanooxyphenyl)-m-diisopropylbenzene, phenol novolac, and cyanate esters of alkylphenol novolac, etc. Among them, 2,2-bis(4-cyanooxyphenyl)propane is ideal because it has a particularly good balance between the dielectric properties and curability of the cured product and is also low in cost. One type of cyanate ester resin such as these cyanate ester compounds may be used alone, or two or more types may be mixed and used. In addition, a part of the aforementioned cyanate ester compound may be oligomerized into trimers or pentamers.

Furthermore, a curing catalyst or a curing accelerator may be used in combination with the cyanate ester resin. Examples of the hardening catalyst include metals such as manganese, iron, cobalt, nickel, copper, and zinc. Specific examples include organic metal salts such as 2-ethylhexanoate and octanoate, and acetyl acetone complexes. Organometallic complexes. One type of hardening catalyst may be used alone, or two or more types may be used in combination.

In addition, phenols are ideally used as hardening accelerators. Monofunctional phenols such as nonylphenol and p-cumylphenol can be used; bifunctional phenols such as bisphenol A, bisphenol F, and bisphenol S; or phenol novolak, cresol Novolac and other polyfunctional phenols, etc. One type of hardening accelerator may be used alone, or two or more types may be mixed and used.

The maleimide resin only needs to have more than one (ideally 2 to 12, more preferably 2 to 6, still more preferably 2 to 4, still more preferably 2 or 3, still more preferably 2) maleimide resin in one molecule. As a compound or resin based on a maleimide group, a commonly known maleimide resin can be used. Examples include: 4,4-diphenylmethanebismaleimide, phenylmethanebismaleimide, m-phenylbismaleimide, 2,2-bis(4-(4- Maleimide (phenoxy)-phenyl)propane, 3,3-dimethyl-5,5-diethyl-4,4-diphenylmethane bismaleimide, 4-methyl -1,3-phenylene bismaleimide, 1,6-bismaleimide-(2,2,4-trimethyl)hexane, 4,4-diphenyl ether bismaleimide Imide, 4,4-diphenyl bismaleimide, 1,3-bis(3-maleimidephenoxy)benzene, 1,3-bis(4-maleimide) Phenoxy)benzene, polyphenylmethane maleimide, novolak-type maleimide, biphenyl aralkyl-type maleimide, and prepolymers of these maleimide compounds , or a prepolymer of a maleimide compound and an amine compound, and is not particularly limited. One type of these maleimide resins may be used alone, or two or more types may be mixed and used.

Modified polyphenylene ether is useful from the viewpoint of improving the dielectric properties of the cured product. Modified polyphenylene ethers include, for example: poly(2,6-dimethyl-1,4-phenylene) ether, poly(2,6-dimethyl-1,4-phenylene) ether and poly(phenylene ether). Alloyed polymer of styrene, alloyed polymer of poly(2,6dimethyl-1,4-phenylene) ether and styrene-butadiene copolymer, poly(2,6-dimethyl -Alloy polymer of 1,4-phenylene) ether and styrene-maleic anhydride copolymer, alloy of poly(3,6-dimethyl-1,4-phenylene) ether and polyamide Polymers, alloyed polymers of poly(2,6-dimethyl-1,4-phenylene) ether and styrene-butadiene-acrylonitrile copolymer, oligomeric phenylene ethers, etc. In addition, in order to impart reactivity and polymerizability to polyphenylene ether, functional groups such as amine groups, epoxy groups, carboxyl groups, and styrene groups can be introduced at the end of the polymer chain, or amine groups, cyclic groups, etc. can be introduced into the side chains of the polymer chain. Functional groups such as oxygen group, carboxyl group, styryl group, and methacryl group.

The isocyanate resin is not particularly limited, and examples include isocyanate resins obtained by subjecting phenols and cyanogen halide to a dehydrohalogenation reaction. Examples of the isocyanate resin include 4,4'-diphenylmethane diisocyanate MDI, polymethylene polyphenyl polyisocyanate, tolylene diisocyanate, and hexamethylene diisocyanate. One type of these isocyanate resins may be used alone, or two or more types may be mixed and used.

The benzocyclobutene resin is not particularly limited as long as it contains a cyclobutene skeleton. For example, divinylsiloxane-bisbenzocyclobutene (manufactured by Dow Chemical Company) can be used. One type of these benzocyclobutene resins may be used alone, or two or more types may be mixed and used.

The vinyl resin is not particularly limited as long as it is a polymer or copolymer of a vinyl monomer. The vinyl monomer is not particularly limited, and examples thereof include: (meth)acrylate derivatives, vinyl ester derivatives, maleic acid diester derivatives, (meth)acrylamide derivatives, styrene derivatives, Vinyl ether derivatives, vinyl ketone derivatives, olefin derivatives, maleimine derivatives, (meth)acrylonitrile. One type of these vinyl resins may be used alone, or two or more types may be mixed and used.

Resin compositions used as insulating materials can also be blended with thermoplastic resins in consideration of dielectric properties, impact resistance, and film processability. The thermoplastic resin is not particularly limited, and examples thereof include fluororesin, polycarbonate, polyetherimide, polyetheretherketone, polyacrylate, polyamide, polyamideimide, and polybutadiene. One type of thermoplastic resin may be used alone, or two or more types may be mixed and used. In addition, the fluororesin is not particularly limited, and examples thereof include polytetrafluoroethylene, polychlorotrifluoroethylene, polyvinylidene fluoride, and polyvinyl fluoride. One type of these fluorine resins may be used alone, or two or more types may be mixed and used.

Among thermoplastic resins, polyamide imine resins are useful from the viewpoint of excellent moisture resistance and better adhesion to metals. The raw materials of the polyamide imine resin are not particularly limited. Examples of its acidic components include trimellitic anhydride and trimellitic anhydride monochloride; examples of its amine components include: m-phenylenediamine, p-phenylenediamine, and 4,4'-diaminodiamine. Phenyl ether, 4,4'-diaminodiphenylmethane, bis[4-(aminophenoxy)phenyl]terine, 2,2'-bis[4-(4-aminophenoxy)benzene base] propane, etc. Polyamide imine resin can also be modified with siloxane to improve dryness. In this case, siloxane diamine can be used as the amine component. If film processability is taken into consideration, it is ideal to use a polyamide imine resin with a molecular weight of 50,000 or more.

Regarding the above-mentioned thermoplastic resin, it is mainly used as an insulating material for prepregs, but these thermoplastic resins are not limited to use as prepregs. For example, what is processed into a film using the above-mentioned thermoplastic resin (film material) may be used as the core resin layer 11A.

Fillers can be mixed into the resin composition used as an insulating material. The filler is not particularly limited, and examples thereof include the following inorganic fillers (inorganic fillers): metal oxides (including hydrates) such as aluminum oxide, white carbon, titanium dioxide, titanium oxide, zinc oxide, magnesium oxide, and zirconium oxide. ; Metal hydroxides such as aluminum hydroxide, diaspore, magnesium hydroxide; natural silica, fused silica, synthetic silica, amorphous silica, fumed silica (Aerosil), hollow silica Silicon dioxide such as silicon oxide; clay, talc, mica, glass powder, quartz powder, volcanic ash ball (shirasu balloon), etc. In addition, the following organic fillers (organic fillers) can be listed: Styrene type , butadiene type, acrylic type, etc. rubber powder; core-shell type rubber powder; silicone resin powder, silicone rubber powder, silicon composite powder, etc. One type of these fillers may be used alone, or two or more types may be mixed and used.

Resin compositions used as insulating materials may also contain organic solvents. The organic solvent is not particularly limited. The following solvents may be used in combination as needed: aromatic hydrocarbon solvents such as benzene, toluene, xylene, and trimethylbenzene; ketone solvents such as acetone, methyl ethyl ketone, and methyl isobutyl ketone; such as Ether solvents of tetrahydrofuran; alcohol solvents such as isopropyl alcohol and butanol; ether alcohol solvents such as 2-methoxyethanol and 2-butoxyethanol; such as N-methylpyrrolidone, N,N-bis Methylformamide, N,N-dimethylacetylamine-based solvents, etc. Furthermore, when producing a prepreg, the amount of solvent in the varnish is preferably in the range of 40% by mass to 80% by mass relative to the entire resin composition. In addition, the viscosity of the varnish is preferably in the range of 20 cP to 100 cP (20 mPa･s to 100 mPa･s).

Resin compositions used as insulating materials may also contain flame retardants. The flame retardant is not particularly limited. For example, the following commonly used flame retardants can be used: decabromodiphenyl ether, tetrabromobisphenol A, tetrabromophthalic anhydride, tribromophenol and other bromine compounds; triphenyl phosphate Phosphorus compounds such as ester, tri(xylene) phosphate, toluene diphenyl phosphate; red phosphorus and its modified products; antimony compounds such as antimony trioxide and antimony pentoxide; melamine, cyanuric acid, cyanuric acid Triazine compounds such as acid melamine, etc.

In the resin composition used as an insulating material, the above-mentioned hardener, hardening accelerator, or other various additives and fillers such as thermoplastic particles, colorants, ultraviolet opaque agents, antioxidants, reducing agents, etc. may be added as necessary. .

The prepreg in this embodiment is, for example, such that the adhesion amount of the resin composition to the base material is such that the resin content in the prepreg after drying is 20 mass % or more and 90 mass % or less, and the base material is After being impregnated or coated with a resin composition (including varnish), the prepreg is heated and dried at a temperature of 100°C or more and 200°C or less for 1 to 30 minutes, thereby obtaining a prepreg in a semi-hardened state (B-stage state). As such prepregs, for example, GHPL-830NS (product name) and GHPL-830NSF (product name) manufactured by Mitsubishi Gas Chemical Co., Ltd. can be used.

(First metal layer 11B) The first metal layer 11B may be composed of a metal foil with a carrier, for example. The metal foil with a carrier is, for example, a metal foil laminated on a carrier through a peeling layer as a peeling mechanism. A commercially available metal foil with a carrier may be used. For example, MT18SD-H-T5 (product name) manufactured by Mitsui Metal Mining Co., Ltd. can be used. The thickness of the first metal layer 11B is preferably, for example, 100 μm or less. The reason is that in order to form fine wiring, it is advantageous to have a thin metal layer. In addition, it is more preferable that the thickness of the first metal layer 11B is 0.5 μm or more. Furthermore, it is more preferable that the thickness of the first metal layer 11B is not less than 1 μm and not more than 100 μm.

The carrier may be made of various metal foils, for example. However, from the viewpoint of thickness uniformity, corrosion resistance of the foil, etc., it is preferably made of copper foil. The thickness of the carrier is thicker than the thickness of the metal foil, and may be, for example, 3 μm or more and 100 μm or less, preferably 5 μm or more and 50 μm or less, and more preferably 6 μm or more and 30 μm or less.

The release layer is used to allow the carrier to be easily released from the metal foil. The material of the release layer is not particularly limited, and various conventional materials can be suitably used. For example, if it is an organic material, a nitrogen-containing organic compound, a sulfur-containing organic compound, a carboxylic acid, etc. may be mentioned. Examples of nitrogen-containing organic compounds include triazole compounds, imidazole compounds, and the like. Among them, triazole compounds are preferred because they have easy and stable peelability. Examples of triazole compounds include: 1,2,3-benzotriazole, carboxybenzotriazole, N',N'-bis(benzotriazolylmethyl)urea, 1H-1,2,4 -Triazole, and 3-amino-1H-1,2,4-triazole, etc. Examples of sulfur-containing organic compounds include mercaptobenzothiazole, thiocyanate, 2-benzimidazolethiol, and the like. Examples of the carboxylic acid include monocarboxylic acid, dicarboxylic acid, and the like. In addition, inorganic materials include metals or alloys made of at least one of Ni, Mo, Co, Cr, Fe, Ti, W, P, Zn, etc., or these oxides. The thickness of the peeling layer can be, for example, 1 nm or more and 1 μm or less, preferably 5 nm or more and 500 nm or less.

The metal foil may be composed of various metal foils, for example. However, from the viewpoint of uniformity of thickness, corrosion resistance of the foil, etc., it is preferably composed of copper foil. The thickness of the metal foil can be appropriately set depending on the needs and is not particularly limited. For example, it can be 0.5 μm or more and 70 μm or less, preferably 1 μm or more and 50 μm or less, and more preferably 6 μm or more and 30 μm or less.

The first metal layer 11B can be configured so that the carrier is on the side of the core resin layer 11A, or it can be configured so that the metal foil is on the side of the core resin layer 11A. The thickness of the first metal layer 11B from the end surface on the opposite side to the core resin layer 11A to the peeling mechanism, that is, the thickness from the end surface on the side of the first wiring conductor 12 to be described later to the peeling mechanism is preferably 6 μm or more. If it is 10 μm or more, More preferably, it is 15 μm or more. The reason is that when at least the core resin layer 11A is peeled off in the core resin layer peeling step described later, the first wiring conductor 12 to the (n+2)th wiring conductor 15B and the first insulating resin layer 13A to the (n+1)th insulation can be reinforced. The resin layer 15A prevents such damage. In addition, the thickness from the end surface on the side opposite to the core resin layer 11A to the peeling mechanism in the first metal layer 11B, that is, the thickness from the end surface on the side of the first wiring conductor 12 to be described later to the peeling mechanism is preferably 70 μm or less. If it is 50 μm, It is more preferable that it is 30 μm or less, and it is even more preferable that it is 30 μm or less. The reason is that it is time-consuming to remove the remaining first metal layer 11B in the first metal layer removal step described later.

In addition, the first metal layer 11B may be composed of a metal foil having a peeling layer as a peeling mechanism. In this case, a peeling layer is laminated on the side of the core resin layer 11A. Examples of the peelable layer include a layer containing at least a silicon compound. For example, it can be formed by providing a silicon compound composed of a single or a plurality of silane compounds on a metal foil. In addition, the means for imparting the silicon compound is not particularly limited, and for example, conventional means such as coating can be used. Anti-rust treatment (forming an anti-rust treatment layer) can be applied to the interface with the peeling layer of the metal foil. The anti-rust treatment can be performed using any one of nickel, tin, zinc, chromium, molybdenum, cobalt, or alloys thereof. The thickness of the peeling layer is not particularly limited, but from the viewpoint of removability and peelability, it is preferably 5 nm to 100 nm, more preferably 10 nm to 80 nm, and particularly preferably 20 nm to 60 nm. In addition, the metal foil is preferably a copper foil from the viewpoints of uniformity of thickness and corrosion resistance of the foil. In this case, the thickness from the end surface on the opposite side to the core resin layer 11A to the peeling mechanism in the first metal layer 11B, that is, the thickness from the end surface on the side of the first wiring conductor 12 to be described later to the peeling mechanism is preferably as described above. .

Moreover, the first laminated body 11 can be produced, for example, by laminating the core resin layer 11A and the first metal layer 11B and applying heat and pressure to press-bond them. The thickness of the first laminated body 11 may be, for example, 20 μm or more and 1000 μm or less, preferably 20 μm or more and 950 μm or less, and more preferably 20 μm or more and 900 μm or less.

<First wiring formation step> Next, for example, as shown in FIG. 1(B) , at least one of electroplating and electroless plating is applied to the first metal layer 11B of the first laminated body 11 to form the first wiring conductor 12 (first wiring forming step) . Specifically, it can be formed by, for example, the following steps: laminating a plating photoresist on the first metal layer 11B, baking a circuit pattern on the plating photoresist and developing it to form a plating photoresist pattern, and then applying Pattern plating is performed to form the first wiring conductor 12, and then the plating photoresist is removed.

The photoresist used for plating is not particularly limited. For example, a commercially available dry film photoresist or other conventional photoresist may be appropriately selected. In addition, the baking, development, and removal of the photoresist for plating are not particularly limited, and can be implemented using conventional means and devices. Moreover, the pattern plating used to form the first wiring conductor 12 is not particularly limited, and a conventional method can be suitably used. The first wiring conductor 12 is preferably formed by copper plating.

The thickness of the first wiring conductor can be appropriately set as needed and is not particularly limited. For example, it may be 0.5 μm or more and 100 μm or less, preferably 1 μm or more and 50 μm or less, and more preferably 1 μm or more and 30 μm or less. The pattern width of the first wiring conductor is not particularly limited and can be appropriately selected depending on the application. For example, it can be 1 μm or more and 100 μm or less, and ideally it can be 3 μm or more and 30 μm or less.

<Second laminated body formation step> Next, for example, as shown in FIG. 1(C) , the first insulating resin layer 13A and the second metal layer 13B are sequentially laminated on the surface of the first wiring conductor 12 provided with the first laminated body 11 to form Second laminated body 13 (second laminated body forming step).

The first insulating resin layer 13A is not particularly limited, and may be made of the same material as the core resin layer 11A (for example, a prepreg or an insulating film material). The thickness of the first insulating resin layer 13A can be appropriately set as needed and is not particularly limited. For example, it can be 0.1 μm or more and 100 μm or less, preferably 3 μm or more and 50 μm or less, and more preferably 5 μm or more and 20 μm or less.

The second metal layer 13B may be composed of various metal foils, but is preferably composed of copper foil from the viewpoints of uniformity of thickness and corrosion resistance of the foil. The thickness of the second metal layer 13B can be appropriately set as needed and is not particularly limited. For example, it can be 0.5 μm or more and 100 μm or less, preferably 1 μm or more and 50 μm or less, and more preferably 1 μm or more and 30 μm or less.

The second laminated body formation step is not particularly limited, and can be performed by the following steps, for example. For example, as an adhesion treatment for obtaining close adhesion with the first insulating resin layer 13A, the surface of the first wiring conductor 12 is roughened, and then the resin layer is in contact with the first wiring conductor 12 The first insulating resin layer 13A and the second metal layer 13B can be laminated by arranging a metal foil with a resin layer and a metal foil with a carrier, heating and pressing, and peeling off the carrier. The roughening treatment is not particularly limited, and conventional means can be suitably used. For example, means using a copper surface roughening liquid can be used.

The metal foil with a carrier with a resin layer is, for example, a resin layer laminated on the metal foil side of the metal foil with a carrier. The resin layer becomes the first insulating resin layer 13A, and the metal foil becomes the second metal layer 13B. A commercially available metal foil with a resin layer and a carrier can be used. For example, CRS381NSI (product name) manufactured by Mitsubishi Gas Chemical Co., Ltd. can be used. The heating and pressurizing conditions of the carrier-attached metal foil with the resin layer are not particularly limited. For example, vacuum pressurization can be performed at a temperature of 220±2°C, a pressure of 3±0.2MPa, and a holding time of 60 minutes.

<Second wiring formation step> Then, for example, as shown in FIG. 1(D) , a non-through hole 14A reaching the first wiring conductor 12 is formed in the first insulating resin layer 13A, and at least one of electroplating and electroless plating is applied to the surface on which the non-through hole is formed. One to form the second wiring conductor 14B (second wiring forming step). The thickness and pattern width of the second wiring conductor 14B can be appropriately set as needed and are not particularly limited. For example, they can be the same as the first wiring conductor 12 .

The means for forming the non-through hole 14A is not particularly limited, and for example, conventional means such as laser such as carbon dioxide laser or drilling can be used. Among them, it is ideal to form the non-through hole 14A by laser. The reason is that it is suitable for micromachining. The non-through hole 14A is formed in the first insulating resin layer 13A through the second metal layer 13B, and is provided to electrically connect the second wiring conductor 14B formed in this step to the first wiring conductor 12 . The number and size of the non-through holes 14A can be appropriately selected as needed. In addition, after the non-through hole 14A is formed, a desmear treatment may be performed using a sodium permanganate aqueous solution or the like.

After the non-through hole 14A is formed, at least one of electroplating and electroless plating is applied to form a plating film on the inner wall of the non-through hole 14A, so that the first wiring conductor 12 and the second metal layer 13B are electrically connected while adding a second The thickness of the metal layer 13B allows the second wiring conductor 14B to be formed. The method of electroplating copper or electroless copper plating is not particularly limited, and conventional methods can be used. Plating may be performed by either electroplating or electroless plating, but ideally it is performed by both electroplating and electroless plating. Furthermore, the plating is preferably copper plating, and preferably at least one of electrolytic copper plating and electroless copper plating is applied.

The formation method of the second wiring conductor 14B is not particularly limited, and for example, a conventional method such as a subtractive method or a semi-additive method may be suitably used. In the case of the subtractive method, for example, first, the non-through holes 14A are formed, and at least one of electroplating and electroless plating is applied to the surface on which the non-through holes are formed to increase the thickness of the second metal layer 13B, and then surface plating is performed as necessary. Trim. Then, for example, a dry film photoresist is laminated, a negative photomask is attached, the circuit pattern is baked and developed, thereby forming an etching photoresist. Next, for example, using the etching photoresist as a photomask, the second metal layer 13B whose thickness has been increased is etched to form the second wiring conductor 14B, and then the etching photoresist is removed.

In addition, in the case of the semi-additive method, for example, first, after forming the non-through hole 14A, the second metal layer 13B is completely removed by etching or the like to expose the first insulating resin layer 13A. Next, electroless copper plating is applied to the surface on the side of the first insulating resin layer 13A to form an electroless copper plating layer with a thickness of, for example, 0.4 μm to 2 μm. Next, a dry film is thermocompressed on the electroless copper plating layer and a photoresist layer is provided, and then exposed and developed to form a photoresist pattern in which the portion forming the second wiring conductor 14B has been removed. Exposure is performed, for example, by irradiating active energy rays to a designated portion of the photoresist layer. The irradiation of active energy rays can be through a mask pattern, or a direct drawing method of directly irradiating active energy rays can be used. After the photoresist pattern is formed, the residue (photoresist residue) is removed by, for example, plasma cleaning, and the photoresist pattern is used as a plating photoresist. An electroplated copper layer is formed by electroplating copper on the surface of the electroless copper layer. . After the electroplated copper layer is provided, the photoresist pattern is removed using a photoresist stripper, and the electroless copper layer is etched by flash etching or the like to form an electroless copper layer and an electroplated copper layer. The second wiring conductor 14B is formed.

＜Wiring Layer Steps＞ After the second wiring forming step, for example, as shown in FIG. 2(E) , the second laminated body forming step and the second wiring are further repeated on the surface of the second wiring conductor 14B on which the second laminated body 13 is provided. The same conductor forming steps are performed n times to form a build-up structure (wiring build-up step) having (n+2) layers of wiring conductors. n is an integer greater than 1. The number of repetitions n can be appropriately set as needed and is not particularly limited. For example, it can be 1 or more times and 10 times or less. In addition, FIG. 2 shows a case where the number of repetitions n is three times.

Specifically, in the wiring lamination step, for example, the (m+1)th insulating resin layer 15A and the (m+2)th metal layer are sequentially stacked on the surface of the (m+1)th wiring conductor provided with the (m+1)th laminate. In the (m+2)-th laminated body forming step of forming the (m+2)-th laminated body 15, a non-through hole reaching the (m+1)-th wiring conductor is formed in the (m+1)-th insulating resin layer 15A, and the non-through hole is formed on the The surface is subjected to at least one of electroplating and electroless plating to form the (m+2)th wiring conductor 15B in the (m+2)th wiring forming step. These two steps are sequentially repeated n times to form the second to (n+1)th insulation. Resin layer 15A, and third to (n+2) wiring conductors 15B. m is an integer above 1, but m≦n.

＜Solder resist layer formation step＞ After the wiring lamination step, for example, as shown in FIG. 2(F) , a solder resist layer is formed on the (n+1)th insulating resin layer 15A and the (n+2)th wiring conductor 15B such that the (n+2)th wiring conductor 15B is partially exposed. 16A, thereby forming the solder resist layer forming body 16 (solder resist layer forming step). By forming the solder resist layer 16A before the subsequent core resin layer peeling step, when at least the core resin layer 11A is peeled off, and when the first metal layer 11B is removed in the first metal layer removal step after peeling off, the first metal layer 11B can be reinforced. wiring conductor 12 to (n+2)th wiring conductor 15B, and first insulating resin layer 13A to (n+1)th insulating resin layer 15A.

The method of forming the solder resist layer 16A is not particularly limited, and conventional means can be appropriately used. For example, the solder resist layer 16A can be formed by applying the solder resist on the (n+1)-th insulating resin layer 15A and the (n+2)-th wiring conductor 15B, that is, on the (n+2)-th laminated body 15 formed thereon. The entire surface of the (n+2) wiring conductor 15B is exposed and hardened through a negative film on which a circuit pattern has been formed, and then the unhardened portion is developed. In addition, for example, the solder resist layer 16A can also be formed by printing a solder resist pattern on the (n+1)-th insulating resin layer 15A and the (n+2)-th wiring conductor 15B by screen printing, that is, the pattern is printed on The surface on which the (n+2)th wiring conductor 15B of the (n+1)th laminated body 15 is formed is irradiated with ultraviolet rays or heated to be hardened. That is, the solder resist layer 16A is a layer after hardening treatment. In this way, since the solder resist layer 16A has been hardened, possible contamination in subsequent steps can be suppressed.

＜Core resin layer peeling step＞ After the solder resist layer forming step, for example, as shown in FIG. 2(G) , at least the core resin layer 11A is peeled off and removed from the solder resist layer forming body 16 by the peeling mechanism of the first metal layer 11B. Thereby, a part of the core resin layer 11A and optionally the first metal layer 11B (such as a carrier) are peeled off in a peeling mechanism (such as a peeling layer or a peeling layer), and a laminated layer is formed on the remaining first metal layer 11B. The core resin layer remover 17 of the first to (n+2)th wiring conductors 12 to 15B, the first to (n+1)th insulating resin layers 13A to 15A, and the solder resist layer 16A (core resin layer peeling step). In this embodiment, since the hardened solder resist layer 16A is provided, sufficient strength can be obtained and damage can be suppressed. In addition, at least part of the peeling mechanism of the first metal layer 11B may be peeled off together with at least the core resin layer 11A, or may remain without being peeled off. The means for peeling off at least the core resin layer 11A by the peeling mechanism can be either physical means or chemical means, but it is desirable to apply physical force to the peeling mechanism and perform peeling by physical means, for example.

<First metal layer removal step> After the core resin layer peeling step, for example, as shown in FIG. 3(H) , the remaining first metal layer 11B is removed from the core resin layer removal body 17 to form the first metal layer removal body 18 (first metal layer removal step ). The means for removing the first metal layer 11B is not particularly limited. For example, it can be removed using a sulfuric acid-based or hydrogen peroxide-based etching solution. The sulfuric acid-based or hydrogen peroxide-based etching liquid is not particularly limited, and any etching liquid used in the industry can be used. In addition, in this embodiment, since the solder resist layer 16A has been hardened, damage caused by the chemical liquid can be reduced.

＜Reverse solder mask formation steps＞ After the first metal layer removal step, for example, as shown in FIG. 3(I) , a solder resist layer 19 is formed on the first insulating resin layer 13A and the first wiring conductor 12 in such a manner that the first wiring conductor 12 is partially exposed (reverse side). Solder mask formation step). The formation method of the solder resist layer 19 is the same as the formation step of the solder resist layer.

＜Plating Processing Steps＞ After the reverse solder resist layer formation step, for example, on both sides of the first metal layer removal body 18, on the first wiring conductor 12 exposed from the solder resist layer 19, and on the (n+2)th wiring conductor 15B exposed from the solder resist layer 16A A gold plating layer is formed on it. Thereby, a package substrate for mounting a semiconductor element can be obtained.

In this way, according to this embodiment, after the solder resist layer 16A is formed on the (n+1)-th insulating resin layer 15A and the (n+2)-th wiring conductor 15B such that the (n+2)-th wiring conductor 15B is partially exposed, it is peeled off. The mechanism peels off at least the core resin layer 11A, so the first to (n+2)th wiring conductors 12 to 15B and the first to (n+1)th insulating resin layers 13A to 15A can be reinforced by the solder resist layer 16A. And can inhibit such damage. Therefore, the package substrate for mounting a semiconductor element can be manufactured satisfactorily.

In addition, since the solder resist layer 16A has been hardened, possible contamination in subsequent steps can be suppressed, and sufficient strength and liquid resistance can be obtained.

Furthermore, if the thickness of the first metal layer 11B from the end surface on the first wiring conductor 12 side to the peeling mechanism is 6 μm or more, further 10 μm or more, and further 15 μm or more, when at least the core resin layer 11A is peeled off, , the first to (n+2)th wiring conductors 12 to 15B, and the first to (n+1)th insulating resin layers 13A to 15A can be further reinforced.

[Second implementation type] A method for manufacturing a package substrate for mounting a semiconductor element according to a second embodiment of the present invention includes a support substrate lamination step between the solder resist layer forming step and the core resin layer peeling step of the first embodiment, and in the first embodiment The metal layer removal step is followed by a support substrate removal step. Other steps (first laminated body preparation step, first wiring forming step, second laminated body forming step, second wiring forming step, wiring laminating step, solder resist layer forming step, core resin layer peeling step, first metal layer The removal step, the reverse solder resist layer forming step, and the plating processing step) are the same as those in the first embodiment.

4 and 5 are diagrams showing each step of a method of manufacturing a semiconductor element mounting package substrate according to the second embodiment. In this method of manufacturing a package substrate for mounting a semiconductor element, first, for example, a first laminated body preparation step, a first wiring forming step, a second laminated body forming step, and a second wiring forming step are performed in the same manner as in the first embodiment. The wiring lamination step and the solder resist layer formation step.

＜Support substrate lamination step＞ After the solder resist layer forming step, for example, as shown in FIG. 4 (F-1), a support substrate 20A having a thermoplastic resin layer is laminated on the surface of the solder resist layer 16A provided with the solder resist layer forming body 16. The support substrate laminate 20 is formed (support substrate lamination step). The support substrate 20A is formed together with the solder resist layer 16A when at least the core resin layer 11A is peeled off in the subsequent core resin layer peeling step, and when the first metal layer 11B is removed in the first metal layer removal step after peeling off. The first to (n+2)th wiring conductors 12 to 15B and the first to (n+1)th insulating resin layers 13A to 15A are reinforced. In addition, as will be described later, the support substrate 20A is removed after at least the core resin layer 11A is peeled off.

The support substrate 20A may have, for example, a thermosetting resin layer in addition to the thermoplastic resin layer, or may be composed of only the thermoplastic resin layer. The reason is that compared to thermosetting resins, thermoplastic resins have higher toughness and can achieve higher strength. The material of the thermoplastic resin layer is not particularly limited, and examples thereof include dry film photoresist. Among them, the thermoplastic resin layer is preferably composed of a photosensitive resin layer made of a photosensitive thermoplastic resin. The reason is that it can be used in the wiring conductor forming step. Examples of the photosensitive thermoplastic resin include dry film photoresist used for patterning. In addition, the thermoplastic resin layer can be composed of, for example, a UV peelable resin layer or a thermally peelable resin layer, and is preferably composed of at least one selected from the group consisting of a photosensitive resin layer, a UV peelable resin layer, and a thermally peelable resin layer. One kind.

The support substrate 20A can be, for example, a film-like or sheet-like support substrate 20A disposed on the surface of the solder resist layer 16A on which the solder resist layer forming body 16 is provided, and can be press-bonded and laminated by lamination. In addition, when the thermoplastic resin layer is composed of a photosensitive resin layer, the step of laminating the photosensitive resin layer may include, for example, the following step: arranging the solder resist layer forming body 16 on the surface of the solder resist layer 16A. After laminating the photosensitive resin layer, the entire surface of the photosensitive resin layer is exposed and cured. By exposing and curing the entire surface of the photosensitive resin layer, the adhesion to the (n+1)th insulating resin layer 15A and the (n+2)th wiring conductor 15B can be improved. When the thermoplastic resin layer is composed of a UV peelable resin layer or a heat peelable resin layer, the step of laminating the UV peelable resin layer or the heat peelable resin layer may include, for example, the following steps: providing a solder resist layer A UV releasable resin layer or a thermal releasable resin layer is disposed on the surface of the solder resist layer 16A of the formed body 16 and laminated. The thickness of the support substrate 20A can be appropriately set as needed and is not particularly limited. For example, it may be 1 μm or more, preferably 1 μm or more and 50 μm or less, and more preferably 1 μm or more and 30 μm or less.

<Core resin layer peeling step and first metal layer removal step> After the support substrate lamination step, for example, as shown in FIG. 4(G) , the peeling mechanism of the first metal layer 11B removes at least the core resin layer 11A from the support substrate laminate 20 , that is, from the peeling mechanism of the first metal layer 11B. The solder resist layer forming body 16 of the laminated support substrate 20A is peeled off to form the core resin layer removed body 17 (core resin layer peeling step). Next, for example, as shown in FIG. 5 (H-1), the remaining first metal layer 11B is removed in the same manner as in the first embodiment to form the first metal layer removal body 18 (first metal layer removal step ).

<Support substrate removal step> After the first metal layer removal step, for example, as shown in FIG. 5 (H-2), the support substrate 20A is removed from the first metal layer removal body 18 to form the support substrate removal body 21 (support substrate removal step). The means for removing the support substrate 20A is not particularly limited, and can be appropriately selected depending on the material of the support substrate 20A. The support substrate 20A can be removed by, for example, a chemical solution such as sodium hydroxide aqueous solution, a laser, or a plasma treatment; for example, in the case of a UV peelable resin layer, it can be removed by irradiation. It can be peeled off and removed by using light in the ultraviolet range, and in the case of a heat-peelable resin layer, it can be peeled off and removed by heat treatment.

After the support substrate removal step, for example, the reverse solder resist layer forming step and the plating processing step are performed in the same manner as in the first embodiment. Thereby, a package substrate for mounting a semiconductor element can be obtained.

Thus, according to this embodiment, after the solder resist layer 16A is formed on the (n+1)-th insulating resin layer 15A and the (n+2)-th wiring conductor 15B and the support substrate 20A is laminated, at least the core resin layer 11A is removed by the peeling mechanism Therefore, the first to (n+2)th wiring conductors 12 to 15B and the first to (n+1)th insulating resin layers 13A to 15A can be more strongly reinforced, and such damage can be suppressed. [Example]

In the following, this implementation type will be specifically described through examples, but this implementation type is not limited by these examples.

[Example 1] A semiconductor element mounting package substrate is produced as follows. <First laminated body preparation step> (Refer to Figure 1(A)) Glass cloth (glass fiber) is impregnated with bismaleimidetriazine resin (BT resin) to form a B-stage prepreg (thickness 0.100mm: manufactured by Mitsubishi Gas Chemical Co., Ltd., product name: GHPL-830NS ST56) As the core resin layer 11A, an ultra-thin copper foil with a carrier copper foil having a thickness of 18 μm as the first metal layer 11B (ultra-thin copper foil; thickness 5 μm: manufactured by Mitsui Metal Mining Co., Ltd., product name: MT18SD- H-T5) is placed on both sides of the core resin layer 11A so that the carrier copper foil side is in contact with the core resin layer 11A, and vacuum heating is performed under the conditions of a temperature of 220±2°C, a pressure of 3±0.2MPa, and a holding time of 60 minutes. By pressing, the first laminated body 11 in which the first metal layer 11B is provided on both sides of the core resin layer 11A is produced.

<First wiring formation step> (Refer to Fig. 1(B)) Dry film photoresist LDF515F (product name, manufactured by Nikko-Materials Co., Ltd.) with a thickness of 15 μm was laminated on the first laminate 11 at a temperature of 110±10°C and a pressure of 0.50±0.02MPa. After baking the circuit pattern on the dry film photoresist using a parallel exposure machine, the dry film photoresist is developed using 1% sodium carbonate aqueous solution to form a photoresist pattern for plating. Next, a copper sulfate plated wire with a copper sulfate concentration of 60 g/L to 80 g/L and a sulfuric acid concentration of 150 g/L to 200 g/L is electroplated with copper in a pattern of about 5 μm to 20 μm (electroplating copper) to form the first wiring conductor 12 . Subsequently, an amine-based photoresist stripper is used to strip off the dry film photoresist.

<Second laminated body formation step> (Refer to Figure 1(C)) In order to obtain close adhesion with the insulating resin, the surface of the first wiring conductor 12 is roughened using copper surface roughening liquid CZ-8101 (product name, manufactured by MEC Co., Ltd.). Next, the copper foil with the resin layer has a thickness of 18 μm and the ultra-thin copper foil with the carrier copper foil (ultra-thin copper foil (metal layer); thickness 2 μm, resin layer thickness 0.015 mm: Mitsubishi Gas Chemical Co., Ltd. product name : CRS381NSI) is disposed on both sides of the first laminated body 11 on which the first wiring conductor 12 is formed in such a manner that the resin layer is in contact with the first wiring conductor 12, under a pressure of 3±0.2MPa, a temperature of 220±2°C, and a holding time of 60 Carry out vacuum pressurization under conditions of minutes. Subsequently, the 18 μm-thick carrier copper foil was peeled off to obtain the second laminated body 13 in which the first insulating resin layer 13A and the 2-μm-thick second metal layer 13B were laminated on the first wiring conductor 12 .

<Second Wiring Formation Step> (Refer to Fig. 1(D)) On both sides of the second laminated body 13, a carbon dioxide laser processing machine ML605GTWIII-5200U (manufactured by Mitsubishi Electric Co., Ltd., product name) was used, and the beam irradiation diameter was Φ0.06mm, the frequency was 500Hz, the pulse width was 15μs, and the number of irradiations was once. The non-through hole 14A reaching the first wiring conductor 12 is formed in the first insulating resin layer 13A through the second metal layer 13B by processing one hole at a time.

Next, the second laminated body 13 with the non-through holes 14A was desmeared using an aqueous sodium permanganate solution with a temperature of 80±5°C and a concentration of 55±10 g/L, and further electroless copper plating of 0.4 μm was performed. After plating to a thickness of ~0.8 μm, electroplating copper is used to plating to a thickness of 5 μm to 20 μm. Thereby, the inner walls of the non-through hole 14A are connected by plating, so that while the first wiring conductor 12 and the second metal layer 13B are electrically connected due to the plating of the inner wall of the non-through hole 14A, the thickness of the second metal layer 13B is Increase.

Then, the second metal layer 13B was surface-modified, and dry film photoresist LDF515F (product name, manufactured by Nikko-Materials Co., Ltd.) was laminated at a temperature of 110±10°C and a pressure of 0.50±0.02MPa. Subsequently, the negative photomask is attached, a parallel exposure machine is used to bake the circuit pattern, and a 1% sodium carbonate aqueous solution is used to develop the dry film photoresist to form an etching photoresist. Next, the non-etched photoresist portion of the second metal layer 13B is etched and removed with a ferric chloride aqueous solution, and then a sodium hydroxide aqueous solution is used to remove the dry film photoresist, thereby forming the second wiring conductor 14B.

<Wiring Layer Steps> (Refer to Figure 2(E)) The same steps as the second laminated body forming step and the second wiring conductor forming step are repeated three times to form the fifth laminated body 15 having a build-up structure of five layers of wiring conductors.

<Solder resist layer formation step> (Refer to Figure 2(F)) After the wiring lamination step, a solder resist layer 16A with a thickness of 10 μm is formed on the fourth insulating resin layer 15A and the fifth wiring conductor 15B such that the fifth wiring conductor 15B is partially exposed, thereby obtaining the solder resist layer forming body 16 .

<Core resin layer peeling step> (Refer to Figure 2(G)) After the solder resist layer formation body 16 is obtained, physical force is applied to the boundary between the ultra-thin copper foil and the carrier copper foil of the first metal layer 11B to peel and remove at least the core resin layer 11A from the solder resist layer formation body 16 . Thereby, a set of core resin layer-removed bodies 17 is obtained.

<First Metal Layer Removal Step> (Refer to Figure 3(H)) After the core resin layer removed body 17 is obtained, the remaining first metal layer 11B (ultra-thin copper foil) is removed using a perhydrated sulfuric acid-based soft etching solution, thereby obtaining the first metal layer removed body 18 .

<Solder resist layer formation step> (Refer to Figure 3(I)) After the first metal layer removal body 18 is obtained, a solder resist layer 19 with a thickness of 10 μm is formed on the first insulating resin layer 13A and the first wiring conductor 12 so that the first wiring conductor 12 is partially exposed.

＜Plating Processing Steps＞ After the solder resist layer 19 is formed, a gold plating layer is formed on the first wiring conductor 12 or the fifth wiring conductor 15B exposed from the solder resist layers 16A and 19, thereby obtaining a semiconductor element mounting package substrate. According to this example, no damage was observed in the first to fifth wiring conductors 12 to 15B and the first to fourth insulating resin layers 13A to 15A, and the semiconductor element mounting package substrate can be manufactured satisfactorily.

[Example 2] The first laminated body preparation step (refer to FIG. 1(A)), the first wiring forming step (refer to FIG. 1(B)), and the second laminated body forming step (refer to FIG. 1(C)) were performed in the same manner as in Example 1. , a second wiring forming step (refer to FIG. 1(D)), a wiring lamination step (refer to FIG. 2(E)), and a solder resist layer forming step (refer to FIG. 2(F)). Next, on the surface provided with the solder resist layer 16A, a dry film photoresist with a thickness of 15 μm is laminated as a photosensitive resin layer (thermoplastic resin layer) under the conditions of a temperature of 110±10°C and a pressure of 0.50±0.02MPa. LDF515F (product name, manufactured by Nikko-Materials Co., Ltd.) is used as the support substrate 20A. Subsequently, the entire surface is exposed and hardened using a parallel exposure machine, thereby obtaining the support substrate laminated body 20 on which the support substrate 20A has been laminated (support substrate lamination step; see FIG. 4 (F-1)).

After the support substrate laminate 20 is obtained, the core resin layer peeling step (see FIG. 4(G) ) and the first metal layer removing step (see FIG. 5(H) ) are performed in the same manner as in Example 1. Next, the dry film photoresist serving as the supporting substrate 20A is removed using a sodium hydroxide aqueous solution (supporting substrate removal step; see FIG. 5(I) ). Subsequently, a plating process step was performed in the same manner as in Example 1, thereby obtaining a semiconductor element mounting package substrate. In this example, no damage was observed in the first to fifth wiring conductors 12 to 15B and the first to fourth insulating resin layers 13A to 15A, and the semiconductor element mounting package substrate could be manufactured satisfactorily.

[Comparative example 1] After performing the first laminated body preparation step, the first wiring forming step, the second laminated body forming step, the second wiring forming step, and the wiring laminating step in the same manner as in Example 1, the ultrathin copper foil of the first metal layer and The boundary portion of the carrier copper foil applies physical force to peel and remove at least the core resin layer from the fifth laminated body, thereby obtaining a set of laminated bodies. That is, in Comparative Example 1, the solder resist layer forming step of Example 1 was not performed, but the core resin layer peeling step was performed. After peeling off the core resin layer, an attempt was made to remove the ultra-thin copper foil using a perhydrated sulfuric acid-based soft etching solution, but the laminate was damaged.

That is, according to Examples 1 and 2, it can be seen that when peeling off the core resin layer 11A and in the processing steps after peeling off, the solder resist layer 16A can be further reinforced and damage can be suppressed. [Industrial Applicability]

The present invention can be used to manufacture a package substrate for mounting a semiconductor element.

11:First layered body 11A: Core resin layer 11B: First metal layer 12:First wiring conductor 13:Second layered body 13A: First insulating resin layer 13B: Second metal layer 14A:Non-through hole 14B: Second wiring conductor 15: (m+2) layered body 15A: (m+1) insulating resin layer 15B: (m+2) wiring conductor 16: Solder resist layer forming body 16A: Solder mask 17: Core resin layer removed body 18: First metal layer removal body 19: Solder mask 20:Support substrate laminate 20A:Support substrate 21: Support substrate removal body

[Fig. 1] A diagram showing each step of a method of manufacturing a semiconductor element mounting package substrate according to the first embodiment. [Fig. 2] is a diagram showing each step following the steps in Fig. 1. [Fig. 3] is a diagram showing each step following the steps in Fig. 2. [Fig. 4] A diagram showing each step of a method of manufacturing a semiconductor element mounting package substrate according to the second embodiment. [Fig. 5] is a diagram showing each step following the steps in Fig. 4.

11:First layered body

11A: Core resin layer

11B: First metal layer

12:First wiring conductor

13A: First insulating resin layer

14A:Non-through hole

14B: Second wiring conductor

15:(m+2)th laminated body

15A:(m+1) insulating resin layer

15B:(m+2)th wiring conductor

16: Solder resist layer forming body

16A: Solder mask

17: Core resin layer removed body

Claims (7)

A method of manufacturing a packaging substrate for mounting semiconductor components, which includes: The first laminated body preparation step is to prepare a first laminated body having a core resin layer and a first metal layer provided on at least one side of the core resin layer and equipped with a peeling mechanism; A first wiring forming step, applying at least one of electroplating and electroless plating on the first metal layer to form a first wiring conductor; The second laminate forming step includes sequentially laminating a first insulating resin layer and a second metal layer on the surface of the first wiring conductor on which the first laminate is provided to form a second laminate; In a second wiring forming step, a non-through hole reaching the first wiring conductor is formed in the first insulating resin layer, and at least one of electroplating and electroless plating is applied to the surface on which the non-through hole is formed to form a second wiring conductor. ; In the wiring lamination step, after the second wiring forming step, the (m+1)th insulating resin layer and the (m+2)th metal are further sequentially layered on the surface of the (m+1)th wiring conductor provided with the (m+1)th laminate. layer to form the (m+2)th laminated body forming step of forming the (m+2)th laminated body, and forming a non-through hole reaching the (m+1)th wiring conductor in the (m+1)th insulating resin layer, and forming the non-through hole The surface of the hole is subjected to at least one of electroplating and electroless plating to form the (m+2)th wiring forming step of the (m+2)th wiring conductor. These two steps are sequentially repeated n times to form the second insulating resin layer to the (m+2)th wiring conductor. (n+1) insulating resin layer, and the third wiring conductor to the (n+2)th wiring conductor (m and n are integers above 1, provided that m≦n); The solder resist layer forming step is to form a solder resist layer on the (n+1)th insulating resin layer and the (n+2)th wiring conductor in such a manner that the (n+2)th wiring conductor is partially exposed, to form a solder resist layer formation body; as well as In the core resin layer peeling step, at least the core resin layer is peeled off from the solder resist layer forming body in the peeling mechanism to form a core resin layer removed body. The method of manufacturing a packaging substrate for mounting a semiconductor element according to claim 1, wherein the thickness of the core resin layer is 1 μm or more. The method of manufacturing a packaging substrate for mounting a semiconductor element according to claim 1, wherein the thickness of the first metal layer is 100 μm or less. The method of manufacturing a semiconductor element mounting package substrate according to claim 1, wherein the thickness of the first metal layer from the end surface on the side of the first wiring conductor to the peeling mechanism is 6 μm or more. The method of manufacturing a semiconductor element mounting package substrate according to claim 1, wherein the thickness of the first laminated body is 20 μm or more and 1000 μm or less. The method of manufacturing a semiconductor element mounting package substrate according to claim 1, wherein the thicknesses of the first to (n+1)th insulating resin layers are each from 0.1 μm to 100 μm. The manufacturing method of a packaging substrate for mounting a semiconductor element as claimed in claim 1, wherein the manufacturing method of a packaging substrate for mounting a semiconductor element includes a support substrate lamination step, which is after the solder resist layer forming step, the core resin layer Before the peeling step, a support substrate having a thermoplastic resin layer is laminated on the surface of the solder resist layer on which the solder resist layer formation body is provided.