TW202239288A - Substrate and method for producing wiring substrate - Google Patents

Abstract

The present invention provides a substrate which can be easily conveyed despite being thin, and a method for producing a wiring substrate that uses this substrate. In a substrate (10), a first metal layer (12), a first insulating resin layer (13), a second metal layer (14), a second insulating resin layer (15), and a carrier-equipped ultrathin metal foil layer (11) are laminated in this order. The substrate (10) has, in the planar direction, a circuit formation region (10A) and an outer peripheral region (10B) which is provided at the outer periphery of the circuit formation region (10A). In the circuit formation region (10A), the carrier (11B) of the carrier-equipped ultrathin metal foil layer (11) is removed such that the ultrathin metal foil layer (11A) is exposed, and thickness is not more than 80 [mu]m. Provided in at least part of the outer peripheral region (10B), is a carrier remaining part (10C) in which the carrier (11B) remains and the surface of the ultrathin metal foil layer (11A) is covered by the carrier (11B).

Description

Manufacturing method of substrate and wiring substrate

The present invention relates to a substrate and a method for manufacturing a wiring substrate using the substrate.

In recent years, the high functionality and miniaturization of semiconductor packages widely used in electronic equipment, communication equipment, and personal computers have been accelerated, and therefore the wiring boards of semiconductor packages have been required to be thinner. Subsequently, the substrate forming the base of the wiring substrate is also thinned. For example, a coreless substrate has been disclosed, which is an ultra-thin copper-clad laminate laminated with an ultra-thin metal foil on a core resin, or an ultra-thin copper-clad laminate on a core resin. After laminating the metal layer and the insulating layer, the metal layer and the insulating layer are peeled off from the core resin layer (for example, refer to Patent Document 1). [Prior Technical Literature] [Patent Document]

[Patent Document 1] International Publication No. WO2020/121651

[Technical problem to be solved by the invention]

When manufacturing a wiring board using such a substrate, for example, a step of transferring the substrate is required. The substrate is conveyed, for example, by moving on a plurality of rollers. At this time, the above-mentioned thin substrates are difficult to transport due to their low handling properties, and the substrates may be damaged during the transport process, resulting in a decrease in yield or contamination of the device. In addition, there may be cases where it cannot be transported due to its thickness. Therefore, for example, a guide plate having a higher rigidity than the substrate is connected to the leading end side in the substrate conveyance direction with an adhesive tape, and the substrate is guided by the guide plate to be conveyed. However, in this method, each substrate must be connected with a lead plate, and the lead plate must be peeled off after the process is completed, so it is very troublesome and the manufacturing cost is increased.

The present invention was made in view of such a problem, and an object of the present invention is to provide a board that can be easily transported even if it is thin, and a method of manufacturing a wiring board using the board. [Technical means]

The contents of the present invention are as follows. [1] A substrate, which has a laminated carrier and an ultra-thin metal foil layer attached to the carrier on at least one side of the substrate, characterized by having a circuit formation area, and an outer peripheral area provided outside the circuit formation area; The above-mentioned circuit formation region is the ultra-thin metal foil layer with the carrier removed from the ultra-thin metal foil layer with a carrier, and the thickness is 80 μm or less; In at least a part of the outer peripheral region, the carrier remains, and a carrier remaining portion where the carrier covers the surface of the ultra-thin metal foil layer is provided. [2] A substrate, which has a laminated carrier and an ultra-thin metal foil layer attached to the carrier on at least one side of the substrate, characterized by having a circuit formation area, and an outer peripheral area provided outside the circuit formation area; In order to remove the carrier in the circuit formation region and leave the carrier in at least a part of the outer peripheral region to form a carrier remaining portion, in the boundary between the outer peripheral region and the circuit formation region and in the outer peripheral region At least one side of the carrier is provided with a cutout from the surface layer of the carrier to the ultra-thin metal foil layer. [3] The substrate according to [1] or [2], wherein the width of the outer peripheral region is within the range of 1 mm to 300 mm. [4] A method of manufacturing a wiring substrate, using the substrate described in [1] or [2], characterized by comprising In the conveying step, the substrate remains on the front side, and the substrate is conveyed by moving on a plurality of rollers. [5] The method of manufacturing a wiring board according to [4], wherein etching is performed in the transferring step. [Effect of the invention]

According to the present invention, at least a part of the outer peripheral region is provided with a carrier remaining portion where the carrier remains, or at least one side of the boundary between the outer peripheral region and the circuit formation region and the outer peripheral region is provided with a cutout on the carrier to form the carrier residue. Therefore, when using this substrate to manufacture a wiring board, the thickness of the substrate in the carrier remaining part can be increased by the thickness of the carrier compared to the thickness of the substrate in the circuit formation region. Therefore, instead of the guide plate, the substrate can be easily conveyed by using the carrier remaining part as a guide part. Accordingly, it is not necessary to connect and peel off the lead plate, and labor and cost can be reduced.

Hereinafter, the form for implementing the present invention (hereinafter, referred to as "the present embodiment") will be described in detail, but the present invention is not limited thereto, and various changes can be made within the scope not departing from the concept.

[First Embodiment] FIG. 1 is a diagram showing a cross-sectional structure of a substrate 10 according to a first embodiment of the present invention. FIG. 2 is a diagram showing a planar configuration viewed from one side of the substrate 10 . This substrate 10 has, on one surface side, an ultra-thin metal foil layer 11 with a carrier that is a laminated carrier 11B and an ultra-thin metal foil layer 11A. Specifically, the substrate 10 has, for example, a first metal layer 12, a first insulating resin layer 13, a second metal layer 14, a second insulating resin layer 15, and an ultra-thin metal foil layer 11 with a carrier laminated in this order. The composition. The ultra-thin metal foil layer 11 with a carrier is, for example, a layer formed by using an ultra-thin metal foil with a carrier 11B on the ultra-thin metal foil layer 11A through a release layer (not shown), and the ultra-thin metal foil Foil layer 11A is laminated on the side of second insulating resin layer 15 . In addition, the substrate 10 is a so-called coreless substrate. For example, as described later, the first metal layer 12, the first insulating resin layer 13, the second metal layer 14, and the second insulating resin layer 16 are laminated on the core resin layer 16. The resin layer 15 and the ultra-thin metal foil layer 11 with a carrier can be manufactured by peeling off the interface between the core resin layer 16 and the first metal layer 12 .

The substrate 10 has, in the planar direction, a circuit formation region 10A where a circuit is formed, and an outer peripheral region 10B provided on the periphery of the circuit formation region 10A. The substrate 10 is, for example, quadrilateral in plan view. The outer peripheral area 10B is provided along each side, for example, and the circuit formation area 10A is provided in the area surrounded by the outer peripheral area 10B. The width (width in the planar direction) of the outer peripheral region 10B is, for example, within a range of not less than 1 mm and not more than 300 mm.

In the circuit formation region 10A, the carrier 11B is removed from the ultrathin metal foil layer 11 with a carrier to expose the ultrathin metal foil layer 11A, and the thickness of the circuit formation region 10A is as thin as 80 μm or less. This is for thinning. The thickness of the circuit formation region 10A is, for example, preferably 30 μm or more, more preferably 35 μm or more. The reason is that if it is thinner than this, the reinforcement strength will be insufficient, and the risk of damage will increase. In addition, the thickness refers to the thickness in the lamination direction (the same applies hereinafter).

On the other hand, carrier 11B remains in at least a part of outer peripheral region 10B, and carrier remaining portion 10C in which carrier 11B covers the surface of ultrathin metal foil layer 11A is provided. Thus, the thickness of the substrate 10 in the carrier remaining portion 10C can be increased by the thickness of the carrier 11B compared with the thickness of the substrate 10 in the circuit formation region 10A, and it can function as a guide to guide the substrate 10 during transportation. . In addition, in the region other than the carrier remaining portion 10C in the outer peripheral region 10B, the carrier 11B is removed to expose the ultra-thin metal foil layer 11A, as in the circuit formation region 10A.

For example, the carrier remaining portion 10C is preferably provided along at least one side, and may be provided along all the sides. In addition, FIGS. 1 and 2 show the case where the carrier remaining portion 10C is provided along one side of the substrate 10 . In addition, the width of the carrier remaining portion 10C may be the same as the width of the outer peripheral region 10B, but not necessarily the same, and may be provided in a part of the width direction. For example, it may be provided at a distance from the side, or may be provided at a distance from the circuit formation region 10A. In addition, 10 C of carrier remaining parts may be provided in a part of the longitudinal direction of a side, and it is preferable to provide continuously over the whole.

(Carrier 11B) The carrier 11B is used to support the ultra-thin metal foil layer 11A and improve handling. The material constituting the carrier 11B is not particularly limited. For example, metal foils such as copper foil, copper alloy foil, aluminum foil, composite metal foil with metal plating such as copper or zinc on the surface of the aluminum foil, and stainless steel foil can be used. Others include resin films such as PET films, PEN films, aramid films, polyimide films, nylon films, and liquid crystal polymers, metal-coated resin films with metal coating layers on resin films, glass plates, ceramic plates etc. Among them, metal foil is preferable from the viewpoint of preventing static electricity from being entrapped during handling, and copper foil is preferable from the viewpoint of thickness uniformity and corrosion resistance of the foil. The thickness of the carrier 11B is thicker than that of the ultra-thin metal foil layer 11A, and, for example, is preferably not more than 250 μm, more preferably not less than 12 μm and not more than 200 μm.

(peeled layer) The peeling layer is for easily peeling the carrier 11B from the ultra-thin metal foil layer 11A. The material of the release layer is not particularly limited, and various known materials can be appropriately used.

(Extremely thin metal foil layer 11A) The ultra-thin metal foil layer 11A can be composed of various metal foils, for example, and is preferably composed of copper foil. The thickness of the ultra-thin metal foil layer 11A can be appropriately set according to needs, so it is not particularly limited. For example, it can be 2 μm to 70 μm, preferably 2 μm to 18 μm, and more preferably 2 μm to 5 μm.

(first metal layer 12) The first metal layer 12 preferably has a thickness of 1 μm to 70 μm, for example, and is formed of a metal foil that can be peeled from the core resin layer 16 as will be described later. If the thickness of the first metal layer 12 is less than 1 μm, the formation of the substrate 10 will be defective, and if it exceeds 70 μm, the surface will be defective. The thickness of the first metal layer 12 is preferably from 1 μm to 12 μm, more preferably from 2 μm to 5 μm, from the viewpoint of circuit formability.

The first metal layer 12 is preferably formed of, for example, copper foil. As the copper foil, for example, a peelable copper foil can be used. The "peelable" copper foil refers to an extremely thin copper foil with a peelable layer; the peelable layer refers to, for example, a peelable copper foil.

(1st insulating resin layer 13) The first insulating resin layer 13 is not particularly limited. For example, a prepreg of an insulating resin material (insulating material) such as a thermosetting resin impregnated with a glass cloth or the like, or an insulating material can be used. Film material etc. The thickness of the first insulating resin layer 13 can be appropriately set according to needs, so it is not particularly limited. For example, it can be 10 μm to 100 μm, preferably 10 μm to 50 μm, more preferably 10 μm to 30 μm.

"Prepreg" is obtained by impregnating or coating an insulating material such as a resin composition on a base material. The base material is not particularly limited, and conventional base materials used for laminates for various electrical insulating materials can be appropriately used. Materials constituting the substrate include, for example, inorganic fibers such as E glass, D glass, S glass, or Q glass; organic fibers such as polyimide, polyester, or tetrafluoroethylene; and mixtures thereof. The substrate is not particularly limited, and for example, substrates having shapes such as woven fabrics, nonwoven fabrics, rovings, cut mats, and surface mats can be suitably used. The material and shape of the base material can be selected depending on the usage or performance of the intended molding, and single or two or more types of materials and shapes can be used as needed.

The thickness of the base material is not particularly limited as long as the thickness of the first insulating resin layer 13 is within the above range. In addition, as the base material, a base material subjected to surface treatment with a silane coupling agent or a base material subjected to a mechanical fiber opening treatment can be used, and these base materials are suitable in terms of heat resistance, moisture resistance, and processability. .

The insulating material is not particularly limited, and conventional resin compositions that have been used as insulating materials for printed wiring boards can be appropriately selected. For the resin composition, a thermosetting resin having good heat resistance and chemical resistance can be used as a base. The thermosetting resin is not particularly limited, and examples thereof include phenolic resins, epoxy resins, cyanate resins, maleimide resins, isocyanate resins, benzocyclobutene resins, and vinyl resins. Thermosetting resins may be used alone or in combination of two or more.

Among thermosetting resins, epoxy resin is preferably used as an insulating material because it is excellent in heat resistance, chemical resistance, and electrical characteristics, and is relatively inexpensive. Epoxy resins, for example, bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, alicyclic epoxy resin, aliphatic chain epoxy resin, phenol novolac type epoxy resin, cresol novolak type epoxy resin, bisphenol A novolak type epoxy resin, bisphenol diglycidyl ether compound, naphthalene diol diglycidyl ether compound, phenol diglycidyl ether Compounds, diglycidyl ether compounds of alcohols, and their alkyl substituents, halides, hydrides, etc. One type of epoxy resin may be used alone, or two or more types may be used in combination. In addition, the hardener used together with the epoxy resin can be used without limitation as long as it can harden the epoxy resin, for example, polyfunctional phenols, polyfunctional alcohols, amines, imidazole compounds, acid anhydrides, organophosphorus compounds And these halides, etc. These epoxy resin hardeners may be used alone or in combination of two or more.

Cyanate resin is a resin that generates a hardened product with a triazine ring as a repeating unit by heating. The hardened product has excellent dielectric properties. Therefore, it is particularly suitable for situations where high frequency characteristics are required. Cyanate resins are not particularly limited, for example, 2,2-bis(4-cyanophenyl)propane, bis(4-cyanophenyl)ethane, 2,2-bis(3,5 Dimethyl-4-cyanophenyl)methane, 2,2-(4-cyanophenyl)-1,1,1,3,3,3-hexafluoropropane, α,α'-bis(4 -cyanophenyl)-m-diisopropylbenzene, phenol novolac and cyanate esters of alkylphenol novolak, etc. Among them, 2,2-bis(4-cyanophenyl)propane is preferable because the balance between the dielectric properties and curability of the cured product is particularly good, and the cost is also low. Cyanate resins such as these cyanate compounds may be used alone or in combination of two or more. In addition, the aforementioned cyanate compounds may also be partly oligomerized into trimers or pentamers in advance.

Furthermore, a curing catalyst or a curing accelerator may be used in combination with the cyanate resin. Hardening catalysts, for example, metals such as manganese, iron, cobalt, nickel, copper, zinc, etc. can be used, specifically, organic metal salts such as 2-ethylhexanoate, octanoate, etc.; Compounds and other organometallic complexes. As the curing catalyst, one type may be used alone, or two or more types may be used in combination.

In addition, as the hardening accelerator, it is preferable to use phenols, such as monofunctional phenols such as nonylphenol and p-cumylphenol; bifunctional phenols such as bisphenol A, bisphenol F, and bisphenol S; or phenol novolac Polyfunctional phenols such as varnishes, cresol novolaks, etc. As the hardening accelerator, one type may be used alone, or two or more types may be used in combination.

A resin composition used as an insulating material, considering dielectric properties, impact resistance, film processability, etc., thermoplastic resins can also be blended. The thermoplastic resin is not particularly limited, and examples thereof include fluororesin, polyphenylene ether, modified polyphenylene ether, polyphenylene sulfide, polycarbonate, polyetherimide, polyether ether ketone, polyacrylate, Polyamide, polyamideimide, polybutadiene, etc. Thermoplastic resins may be used alone or in combination of two or more.

Among thermoplastic resins, it is useful to add polyphenylene ether and modified polyphenylene ether from the viewpoint of improving the dielectric properties of the cured product. Polyphenylene ether and modified polyphenylene ether, for example, poly(2,6-dimethyl-1,4-phenyl) ether, poly(2,6-dimethyl-1,4-phenyl) ether and Alloyed polymer of polystyrene, alloyed polymer of poly(2,6-dimethyl-1,4-phenyl) ether and styrene-butadiene copolymer, poly(2,6-dimethyl Alloyed polymer of -1,4-phenyl) ether and styrene-maleic anhydride copolymer, alloyed polymer of poly(3,6-dimethyl-1,4-phenyl) ether and polyamide, Alloy polymer of poly(2,6-dimethyl-1,4-phenyl) ether and styrene-butadiene-acrylonitrile copolymer, etc. In addition, in order to impart reactivity and polymerizability to polyphenylene ether, functional groups such as amino groups, epoxy groups, carboxyl groups, and styryl groups can be introduced at the end of the polymer chain, or amino groups, rings, etc. can be introduced at the side chains of the polymer chain. Functional groups such as oxygen group, carboxyl group, styryl group, methacrylic group, etc.

Among thermoplastic resins, polyamideimide resins are useful from the viewpoint of excellent moisture resistance and better adhesion to metals. The raw material of polyamideimide resin is not particularly limited, and the acid component includes trimellitic anhydride and trimellitic anhydride monochloride; the amine component includes m-phenylenediamine, p-phenylenediamine, and 4,4'-diamine Diphenyl ether, 4,4'-diaminodiphenylmethane, bis[4-(aminophenoxy)phenyl]pyridine, 2,2'-bis[4-(4-aminophenoxy) Phenyl]propane, etc. Polyamideimide resin can also be modified with siloxane in order to improve drying properties. In this case, siloxane diamine can be used as the amine component. For polyamideimide resins, if film processability is considered, it is better to use those with a molecular weight of 50,000 or more.

Regarding the above-mentioned thermoplastic resins, insulating materials used for prepregs are mainly explained, but these thermoplastic resins are not limited to use as prepregs. For example, what is processed into a film (film material) using the above-mentioned thermoplastic resin can also be used as the said insulating resin layer.

The resin composition used as insulating material can also be mixed with inorganic fillers. Inorganic fillers are not particularly limited, for example, aluminum oxide, aluminum hydroxide, magnesium hydroxide, clay, talc, antimony trioxide, antimony pentoxide, zinc oxide, fused silica, glass powder, quartz powder, shirasu balloon, etc. These inorganic fillers may be used individually by 1 type, and may mix and use 2 or more types.

Resin compositions used as insulating materials may also contain organic solvents. Organic solvents are not particularly limited, and aromatic hydrocarbon solvents such as benzene, toluene, xylene, and trimethylbenzene; ketone solvents such as acetone, methyl ethyl ketone, and methyl isobutyl ketone; such as tetrahydrofuran Ether-based solvents; alcohol-based solvents such as isopropanol and butanol; ether-alcohol-based solvents such as 2-methoxyethanol and 2-butoxyethanol; such as N-methylpyrrolidone, N,N-dimethyl Amide-based solvents such as methyl formamide and N,N-dimethylacetamide. Also, when producing a prepreg, the amount of solvent in the varnish is preferably in the range of 40% by mass to 80% by mass relative to the entire resin composition. In addition, the viscosity of the aforementioned varnish is desirably in the range of 20cP to 100cP (20mPa･s to 100mPa･s).

Resin compositions used as insulating materials may also contain flame retardants. Flame retardants are not particularly limited. For example, brominated compounds such as decabromodiphenyl ether, tetrabromobisphenol A, tetrabromophthalic anhydride, and tribromophenol can be used; triphenyl phosphate, trityl phosphate Phosphorus compounds such as esters and cresyl diphenyl phosphate; metal hydroxides such as magnesium hydroxide and aluminum hydroxide; red phosphorus and its modified products; antimony compounds such as antimony trioxide and antimony pentoxide; melamine , cyanuric acid, triazine compounds such as cyanuric acid and melamine, etc., are conventional flame retardants.

For resin compositions used as insulating materials, the above-mentioned hardeners, hardening accelerators, or other additives or fillers such as thermoplastic particles, colorants, UV inhibitors, antioxidants, reducing agents, etc. can be added as needed material.

In the present embodiment, the prepreg, for example, has a resin content of 20% by mass to 90% by mass of the prepreg after drying, and the resin composition (containing Varnish) impregnates or coats the substrate, and then heats and dries at a temperature of 100°C to 200°C for 1 minute to 30 minutes to obtain a prepreg in a semi-hardened state (B-stage state). As such a prepreg, for example, GHPL-830NS series (product name) and GHPL-830NSF series (product name) manufactured by Mitsubishi Gas Chemical can be used.

(2nd metal layer 14) The 2nd metal layer 14 can be comprised with various metal foils, for example, Preferably it is comprised with copper foil. The thickness of the second metal layer 14 can be appropriately set according to needs, so it is not particularly limited. For example, it can be 2 μm to 70 μm, preferably 2 μm to 18 μm, and more preferably 2 μm to 12 μm. In addition, a circuit pattern may be formed on the second metal layer 14 if necessary.

(Second insulating resin layer 15) The second insulating resin layer 15 is not particularly limited, and may be formed of the same material as the first insulating resin layer 13 (for example, prepreg). The thickness of the second insulating resin layer 15 can be appropriately set according to needs, so it is not particularly limited. For example, it can be 10 μm to 100 μm, preferably 10 μm to 50 μm, and more preferably 10 μm to 30 μm.

<Manufacturing of substrate 10> 3 and 4 show the manufacturing steps of the substrate 10 . The substrate 10 can be manufactured, for example, as follows.

(1st laminate forming step) First, for example, as shown in FIG. 3(A), a core resin layer 16 is prepared as a base material for forming the substrate 10, and on both sides of the core resin layer 16, the first metal layer 12 and the first insulating layer 12 are sequentially arranged. After the resin layer 13 and the second metal layer 14 are heated and pressed together, for example, as shown in FIG. 3(B), a first laminate 17 in which each layer is pressure-bonded is formed.

The core resin layer 16 is not particularly limited, and can be formed of, for example, the same material as the first insulating resin layer 13 (for example, prepreg). The thickness of the core resin layer 16 is, for example, preferably 1 μm to 80 μm. If the thickness of the core resin layer 16 is less than 1 μm, resin molding will be poor, and if it exceeds 80 μm, wrinkles and unevenness will occur on the surface of the first metal layer 12 peeled from the core resin layer 16 . The thickness of the core resin layer 16 is preferably from 3 μm to 40 μm, and more preferably from 10 μm to 25 μm, from the viewpoint of laminate formability.

The first metal layer 12 is preferably formed of a metal foil that can be peeled from the core resin layer 16 as described above, for example, using a peelable copper foil. When using a peelable copper foil, the first metal layer 12 is laminated with the peelable layer in contact with the core resin layer 16 . The peeling layer includes, for example, a layer containing at least a silicon compound. For example, it can be formed by imparting a silicon compound composed of a silane compound alone or in combination on a copper foil. In addition, the means for providing the silicon compound is not particularly limited, and for example, known means such as coating can be used. Anti-rust treatment can be applied to the bonding surface of the peeling layer with copper foil (formation of an anti-rust treatment layer). Any one of nickel, tin, zinc, chromium, molybdenum, and cobalt, or an alloy thereof can be used for antirust treatment. The thickness of the peeling layer is not particularly limited, but it is preferably 5 nm to 100 nm, more preferably 10 nm to 80 nm, and particularly preferably 20 nm to 60 nm from the viewpoint of removability and peelability.

The second metal layer 14 can be formed, for example, by using an ultra-thin metal foil with a carrier and then peeling off the carrier. In this case, the second metal layer 14 is formed by arranging an ultra-thin metal foil with a carrier on the side of the first insulating resin layer 13, heating and pressing to form the first laminate 17, and then peeling off the carrier. And formed.

The heating and pressing conditions of the first layered body forming step are not particularly limited, for example, the first layered layer can be formed by applying vacuum pressure under the conditions of temperature 220±2°C, pressure 5±0.2MPa, and holding time 60 minutes Body 17. In addition, in order to obtain the adhesion force between the first metal layer 12 and the core resin layer 16, or the adhesion force between the first metal layer 12 or the second metal layer 14 and the first insulating resin layer 13, the first The surface of the metal layer 12 or the second metal layer 14 is roughened. The roughening treatment is not particularly limited, and known means can be used as appropriate. When the first metal layer 12 or the second metal layer 14 is copper foil, for example, means using a copper surface roughening liquid can be cited.

(patterning step) Next, for example, as shown in FIG. 3(C), a pattern is formed on the second metal layer 14 . The means for forming the pattern is not particularly limited, for example, it can be formed by the following steps. The entire surface of the second metal layer 14 is implemented, and dry film photoresist is laminated. Then, after covering the negative photomask, the circuit pattern is printed with an exposure machine, and the dry film photoresist is developed with a developer to form an etching photoresist. Then, an etching process is applied, and the second metal layer 14 where the photoresist is not etched is removed by an aqueous ferric chloride solution, etc., and then the photoresist is removed, so that a pattern can be formed on the second metal layer 14 .

The photoresist at this time is not particularly limited, for example, a conventional photoresist such as a commercially available dry film photoresist can be appropriately selected. In addition, the photolithography (including exposure, development, and removal of photoresist) when forming a pattern on the second metal layer 14 is not particularly limited, and can be implemented using known means and devices. The pattern width of the second metal layer 14 is not particularly limited, and an appropriate width can be selected according to the application. For example, it can be 5 μm to 100 μm, preferably 10 μm to 30 μm.

(2nd laminate forming step) Next, for example, as shown in FIG. 3(D), on the surface of the second metal layer 14 of the first laminate 17, the second insulating resin layer 15 and the ultra-thin metal foil layer 11 with a carrier are sequentially arranged, Heating and pressing are performed to form the second laminate 18 . In the ultra-thin metal foil layer 11 with a carrier, the ultra-thin metal foil layer 11A of the ultra-thin metal foil with a carrier is arranged on the side of the second insulating resin layer 15 . The method and conditions for laminating the second insulating resin layer 15 and the ultrathin metal foil layer 11 with a carrier are not particularly limited. For example, the second insulating resin layer 15 and the ultrathin metal foil layer with a carrier are laminated on the first laminate 17. After the metal foil layer 11, the second laminated body 18 can be formed by applying vacuum pressure at a temperature of 220±2° C., a pressure of 5±0.2 MPa, and a holding time of 60 minutes. In addition, in order to obtain the adhesion between the ultra-thin metal foil layer 11A and the second insulating resin layer 15, roughening treatment may be applied to the surface of the ultra-thin metal foil layer 11A.

(cutting step) Next, for example, as shown in FIG. 4(E), in the second laminate 18, the carrier 11B is removed in the circuit formation region 10A, and the carrier 11B is left in at least a part of the outer peripheral region 10B to form a carrier. Remaining portion 10C is at least one side of the boundary between outer peripheral region 10B and circuit formation region 10A and outer peripheral region 10B, and cuts 11C from the surface layer of carrier 11B to ultra-thin metal foil layer 11A in carrier 11B. The notch 11C can be cut by a cutter or the like. By this notch 11C, the carrier 11B is separated into the carrier remaining part 10C and other parts.

(carrier stripping step) Next, for example, as shown in FIG. 4(F), the carrier 11B in which the notch 11C has been cut is left with a part of the carrier remaining portion 10C, and the other parts are peeled off. 4 (F), shows the following situation: along one side of the substrate 10, in the outer peripheral region 10B, or the boundary between the outer peripheral region 10B and the circuit formation region 10A and the outer peripheral region 10B cut 11C, along one side of the substrate The carrier 11B is left and other parts are peeled off to form the carrier remaining part 10 .

(Core resin layer separation step) Then, for example, the second laminate 18 is separated by peeling at the interface between the core resin layer 16 and the first metal layer 12 disposed on both surfaces thereof. Thereby, the substrate 10 ( Refer to Figure 1). Also, in the peeling of the core resin layer 16, it is preferable to peel at the interface between the core resin layer 16 and the first metal layer 12, but for example, in the case where the first metal layer 12 has a peeling layer, a part of it may be Peel off together with the core resin layer 16 . In addition, in the interface between the peelable layer of the first metal layer 12 and the metal foil, the peelable layer and the core resin layer 16 are also peeled off together. When the peeling layer remains on the first metal layer 12, for example, the peeling layer can be removed using a sulfuric acid-based or hydrogen peroxide-based etchant. The sulfuric acid-based or hydrogen peroxide-based etchant is not particularly limited, and an etchant commonly used in the industry can be used.

(Variation of the order of the incision step, the carrier peeling step, and the core resin layer separation step) In addition, in the above, the case where the incision step, the carrier peeling step, and the core resin layer separation step are sequentially performed after the second laminate forming step has been described, but the core resin layer separation step may be performed after the second laminate forming step. The core resin layer separating step, the cutting step, and the carrier peeling step are performed in this order, or the cutting step, the core resin layer separating step, and the carrier peeling step may be performed in that order after the second laminate forming step.

<Manufacturing of wiring substrate 20 using substrate 10> FIG. 5 shows an example of the steps of manufacturing the wiring board 20 using the substrate 10 . The substrate 10 can be used, for example, in the manufacture of a wiring substrate 20 in which wiring conductors 22 are formed on both surfaces of an insulating layer 21 . In addition, the insulating layer 21 is composed of the first insulating resin layer 13 and the second insulating resin layer 15; the wiring conductor 22 is formed by individually patterning the first metal layer 12, the second metal layer 14 and the The ultra-thin metal foil layer 11A is formed by electrolytic copper plating and/or electroless copper plating for interlayer connection. Specifically, for example, it can be manufactured as follows.

(Formation of non-through holes) For example, first, as shown in FIG. 5(A), non-through holes 23 reaching the surface of the second metal layer 14 are formed on the surface of the substrate 10 . The non-through holes 23 are provided on both sides of the substrate 10 . That is, the non-through hole 23 is formed in the second insulating resin layer 15 through the ultra-thin metal foil layer 11A from the upper side of the drawing in FIG. 5(A). Similarly, non-through holes 23 are formed in the first insulating resin layer 13 through the first metal layer 12 from the lower side of the drawing in FIG. 5(A). The means for forming the non-through hole 23 is not particularly limited, for example, known means such as carbon dioxide laser can be used. The number or size of the non-through holes 23 can be appropriately selected according to needs. In addition, after the non-through hole 23 is formed, a desmear treatment may be performed using a sodium permanganate aqueous solution or the like.

(Interlayer connection and formation of the third metal layer) Next, for example, as shown in FIG. 5(B), electrolytic copper plating and/or electroless copper plating are applied to form a copper plating film on the inner wall of the non-through hole 23, and the individually patterned first metal layer 12, The second metal layer 14 and the ultra-thin metal foil layer 11A are electrically connected. Furthermore, by this electrolytic copper plating and/or electroless copper plating, the thicknesses of the first metal layer 12 and the ultra-thin metal foil layer 11A on both surfaces of the substrate 10 are increased to form the third metal layer 24 . The method of electrolytic copper plating and/or electroless copper plating is not particularly limited, and known methods can be used. This copper plating may be only one of electrolytic copper plating and electroless copper plating, but it is preferable to give both electrolytic copper plating and electroless copper plating.

(film thickness adjustment) Next, for example, as shown in FIG. 5(C), after the electrolytic/electroless copper plating treatment, if necessary, the third metal layer 24 may be given a conventional treatment such as etching treatment to adjust the thickness of the third metal layer 24 to a desired thickness. 3. The film thickness of the metal layer 24. The adjusted thickness of the substrate 10 can be appropriately set according to needs, so there is no particular limitation, for example, it can be 5 μm-30 μm, preferably 5 μm-20 μm, more preferably 5 μm-12 μm.

(patterned) Next, for example, after the entire surface of the third metal layer 24 can be implemented as needed, a dry film photoresist is laminated, and then, after covering the negative photomask, the circuit pattern is printed with an exposure machine, and the dry film photoresist is developed with a developer. , forming an etch photoresist. After the etching photoresist is formed, for example, the substrate 10 is moved on a plurality of rollers with the carrier remaining part 10C as the front side by a horizontal etching line, and the etching process is performed, and then the non-etching photoresist is removed with an aqueous solution of ferric chloride or the like. The third metal layer 24 of the resistance part. In this embodiment, at least a part of the outer peripheral region 10B of the substrate 10 is provided with a thick carrier remaining portion 10C, so the substrate 10 can be easily transported using the carrier remaining portion 10C as a guide. Then, by removing the photoresist, as shown in FIG. 5(D), a wiring substrate 20 in which wiring conductors 22 are formed on both surfaces of the insulating layer 21 can be formed.

In addition, other applicable interlayer connection methods in this embodiment include a method in which conventional laser-formed blind holes are subjected to electroless copper plating (a wiring circuit is formed by laser processing, and then Patterning by electroless copper plating, interlayer connection method); or metal bumps (preferably copper bumps) formed by plating or etching metal foil on the part where the connection part is formed in advance, together with the insulating layer piercing , and the method of interlayer connection; in addition, the metal paste containing solder or metal fillers such as silver and copper in the insulating resin is subjected to concave-convex printing at the specified place by screen printing, etc., and the paste is hardened by drying, and Electrical conduction between inner and outer layers is ensured by heating and pressing.

In FIG. 5 which exemplifies this embodiment, the wiring substrate 20 is a packaging substrate for semiconductor element mounting formed in a 3-layer structure, but the present invention is not limited thereto, and may form a 5-layer structure with further assembly ( build-up) structure semiconductor device mounting package substrate. For example, after the wiring conductor 22 is formed as described above, the carrier 11B is peeled off, and then an insulating resin layer and a metal layer are laminated, and patterning and interlayer connection are repeated to manufacture a package substrate for mounting a semiconductor element having an assembly structure.

The wiring board 20 can be mounted with, for example, semiconductor elements such as bare chips as needed. The semiconductor element to be mounted is not particularly limited, and necessary elements can be used appropriately. For example, a bare chip in which gold bumps are formed on aluminum electrode portions by ball bonding with gold wires can be used. The semiconductor element can be mounted on the wiring conductor 22 of the wiring substrate 20 through a bonding material. The bonding material is not particularly limited as long as it has a conductive means, for example, solder or the like (solder ball, solder paste, etc.) can be used. In addition, after surface treatment is given to the wiring conductor 22 of the wiring board 20, the semiconductor element can be mounted through a bonding material. The surface treatment is not particularly limited, and examples thereof include formation of a nickel layer or a gold-plated layer. In the case where solder is used as the bonding material, after the semiconductor element is mounted on the wiring conductor 22, reflow soldering or the like may be performed. At this time, the temperature of the reflow soldering can be appropriately selected according to the melting point of the bonding material and the like, for example, it can be 260° C. or higher.

Thus, according to the present embodiment, at least a part of the outer peripheral region 10B is provided with the carrier remaining portion 10C in which the carrier 11B is left. Therefore, when the substrate 10 is used to manufacture the wiring board 20, the thickness of the substrate 10 of the carrier remaining portion 10C can be reduced. , compared with the thickness of the substrate 10 in the circuit formation region 10A, the thickness of the carrier 11B is thickened. Therefore, instead of the guide plate, the substrate 10 can be conveyed using the carrier remaining portion 10C as a guide. Accordingly, it is not necessary to connect and peel off the guide plate, and labor and cost can be reduced.

[Second Embodiment] FIG. 6 shows the structure of the substrates 30A and 30B according to the second embodiment of the present invention, FIG. 6(A) shows the substrate 30A, and FIG. 6(B) shows the substrate 30B. The substrate 30A is a slit 11C cut from the surface layer of the carrier 11B to reach the ultra-thin metal foil layer 11A in the carrier 11B of the second laminate 18 of the first embodiment. The substrate 30B is the carrier 11B of the second laminated body 18 of the first embodiment, which is cut from the surface layer of the carrier 11B to reach the incision 11C of the ultra-thin metal foil layer 11A, and the carrier 11B is not peeled off, but the core resin layer 16 is separated. Alternatively, the core resin layer 16 is separated from the second laminate 18 and cut into the carrier 11B from the surface layer of the carrier 11B to reach the incision 11C of the ultra-thin metal foil layer 11A.

That is, the substrates 30A and 30B are the substrates before the carrier 11B is provided with the notch 11C for forming the carrier remaining portion 10C and the carrier 11B is peeled off, and otherwise have the same configuration as the first embodiment, and can be manufactured in the same manner. In addition, the carrier 11B of the part other than the carrier remaining part 10C can be peeled off, and the core resin layer 16 can be separated in the substrate 30A, and can be used for the production of the wiring board 20 in the same manner as in the first embodiment, and the same as the first embodiment can be obtained. Embodiments have the same effect. Therefore, the same reference numerals are assigned to the same constituent elements as those of the first embodiment, and detailed description thereof will be omitted. In addition, the substrate 30A has the ultra-thin metal foil layer 11 with a carrier on both sides, and the substrate 30B has the ultra-thin metal foil layer 11 with a carrier on one side.

[Third Embodiment] FIG. 7 shows the structure of a substrate 40 according to a third embodiment of the present invention. This substrate 40 has a carrier-attached ultra-thin metal foil layer 41 of a laminate carrier 41B and an ultra-thin metal foil layer 41A on at least one surface side. Specifically, the substrate 40 has, for example, a structure in which an ultra-thin metal foil layer 41 with a carrier is laminated on both surfaces of a resin layer 42, such as a so-called copper-clad laminate.

The ultra-thin metal foil layer 41 with a carrier has the same structure as the ultra-thin metal foil layer 11 with a carrier in the first embodiment. The carrier 41B corresponds to the carrier 11B, and the ultra-thin metal foil layer 41A corresponds to the ultra-thin metal foil layer 11. Metal foil layer 11A. The resin layer 42 has the same structure as the core resin layer 16 of the first embodiment. In the ultra-thin metal foil layer 41 with carrier, the ultra-thin metal foil layer 41A is laminated on the side of the resin layer 42 .

The substrate 40 has a circuit formation region 40A and an outer peripheral region 40B in the planar direction as in the first embodiment except that the laminated structure is different, and a carrier remaining portion 40C is provided in at least a part of the outer peripheral region 40B. The circuit formation region 40A, the outer peripheral region 40B, and the remaining carrier portion 40C are the same as the circuit formation region 10A, the outer peripheral region 10B, and the remaining carrier portion 10C of the first embodiment. That is, in the circuit formation region 40A, the carrier 41B is removed from the ultrathin metal foil layer 41 with a carrier to expose the ultrathin metal foil layer 41A, and the thickness of the circuit formation region 40A is as thin as 80 μm or less. On the other hand, the carrier 41B remains in at least a part of the outer peripheral region 40B, and a carrier remaining portion 40C in which the surface of the ultrathin metal foil layer 41A is covered with the carrier 41B is provided. In addition, in FIG. 7, the case where the carrier remaining part 40C is formed on both surfaces along one side of a board|substrate is shown.

<Manufacturing of substrate 40> FIG. 8 shows the manufacturing steps of the substrate 40 . For the substrate 40, first, as shown in FIG. 8(A), for example, the ultra-thin metal foil layer 41 with a carrier is disposed on both sides of the resin layer 42, and heated and pressed to form a third laminate 43. The ultra-thin metal foil layer 41 with a carrier is formed using the ultra-thin metal foil with a carrier, and the ultra-thin metal foil layer 41A is disposed on the side of the resin layer 42 . Next, for example, as shown in FIGS. 8(B) and (C), as in the first embodiment, the carrier 41B on both sides of the third layered body 43 is subjected to an incision step (FIG. 8(B)) and carrier peeling. step (Fig. 8(C)). Thereby, a substrate 40 as shown in FIG. 7 is obtained.

<Manufacturing of wiring substrate 50 using substrate 40> FIG. 9 shows an example of a procedure for manufacturing a wiring board 50 using the substrate 40 . The substrate 40 can be used, for example, in the manufacture of a wiring substrate 50 in which wiring conductors 52 are formed on both surfaces of an insulating layer 51 . In addition, the insulating layer 51 is composed of the resin layer 42; the wiring conductor 52 is formed by electrolytic copper plating and/or electroless copper plating of the patterned ultra-thin metal foil layer 41A for interlayer connection. Specifically, for example, it can be manufactured as follows.

(Formation of through holes) For example, first, as shown in FIG. 9(A), a through hole 53 is formed in the substrate 40 . The means for forming the through hole 53 is not particularly limited, and for example, known means such as a laser such as a carbon dioxide laser or a drill can be used. The number or size of the through-holes 53 can be appropriately selected according to needs. In addition, after the through hole 53 is formed, desmearing treatment may be performed using an aqueous solution of sodium permanganate or the like.

(Interlayer connection and formation of conductor layer) Next, for example, as shown in FIG. 9(B), electrolytic copper plating and/or electroless copper plating are applied to form a copper plating film on the inner wall of the through hole 53, and the ultra-thin metal foil layer 41A on both sides of the pattern is electrical connection. Furthermore, the conductive layer 54 is formed by increasing the thickness of the ultra-thin metal foil layer 41A on both surfaces by the electrolytic copper plating and/or the electroless copper plating. The method of electrolytic copper plating and/or electroless copper plating is not particularly limited, and known methods can be used. This copper plating may be only any one of electrolytic copper plating and electroless copper plating, but it is preferable to give both electrolytic copper plating and electroless copper plating.

(film thickness adjustment) Next, for example, after the electrolytic/electroless copper plating treatment, the conductive layer 54 may be subjected to conventional processing such as etching treatment to adjust the film thickness of the conductive layer 54 to a desired thickness if necessary.

(patterned) Next, for example, after the entire surface of the conductor layer 54 can be implemented as needed, a dry film photoresist is laminated, and then, after covering the negative photomask, a circuit pattern is printed with an exposure machine, and the dry film photoresist is developed with a developer to form Etch photoresist. After the etching photoresist is formed, for example, the substrate 40 is moved on a plurality of rollers with the carrier remaining part 40C as the front side by a horizontal etching line, and the etching process is performed, and then the non-etching photoresist is removed with an aqueous solution of ferric chloride or the like. The conductive layer 54 of the resistance part. In this embodiment, at least a part of the outer peripheral region 40B of the substrate 40 is provided with a thick carrier remaining portion 40C, so the substrate 40 can be easily transported using the carrier remaining portion 40C as a guide. Then, by removing the photoresist, as shown in FIG. 9(C), a wiring substrate 50 in which wiring conductors 52 are formed on both surfaces of the insulating layer 51 can be formed.

In addition, this embodiment can be applied to other interlayer connection methods as described in the first embodiment. In addition, as described in the first embodiment, the wiring substrate 50 is not limited to a package substrate for mounting a semiconductor element with a two-layer structure, and may form a semiconductor element having a further assembly structure such as a four-, five-, or six-layer structure. Package substrate for mounting. Furthermore, the wiring board 50 is the same as the first embodiment, and semiconductor elements such as bare chips can be mounted as needed.

Thus, according to the present embodiment, at least a part of the outer peripheral region 40B is provided with the carrier remaining portion 40C in which the carrier 41B remains. Therefore, similarly to the first embodiment, the substrate 40 can be transported using the carrier remaining portion 40C as a guide. Accordingly, it is not necessary to connect and peel off the guide plate, and labor and cost can be reduced.

[Fourth Embodiment] FIG. 10 shows the structure of a substrate 60 according to a fourth embodiment of the present invention. The substrate 60 is a slit 41C cut from the surface layer of the carrier 41B to the ultra-thin metal foil layer 41A in the carrier 41B of the third laminate 43 of the third embodiment. That is, the substrate 60 is the substrate before the carrier 41B is provided with the notch 41C for forming the carrier remaining portion 40C and the carrier 41B is peeled off, and otherwise has the same configuration as the third embodiment, and can be manufactured in the same manner. In addition, after peeling off the carrier 41B other than the carrier remaining portion 40C, it can be used in the manufacture of the wiring board 50 in the same manner as in the third embodiment, and the same effects as in the third embodiment can be obtained. Therefore, the same reference numerals are assigned to the same constituent elements as those of the third embodiment, and detailed description thereof will be omitted. [Example]

[Example 1] The substrate 10 is formed as follows, and the wiring substrate 40 is formed using this substrate 10 . <Manufacturing of substrate 10> (1st laminate forming step) As the core resin layer 16, a B-stage prepreg was prepared by impregnating bismaleimide triazine resin (BT resin) into glass cloth (glass fiber) (thickness: 25 μm: GHPL-830NS SF74 manufactured by Mitsubishi Gas Chemical Co., Ltd.) , on both sides of the core resin layer 16, the copper foil (the first metal layer) of the peeling layer (manufactured by JX Nippon Oil Metal Co., Ltd., trade name: PCS) will be coated on the copper foil with a thickness of 2 μm. 12) Arrange in such a way that the peel-off layer contacts the core resin layer 16, and then impregnate the bismaleimide triazine resin (BT resin) on the glass cloth (glass fiber) to form a B-stage prepreg Material (first insulating resin layer 13; thickness 13 μm: GHPL-830NS SP64 manufactured by Mitsubishi Gas Chemical Co., Ltd.), and 12 μm copper foil (second metal layer 14; manufactured by Mitsui Metal Mining Co., Ltd., trade name: 3EC-M2S-VLP) ), laminated under the conditions of pressure 2.5±0.2MPa, temperature 220±2°C, and holding time 60 minutes under vacuum pressure to produce the first laminate 17 (see FIG. 3(A) and (B)).

(patterning step) Next, implement the entire surface of the first laminated body 17, and laminate a dry film photoresist (manufactured by Nichigo-Morton Co., Ltd., trade name : NIT225). Then, cover the negative photomask, print the circuit pattern with a parallel exposure machine, develop the dry film photoresist with 1% sodium carbonate aqueous solution to form an etching photoresist, and remove the second metal of the non-etching photoresist part with an aqueous solution of ferric chloride After layer 14, the dry film photoresist is removed with aqueous sodium hydroxide solution, and a pattern is formed on the second metal layer 14 (see FIG. 3(C)).

(2nd laminate forming step) Next, the surface of the patterned second metal layer 14 is roughened using a copper surface roughening solution (manufactured by MEC Co., Ltd., trade name: CZ-8101), and on the surface of the second metal layer 14, the The prepreg (second insulating resin layer 15; thickness 15 μm: GHPL-830NS SP68 manufactured by Mitsubishi Gas Chemical) is impregnated with glass cloth (glass fiber) to form a B-stage prepreg. 2μm copper foil with 18μm carrier copper foil (extremely thin metal foil layer 11 with carrier; manufactured by Mitsui Metal Mining Co., Ltd., trade name: MTFL), pressurized with a vacuum at a pressure of 2.5±0.2MPa, a temperature of 220±2°C, and maintained Lamination was carried out under the condition of a time of 60 minutes to produce the second laminate 18 (see FIG. 3(D)).

(cutting step) Next, for the second laminated body 18, in order to form the carrier remaining portion 10C in the outer peripheral region 10B, along one of the short sides, the outer peripheral region 10B of the carrier 11B, or the boundary between the outer peripheral region 10B and the circuit formation region 10A and In the outer peripheral region 10B, a notch 11C is cut by a cutter (see FIG. 4(E)). The incision 11C is cut at a position 40mm away from the side.

(carrier stripping step) Next, with respect to the carrier 11B in which the slit 11C has been cut, a portion of the carrier remaining portion 10C along one of the short sides is left, and the other portion is peeled off. Thereby, 10 C of carrier remaining parts with a width of 40 mm were formed along one of the short sides (refer FIG.4(F)).

(Core resin layer separation step) Then, a physical force is applied to the boundary between the copper foil (first metal layer 12 ) and the prepreg (core resin layer 16 ) of the peel-off layer on the second laminate 18 to obtain the circuit formation region 10A. A substrate 10 having a thickness of 39 μm (see FIG. 1 ).

<Manufacturing of wiring substrate 20 using substrate 10> (Formation of non-through holes) On both sides of the substrate 10, by using a carbon dioxide laser processing machine (manufactured by Hitachi Via Machinery Co., Ltd., product name: LC-1C/21) with a beam irradiation diameter of Φ0.21 mm, a frequency of 500 Hz, and a pulse width of 10 μs, one time 1 Hole processing forms non-through holes 23 reaching the surface of the second metal layer 14 (see FIG. 5(A)). Then, use a sodium permanganate aqueous solution with a temperature of 80±5°C and a concentration of 55±10 g/L to perform desmearing treatment.

(Interlayer connection and formation of the third metal layer) Next, electroless copper plating was applied to a thickness of 0.4 μm to 0.8 μm, and electrolytic copper plating was performed to a thickness of 8 μm to form the third metal layer 24 (see FIG. 5(B) ). Thereby, the first metal layer 12 and the ultra-thin metal foil layer 11A pass through the second metal layer 14 and are electrically connected through the non-through hole 23 .

(patterned) Next, the entire surface of the third metal layer 24 was covered, and a dry film photoresist (manufactured by Nichigo-Morton Co., Ltd., trade name: NIT225) was laminated at a temperature of 110±10° C. and a pressure of 0.50±0.02 MPa. Next, after covering the negative photomask, print the circuit pattern with a parallel exposure machine, and develop the dry film photoresist with 1% sodium carbonate aqueous solution to form an etching photoresist, and use a horizontal etching line to form the edge of the carrier residual part 10C As the front, the substrate 10 is moved on a plurality of rollers and subjected to etching treatment, and the third metal layer 24 of the non-etched photoresist part is removed with an aqueous solution of ferric chloride. Then, the dry film resist was removed with an aqueous sodium hydroxide solution to fabricate the wiring board 20 (see FIG. 5(D) ).

The obtained wiring board 20 is subjected to a solder resist forming process and a gold plating process, and is subjected to a cutting process into a package size. The finished wiring board 20 is not damaged, and the wiring board 20 can be easily and favorably manufactured using the substrate 10 .

[Example 2] The substrate 40 is formed as follows, and the wiring substrate 50 is formed using this substrate 40 . <Manufacturing of substrate 40> Copper-clad laminates (HL832NS manufactured by Mitsubishi Gas Chemical Co., Ltd., 2 μm copper foil with 18 μm carrier copper foil) with a thickness of 40 μm and a copper foil with a carrier are prepared (refer to FIG. Next to one of the short sides, a slit 41C is cut by a cutting machine in the outer peripheral region 40B of the carrier 41B, or the boundary between the outer peripheral region 40B and the circuit formation region 40A and the outer peripheral region 40B. The incision 41C is cut at a position 40mm away from the side. Next, with respect to the carrier 41B in which the slit 41C has been cut, a portion of the carrier remaining portion 40C along one of the short sides is left, and the other portion is peeled off. Thereby, the board|substrate 40 (refer FIG. 7) in which the carrier remaining part 40C of width 40mm was formed along one side of the short side was manufactured.

<Manufacturing of wiring substrate 50 using substrate 40> (Formation of through holes) Through-holes 53 were formed on the substrate 40 with a carbon dioxide laser processing machine (manufactured by Hitachi Via Machinery Co., Ltd., trade name: LC-1C/21) under the conditions of beam irradiation diameter Φ0.21 mm, frequency 500 Hz, and pulse width 10 μs. (Refer to FIG. 9(A)). Then, use a sodium permanganate aqueous solution with a temperature of 80±5°C and a concentration of 55±10 g/L to perform desmearing treatment.

(Interlayer connection and formation of conductor layer) Next, electroless copper plating was applied to a thickness of 0.4 μm to 0.8 μm, and electrolytic copper plating was performed to a thickness of 8 μm to form a conductive layer 54 (see FIG. 9(B) ). Thereby, the ultrathin metal foil layer 41A is electrically connected.

(patterned) Next, the entire surface of the conductor layer 54 is laminated with a dry film photoresist (manufactured by Nichigo-Morton Co., Ltd., trade name: NIT225) at a temperature of 110±10° C. and a pressure of 0.50±0.02 MPa. Next, after covering the negative photomask, print the circuit pattern with a parallel exposure machine, and develop the dry film photoresist with 1% sodium carbonate aqueous solution to form an etching photoresist, and use a horizontal etching line to form the edge of the carrier residual part 40C As the front end, the substrate 40 is moved on a plurality of rollers and subjected to etching treatment, and the conductor layer 54 without etching the photoresist part is removed with an aqueous solution of ferric chloride. Then, the dry film resist was removed with an aqueous sodium hydroxide solution to fabricate a wiring board 50 (see FIG. 9(C) ).

The obtained wiring board 50 is subjected to a solder resist forming process and a gold plating process, and is subjected to a cutting process into a package size. The finished wiring board 50 is not damaged, and the wiring board 50 can be easily and favorably manufactured using the substrate 40 .

[Comparative Example 1] In the step of peeling off the carrier, except that the carrier with a thickness of 18 μm was completely peeled off, a substrate was prepared by the same steps as in Example 1. For the produced substrate, as in Example 1, a through-hole was formed by a carbon dioxide laser processing machine, and after the desmearing treatment was completed, electroless copper plating or electrolytic copper plating was used to perform plating with a thickness of 8 μm. Next, in the same manner as in Example 1, a dry film photoresist was laminated, and the dry film photoresist was developed. Then, use a horizontal etching line to move on multiple rollers, and try to remove the copper foil on the non-etched photoresist part with an aqueous solution of ferric chloride, but the substrate is caught by the conveying roller of the horizontal etching line, causing the substrate to deform. damaged.

[Comparative Example 2] In addition to using prepreg with a thickness of 41 μm (GHPL-830NS SI72 manufactured by Mitsubishi Gas Chemical) for the first insulating resin layer, and prepreg with a thickness of 45 μm (GHPL-830NS SI74 manufactured by Mitsubishi Gas Chemical) for the second insulating resin layer, and In the step of peeling off the carrier, except that the carrier with a thickness of 18 μm was completely peeled off, a substrate was prepared by the same steps as in Example 1. The thickness of the substrate (the thickness of the circuit formation region) was 97 μm. That is, in Comparative Example 2, the carrier was completely peeled off, and the thickness of the substrate (circuit formation region) was thick. For the produced substrate, as in Example 1, a through-hole was formed by a carbon dioxide laser processing machine, and after the desmearing treatment was completed, electroless copper plating or electrolytic copper plating was used to perform plating with a thickness of 8 μm. Next, in the same manner as in Example 1, a dry film photoresist was laminated, and the dry film photoresist was developed. Then, use a horizontal etching line to move on a plurality of rollers, and remove the copper foil of the non-etched photoresist part with an aqueous solution of ferric chloride. Then, the dry film resist was removed with an aqueous sodium hydroxide solution to fabricate a wiring board.

Solder resist forming process and gold plating process were performed on the obtained wiring board, and cutting process was given to package size. The finished wiring board was not damaged, and the wiring board could be manufactured well, but it was thick and it was difficult to cope with thinning.

[Comparative Example 3] A copper-clad laminate with a 40 μm thick copper foil with a carrier (HL832NS manufactured by Mitsubishi Gas Chemical Co., Ltd., 2 μm copper foil with a 18 μm carrier copper foil) was prepared as in Example 2, and the 18 μm carrier was completely peeled off to obtain a substrate. Next, as in Example 2, a through hole was formed by a carbon dioxide laser processing machine, and after the desmearing treatment was completed, electroless copper plating or electrolytic copper plating was used to perform plating with a thickness of 8 μm. Next, in the same manner as in Example 2, a dry film photoresist was laminated, and the dry film photoresist was developed. Then, use a horizontal etching line to move on multiple rollers, and try to remove the copper foil on the non-etched photoresist part with an aqueous solution of ferric chloride, but the substrate is caught by the conveying roller of the horizontal etching line, causing the substrate to deform. damaged.

[Comparative Example 4] A copper-clad laminate with a 40 μm thick copper foil with a carrier (HL832NS manufactured by Mitsubishi Gas Chemical Co., Ltd., 2 μm copper foil with a 18 μm carrier copper foil) was prepared as in Example 2, and the 18 μm carrier was completely peeled off to obtain a substrate. Next, as in Example 2, a through hole was formed by a carbon dioxide laser processing machine, and after the desmearing treatment was completed, electroless copper plating or electrolytic copper plating was used to perform plating with a thickness of 8 μm. Next, in the same manner as in Example 2, a dry film photoresist was laminated, and the dry film photoresist was developed. Then, in order to use the horizontal etching line and remove the copper foil of the non-etched photoresist part with ferric chloride aqueous solution, a guide plate with a thickness of 0.10 mm was attached to one side of the substrate with an adhesive tape. Use the pasted guide plate as the front, and remove the copper foil of the non-etched photoresist part with the ferric chloride aqueous solution through the horizontal etching line. Then, the dry film resist was removed with an aqueous sodium hydroxide solution to fabricate a wiring board.

In order to perform a solder resist forming process on the obtained wiring board, the lead plate was removed and a solder resist was applied. Next, in order to develop the solder resist on the horizontal line, the guide plate is attached to the substrate again. Next, in order to perform gold plating and cut into package size, the lead plate is removed again and cut into package size. According to Comparative Example 2, although the wiring board can be fabricated, it is very troublesome to install and remove the lead plate many times. In addition, due to poor installation of the guide plate, there is a risk of damage to the substrate, and stress is applied to the substrate during the removal operation, which may cause damage to the substrate. Further, there is also a risk of bringing the liquid medicine into the next step at the interface of the adhesive tape of the guide plate. [Industrial Utilization]

The present invention can be used for wiring substrates of semiconductor packages.

10: Substrate 10A: Circuit formation area 10B: Peripheral area 10C: carrier residue 11: Ultra-thin metal foil layer with carrier 11A: Very thin metal foil layer 11B: carrier 11C: Incision 12: The first metal layer 13: The first insulating resin layer 14: The second metal layer 15: Second insulating resin layer 16: Core resin layer 17: The first laminate 18: The second laminate 20: Wiring substrate 21: Insulation layer 22: wiring conductor 23: Non-through hole 24: The third metal layer 30A, 30B: substrate 40: Substrate 40A: Circuit formation area 40B: Peripheral area 40C: carrier residue 41: Ultra-thin metal foil layer with carrier 41A: Very thin metal foil layer 41B: carrier 41C: Incision 42: resin layer 43: The third laminate 50: Wiring substrate 51: Insulation layer 52: wiring conductor 53: Through hole 54: conductor layer 60: Substrate

[ Fig. 1 ] is a diagram showing a cross-sectional structure of a substrate according to a first embodiment of the present invention. [ FIG. 2 ] is a diagram showing the planar configuration of the substrate shown in FIG. 1 . [ Fig. 3 ] is a diagram showing the manufacturing steps of the substrate shown in Fig. 1 . [ Fig. 4 ] is a diagram showing the steps following Fig. 3 . [ FIG. 5 ] is a diagram showing the steps of manufacturing a wiring board using the substrate shown in FIG. 1 . [ Fig. 6 ] is a diagram showing the structure of a substrate according to a second embodiment of the present invention. [ Fig. 7 ] is a diagram showing the structure of a substrate according to a third embodiment of the present invention. [ FIG. 8 ] is a diagram showing the manufacturing steps of the substrate shown in FIG. 7 . [ FIG. 9 ] is a diagram showing the steps of manufacturing a wiring board using the substrate shown in FIG. 7 . [ Fig. 10 ] is a diagram showing the structure of a substrate according to a fourth embodiment of the present invention.

10: Substrate

10A: Circuit formation area

10B: Peripheral area

10C: carrier residue

11: Ultra-thin metal foil layer with carrier

11A: Very thin metal foil layer

11B: carrier

12: The first metal layer

13: The first insulating resin layer

14: The second metal layer

15: Second insulating resin layer

Claims (5)

A substrate, which has a laminated carrier and an ultra-thin metal foil layer attached to the carrier on at least one side of the substrate, characterized by having a circuit formation area, and an outer peripheral area provided outside the circuit formation area; The circuit formation area is the ultra-thin metal foil layer with the carrier removed from the ultra-thin metal foil layer with a carrier, and the thickness is 80 μm or less; The carrier remains in at least a part of the outer peripheral region, and a carrier remaining portion where the carrier covers the surface of the ultra-thin metal foil layer is provided. A substrate, which has a laminated carrier and an ultra-thin metal foil layer attached to the carrier on at least one side of the substrate, characterized by having a circuit formation area, and an outer peripheral area provided outside the circuit formation area; In order to remove the carrier in the circuit formation region and leave the carrier in at least a part of the peripheral region to form a carrier remaining portion, the boundary between the peripheral region and the circuit formation region and the peripheral region At least one side of the carrier is provided with a cutout from the surface layer of the carrier to the ultra-thin metal foil layer. The substrate according to claim 1 or 2, wherein the width of the peripheral region is in the range of 1 mm to 300 mm. A method of manufacturing a wiring substrate, which uses the substrate as described in claim 1 or 2, characterized in that it includes In the conveying step, the carrier remaining portion is set as the front side, and the substrate is conveyed by moving on a plurality of rollers. The method of manufacturing a wiring board according to claim 4, wherein etching is performed in the transferring step.

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