WO2023054517A1

WO2023054517A1 - Method of manufacturing package substrate for mounting semiconductor element

Info

Publication number: WO2023054517A1
Application number: PCT/JP2022/036276
Authority: WO
Inventors: 慎也喜多村; 晃樹小松; 和晃川下; 隼斗中川; 豪志信國
Original assignee: Ｍｇｃエレクトロテクノ株式会社; 米沢ダイヤエレクトロニクス株式会社
Priority date: 2021-09-30
Filing date: 2022-09-28
Publication date: 2023-04-06
Also published as: TW202336944A

Abstract

Problem] To provide a method of manufacturing a package substrate for mounting a semiconductor element whereby it is possible to suppress damage when separating a core resin layer or during processing steps subsequent to separation. [Solution] A first wiring conductor 12 through a (n+2)th wiring conductor 15B and a first insulating resin layer 13A through a (n+1)th insulating resin layer 15A are laminated on a first metal layer 11B that comprises a separation means in a first laminate 11 obtained by laminating a core resin layer 11A and the first metal layer 11B, a solder resist layer 16A is formed thereupon, and then at least the core resin layer is separated by the separation means.

Description

Manufacturing method of package substrate for mounting semiconductor element

The present invention relates to a method of manufacturing a semiconductor device mounting package substrate on which a semiconductor device is mounted.

In recent years, the sophistication and miniaturization of semiconductor packages, which are widely used in electronic devices, communication devices, personal computers, etc., are accelerating more and more. Along with this, there is a demand for thinner printed wiring boards and package substrates for mounting semiconductor elements in semiconductor packages. As a thin printed wiring board and a package substrate for mounting a semiconductor element, for example, a so-called coreless substrate is known in which a metal layer and an insulating layer are laminated on a core resin layer and then the core resin layer is peeled off (for example, patent Reference 1).

International publication WO2020/121651

However, in such a coreless substrate, as the thickness of the metal layer and the insulating layer becomes thinner, the metal layer and the insulating layer may be damaged when the core resin layer is peeled off or in the processing step after the peeling. There was a problem that there is

The present invention has been made based on such problems, and provides a method for manufacturing a package substrate for mounting a semiconductor element, which can suppress breakage in the processing steps when the core resin layer is peeled off or after the peeling. intended to provide

The present invention is as follows.
[1]
a first laminated body preparing step of preparing a first laminated body having a core resin layer and a first metal layer provided on at least one side of the core resin layer and provided with a peeling means;
a first wiring forming step of applying at least one of electrolytic plating and electroless plating on the first metal layer to form a first wiring conductor;
A second laminate is formed by laminating a first insulating resin layer and a second metal layer in this order on the surface of the first laminate on which the first wiring conductor is provided. A second laminate forming step to
A non-through hole reaching the first wiring conductor is formed in the first insulating resin layer, and at least one of electrolytic plating and electroless plating is applied to the surface in which the non-through hole is formed to form a second wiring. a second wiring forming step of forming a conductor;
After the second wiring forming step, the (m+1)-th insulating resin layer and the (m+2)-th insulating resin layer are further formed on the surface on which the (m+1)-th wiring conductor of the (m+1)-th laminate is provided. and a metal layer in this order to form an (m+2)-th laminate, and the (m+1)-th wiring on the (m+1)-th insulating resin layer. (m+2)th wiring formation of forming a non-through hole reaching a conductor and applying at least one of electrolytic plating and electroless plating to the surface in which the non-through hole is formed to form a (m+2)th wiring conductor The steps are repeated n times in this order, and a wiring lamination step (m and n are an integer of 1 or more, provided that m ≤ n);
forming a solder-resist layer on the (n+1)-th insulating resin layer and the (n+2)-th wiring conductor so that the (n+2)-th wiring conductor is partially exposed; a solder resist layer forming step;
a core resin layer stripping step of stripping at least the core resin layer from the solder resist formed body by the stripping means to obtain a core resin layer-removed body;
A method of manufacturing a package substrate for mounting a semiconductor device, comprising:
[2]
The method of manufacturing a package substrate for mounting a semiconductor element according to [1], wherein the core resin layer has a thickness of 1 μm or more.
[3]
The method of manufacturing a package substrate for mounting a semiconductor element according to [1], wherein the first metal layer has a thickness of 100 μm or less.
[4]
The method of manufacturing a package substrate for mounting a semiconductor element according to [1], wherein the thickness of the first metal layer from the end face of the first wiring conductor side to the peeling means is 6 μm or more.
[5]
The method for manufacturing a package substrate for mounting a semiconductor element according to [1], wherein the first laminate has a thickness of 20 μm or more and 1000 μm or less.
[6]
The method of manufacturing a package substrate for mounting a semiconductor element according to [1], wherein each of the first insulating resin layer to the (n+1)th insulating resin layer has a thickness of 0.1 μm or more and 100 μm or less.
[7]
After the solder-resist layer forming step and before the core resin layer peeling step, a supporting substrate having a thermoplastic resin layer is laminated on the surface of the solder-resist layer forming body provided with the solder-resist layer. The method for manufacturing a package substrate for mounting a semiconductor element according to [1], including a support substrate lamination step.

According to the present invention, a solder resist layer is formed on the (n+1)-th insulating resin layer and the (n+2)-th wiring conductor so that the (n+2)-th wiring conductor is partially exposed, and then peeled off. Since at least the core resin layer is peeled off in the means, the solder resist layer separates the first wiring conductor to the (n+2)th wiring conductor and the first insulating resin layer to the (n+1)th insulating resin layer. can be reinforced and their damage can be suppressed. Therefore, a package substrate for mounting a semiconductor element can be manufactured satisfactorily.

Also, after forming a solder resist layer and laminating a support substrate thereon, at least the core resin layer 11A is peeled off, so that the first wiring conductor 12 to the (n+2)th wiring conductor 15B, and The first insulating resin layer 13A to the (n+1)th insulating resin layer 15A can be reinforced more firmly.

Furthermore, if the thickness of the first metal layer from the end face of the first wiring conductor side to the peeling means is set to 6 μm or more, when at least the core resin layer is peeled off by the peeling means, the first wiring conductor is separated from the first wiring conductor by the peeling means. The (n+2) wiring conductors and the first insulating resin layer to the (n+1)th insulating resin layer can be reinforced more firmly.

4A to 4C are diagrams showing each step of the manufacturing method of the package substrate for mounting a semiconductor element according to the first embodiment; 1. It is a figure showing each process following FIG. It is a figure showing each process following FIG. It is a figure showing each process of the manufacturing method of the package substrate for mounting a semiconductor element which concerns on 2nd Embodiment. FIG. 5 is a diagram showing each step following FIG. 4;

Hereinafter, the mode for carrying out the present invention (hereinafter referred to as "embodiment") will be described in detail, but the present invention is not limited to this, and various modifications can be made without departing from the scope of the invention. It is possible.

[First Embodiment]
1 to 3 show each step of a method for manufacturing a package substrate for mounting a semiconductor element according to the first embodiment. The method for manufacturing the package substrate for mounting a semiconductor element includes, for example, the following steps (first laminate preparation step, first wiring formation step, second laminate formation step, second wiring formation step). , wiring lamination step, solder resist layer forming step, and core resin layer peeling step).

<First laminate preparation step>
First, for example, as shown in FIG. 1A, a core resin layer 11A is provided on at least one side of the core resin layer 11A as a base substrate for forming a package substrate for mounting a semiconductor element, and A first laminate 11 having a first metal layer 11B provided with peeling means is prepared (first laminate preparation step). Note that FIG. 1 shows the case where the first metal layer 11B is provided on one side of the core resin layer 11A. Although not shown, the first metal layer 11B may be provided on both sides of the core resin layer 11A.

(Core resin layer 11A)
The core resin layer 11A is not particularly limited. It can be composed of a material or the like. The thickness of the core resin layer 11A is appropriately set as desired, and is not particularly limited, but is preferably 1 μm or more, for example. This is because if the thickness of the core resin layer 11A is less than 1 μm, the insulating resin layer formed in the subsequent process may be defective in molding.

"Prepreg" is made by impregnating or coating a base material with an insulating material such as a resin composition. The substrate is not particularly limited, and known substrates used for various laminates for electrical insulating materials can be appropriately used. Materials constituting the substrate include, for example, inorganic fibers such as E-glass, D-glass, S-glass, and Q-glass; organic fibers such as polyimide, polyester, or tetrafluoroerylene; and mixtures thereof. The substrate is not particularly limited, and for example, those having a shape such as woven fabric, nonwoven fabric, roving, chopped strand mat, surfacing mat and the like can be used as appropriate. The material and shape of the base material are selected according to the intended use and performance of the molded article, and if necessary, it is possible to use one or more kinds of materials and shapes.

The thickness of the base material is not particularly limited as long as the thickness of the core resin layer 11A is within the range described above. In addition, as the base material, one surface-treated with a silane coupling agent or the like or one subjected to mechanical fiber opening treatment can be used, and these base materials are suitable in terms of heat resistance, moisture resistance, and workability. is.

The insulating material is not particularly limited, and a known resin composition used as an insulating material for package substrates for mounting semiconductor elements can be appropriately selected and used. As the resin composition, a thermosetting resin having good heat resistance and chemical resistance can be used as a base. The thermosetting resin is not particularly limited, and examples thereof include polyimide resins, phenol resins, epoxy resins, cyanate resins, maleimide resins, modified polyphenylene ethers, bismaleimide triazine resins, isocyanate resins, benzocyclobutene resins and vinyl resins. be done. These thermosetting resins may be used singly or in combination of two or more.

The polyimide resin is not particularly limited, and commercially available products can be appropriately selected and used. For example, a solvent-soluble polyimide resin synthesized by the production method described in JP-A-2005-15629 or a block-copolymerized polyimide resin can be used. Examples of block copolymer polyimide resins include block copolymer polyimide resins described in International Publication WO2010-073952. Specifically, the block copolymerized polyimide resin comprises structure A in which an imide oligomer comprising a second structural unit is bound to the end of an imide oligomer comprising a first structural unit, and a second structural unit. There is no particular limitation as long as it is a copolymerized polyimide resin having a structure in which Structure B, in which an imide oligomer composed of a first structural unit is bonded to the end of the imide oligomer, is alternately repeated. Note that the second structural unit is different from the first structural unit. These block copolymer polyimide resins are produced by reacting a tetracarboxylic dianhydride and a diamine in a polar solvent to form an imide oligomer, and then further tetracarboxylic dianhydride and another diamine or another tetracarboxylic acid. It can be synthesized by a sequential polymerization reaction in which an acid dianhydride and a diamine are added and imidized. One type of these polyimide resins may be used alone, or two or more types may be mixed and used.

The phenolic resin is not particularly limited, and one or more molecules per molecule (preferably 2 to 12, more preferably 2 to 6, still more preferably 2 to 4, more preferably 2 or 3, still more preferably 2 ) can be used as long as they are compounds or resins having a phenolic hydroxy group. For example, bisphenol A type phenol resin, bisphenol E type phenol resin, bisphenol F type phenol resin, bisphenol S type phenol resin, phenol novolak resin, bisphenol A novolac type phenol resin, glycidyl ester type phenol resin, aralkyl novolac type phenol resin, biphenyl Aralkyl-type phenolic resins, cresol novolac-type phenolic resins, polyfunctional phenolic resins, naphthol resins, naphthol novolak resins, polyfunctional naphthol resins, anthracene-type phenolic resins, naphthalene skeleton-modified novolac-type phenolic resins, phenol aralkyl-type phenolic resins, naphthol aralkyl-type phenolic resins Phenol resins, dicyclopentadiene type phenol resins, biphenyl type phenol resins, alicyclic phenol resins, polyol type phenol resins, phosphorus-containing phenol resins and hydroxyl group-containing silicone resins can be mentioned. These phenol resins may be used singly or in combination of two or more.

　Among thermosetting resins, epoxy resins are excellent in heat resistance, chemical resistance, and electrical properties, and are relatively inexpensive, so they can be suitably used as insulating materials. As the epoxy resin, one or more (preferably 2 to 12, more preferably 2 to 6, still more preferably 2 to 4, still more preferably 2 or 3, still more preferably 2) epoxy groups per molecule. There are no particular limitations as long as the compound or resin has , cresol novolak type epoxy resin, bisphenol A novolac type epoxy resin, diglycidyl ether of biphenol, diglycidyl ether of naphthalenediol, diglycidyl ether of phenols, diglycidyl ether of alcohols, and Alkyl-substituted products, halides, and hydrogenated products thereof are included. One type of these epoxy resins may be used alone, or two or more types may be mixed and used. In addition, the curing agent used with this epoxy resin can be used without limitation as long as it cures the epoxy resin. Phosphorus compounds and halides thereof may be mentioned. These epoxy resin curing agents may be used singly or in combination of two or more.

A cyanate resin is a resin that, when heated, produces a cured product with repeating units of triazine rings, and the cured product has excellent dielectric properties. For this reason, it is suitable especially when high-frequency characteristics are required. As the cyanate resin, one or more (preferably 2 to 12, more preferably 2 to 6, more preferably 2 to 4, still more preferably 2 or 3, still more preferably 2) cyanato groups per molecule ( It is not particularly limited as long as it is a compound or resin having an aromatic moiety substituted with a cyanate ester group) in the molecule, but examples include 2,2-bis(4-cyanatophenyl)propane, bis(4-cyanato phenyl)ethane, 2,2-bis(3,5dimethyl-4-cyanatophenyl)methane, 2,2-(4-cyanatophenyl)-1,1,1,3,3,3-hexafluoropropane , α,α'-bis(4-cyanatophenyl)-m-diisopropylbenzene, cyanate esters of phenol novolak and alkylphenol novolak. Among them, 2,2-bis(4-cyanatophenyl)propane is preferable because the balance between the dielectric properties and the curability of the cured product is particularly good and the cost is low. These cyanate resins such as cyanate ester compounds may be used singly or in combination of two or more. A part of the cyanate ester compound may be previously oligomerized into a trimer or a pentamer.

Furthermore, a curing catalyst or curing accelerator can be used in combination with the cyanate resin. As the curing catalyst, for example, metals such as manganese, iron, cobalt, nickel, copper and zinc can be used. Specifically, organic metal salts such as 2-ethylhexanoate and octylate, and acetylacetone Mention may be made of organometallic complexes such as complexes. Curing catalysts may be used singly or in combination of two or more.

Phenols are preferably used as the curing accelerator, and monofunctional phenols such as nonylphenol and paracumylphenol; bifunctional phenols such as bisphenol A, bisphenol F and bisphenol S; or phenol novolak and cresol novolak. can be used. A hardening accelerator may be used individually by 1 type, and may be used in mixture of 2 or more types.

The maleimide resin has 1 or more (preferably 2 to 12, more preferably 2 to 6, still more preferably 2 to 4, still more preferably 2 or 3, still more preferably 2) maleimide groups in one molecule. A generally known compound or resin can be used as long as it has a compound or resin. For example, 4,4-diphenylmethanebismaleimide, phenylmethanemaleimide, m-phenylenebismaleimide, 2,2-bis(4-(4-maleimidophenoxy)-phenyl)propane, 3,3-dimethyl-5,5-diethyl -4,4-diphenylmethanebismaleimide, 4-methyl-1,3-phenylenebismaleimide, 1,6-bismaleimide-(2,2,4-trimethyl)hexane, 4,4-diphenyletherbismaleimide, 4,4 -diphenylsulfone bismaleimide, 1,3-bis(3-maleimidophenoxy)benzene, 1,3-bis(4-maleimidophenoxy)benzene, polyphenylmethanemaleimide, novolac-type maleimide, biphenylaralkyl-type maleimide, and these maleimide compounds or a prepolymer of a maleimide compound and an amine compound, but is not particularly limited. One type of these maleimide resins may be used alone, or two or more types may be mixed and used.

Modified polyphenylene ether is useful from the viewpoint that it can improve the dielectric properties of the cured product. Modified polyphenylene ethers include, for example, poly(2,6-dimethyl-1,4-phenylene) ether, an alloyed polymer of poly(2,6-dimethyl-1,4-phenylene) ether and polystyrene, poly(2 ,6-dimethyl-1,4-phenylene)ether and styrene-butadiene copolymer, alloyed polymer of poly(2,6-dimethyl-1,4-phenylene)ether and styrene-maleic anhydride copolymer, poly Alloyed polymers of (3,6-dimethyl-1,4-phenylene) ether and polyamides, alloyed polymers of poly(2,6-dimethyl-1,4-phenylene) ethers and styrene-butadiene-acrylonitrile copolymers, oligophenylene ether and the like. In addition, in order to impart reactivity and polymerizability to polyphenylene ether, functional groups such as amine groups, epoxy groups, carboxylic groups, and styryl groups are introduced into the polymer chain ends, and amine groups and epoxy groups are introduced into the polymer chain side chains. , a carboxyl group, a styryl group, and a methacryl group may be introduced.

The isocyanate resin is not particularly limited, and includes, for example, an isocyanate resin obtained by a dehydrohalogenation reaction between a phenol and a cyanogen halide. Examples of isocyanate resins include 4,4'-diphenylmethane diisocyanate MDI, polymethylene polyphenyl polyisocyanate, tolylene diisocyanate, and hexamethylene diisocyanate. One type of these isocyanate resins may be used alone, or two or more types may be mixed and used.

The benzocyclobutene resin is not particularly limited as long as it contains a cyclobutene skeleton, but for example, divinylsiloxane-bisbenzocyclobutene (manufactured by Dow Chemical Co.) can be used. One type of these benzocyclobutene resins may be used alone, or two or more types may be mixed and used.

The vinyl resin is not particularly limited as long as it is a polymer or copolymer of vinyl monomers. Vinyl monomers are not particularly limited, and examples include (meth)acrylic acid ester derivatives, vinyl ester derivatives, maleic acid diester derivatives, (meth)acrylamide derivatives, styrene derivatives, vinyl ether derivatives, vinyl ketone derivatives, olefin derivatives, maleimide derivatives, (Meth)acrylonitrile may be mentioned. These vinyl resins may be used singly or in combination of two or more.

The resin composition used as the insulating material can also be blended with a thermoplastic resin in consideration of dielectric properties, impact resistance, film processability, and the like. The thermoplastic resin is not particularly limited, and examples thereof include fluororesin, polycarbonate, polyetherimide, polyetheretherketone, polyacrylate, polyamide, polyamideimide, and polybutadiene. One type of thermoplastic resin may be used alone, or two or more types may be mixed and used. Moreover, the fluororesin is not particularly limited, and examples thereof include polytetrafluoroethylene, polychlorotrifluoroethylene, polyvinylidene fluoride, and polyvinyl fluoride. One type of these fluororesins may be used alone, or two or more types may be mixed and used.

Among thermoplastic resins, polyamide-imide resins are useful from the viewpoint of excellent moisture resistance and good adhesion to metals. The raw material for the polyamideimide resin is not particularly limited, but examples of the acidic component include trimellitic anhydride and trimellitic anhydride monochloride, and examples of the amine component include metaphenylenediamine, paraphenylenediamine, 4 ,4'-diaminodiphenyl ether, 4,4'-diaminodiphenylmethane, bis[4-(aminophenoxy)phenyl]sulfone, 2,2'-bis[4-(4-aminophenoxy)phenyl]propane and the like. The polyamide-imide resin may be modified with siloxane to improve drying properties, and in this case, siloxane diamine can be used as the amino component. Considering film processability, it is preferable to use a polyamide-imide resin having a molecular weight of 50,000 or more.

Although the above thermoplastic resins have been described as insulating materials mainly used for prepregs, these thermoplastic resins are not limited to use as prepregs. For example, the core resin layer 11A may be formed by processing a film (film material) using the thermoplastic resin described above.

A filler may be mixed in the resin composition used as the insulating material. Examples of fillers include, but are not limited to, alumina, white carbon, titanium white, titanium oxide, zinc oxide, magnesium oxide, metal oxides (including hydrates) such as zirconium oxide, aluminum hydroxide, boehmite, Metal hydroxides such as magnesium hydroxide, silicas such as natural silica, fused silica, synthetic silica, amorphous silica, aerosil, and hollow silica, inorganic materials such as clay, kaolin, talc, mica, glass powder, quartz powder, and Shirasu balloons In addition to organic fillers (inorganic fillers), organic fillers ( organic fillers). These fillers may be used singly or in combination of two or more.

The resin composition used as an insulating material may contain an organic solvent. The organic solvent is not particularly limited, and aromatic hydrocarbon solvents such as benzene, toluene, xylene and trimethylbenzene; ketone solvents such as acetone, methyl ethyl ketone and methylinobutyl ketone; and tetrahydrofuran. Ether solvents; alcohol solvents such as isopropanol and butanol; ether alcohol solvents such as 2-methoxyethanol and 2-butoxyethanol; N-methylpyrrolidone, N,N-dimethylformamide and N,N-dimethylacetamide If desired, an amide-based solvent or the like can be used in combination. The amount of the solvent in the varnish when producing the prepreg is preferably in the range of 40% by mass to 80% by mass with respect to the entire resin composition. Further, the viscosity of the varnish is desirably in the range of 20 cP to 100 cP (20 mPa·s to 100 mPa·s).

The resin composition used as an insulating material may contain a flame retardant. Examples of flame retardants include, but are not limited to, bromine compounds such as decabromodiphenyl ether, tetrabromobisphenol A, tetrabromophthalic anhydride, and tribromophenol, triphenyl phosphate, trixylyl phosphate, and clay. Known and customary flame retardants such as phosphorus compounds such as dildiphenyl phosphate, red phosphorus and modified products thereof, antimony compounds such as antimony trioxide and antimony pentoxide, triazine compounds such as melamine, cyanuric acid and melamine cyanurate can be used. can.

For the resin composition used as an insulating material, if necessary, various additives such as the above-mentioned curing agent, curing accelerator, thermoplastic particles, coloring agents, ultraviolet opaque agents, antioxidants, reducing agents, etc. Additives and fillers can be added.

In the present embodiment, the prepreg is, for example, a resin composition (varnish is added so that the amount of the resin composition attached to the base material described above is 20% by mass or more and 90% by mass or less in terms of resin content in the prepreg after drying. ) is impregnated or coated on the substrate, and then dried by heating at a temperature of 100° C. or higher and 200° C. or lower for 1 minute to 30 minutes to obtain a prepreg in a semi-cured state (B stage state). As such a prepreg, for example, GHPL-830NS (product name) and GHPL-830NSF (product name) manufactured by Mitsubishi Gas Chemical Company, Inc. can be used.

(First metal layer 11B)
The first metal layer 11B can be made of, for example, a metal foil with a carrier. The metal foil with a carrier is, for example, laminated with a metal foil on a carrier via a release layer, which is a release means. A commercial product can also be used for the metal foil with a carrier, for example, MT18SD-HT5 (product name) manufactured by Mitsui Mining & Smelting Co., Ltd. can be used. The thickness of the first metal layer 11B is preferably 100 μm or less, for example. This is because a thinner metal layer is more advantageous for forming fine wiring. Moreover, it is more preferable that the thickness of the first metal layer 11B is 0.5 μm or more. Furthermore, the thickness of the first metal layer 11B is more preferably 1 μm or more and 100 μm or less.

The carrier can be composed of, for example, various metal foils, but is preferably composed of copper foil in terms of uniformity of thickness and corrosion resistance of the foil. The thickness of the carrier is thicker than the thickness of the metal foil, and can be, for example, 3 μm or more and 100 μm or less, preferably 5 μm or more and 50 μm or less, and more preferably 6 μm or more and 30 μm or less.

The release layer is for allowing the carrier to be easily separated from the metal foil. Materials for the release layer are not particularly limited, and various well-known materials can be used as appropriate. For example, organic materials include nitrogen-containing organic compounds, sulfur-containing organic compounds, and carboxylic acids. Examples of the nitrogen-containing organic compound include triazole compounds, imidazole compounds, etc. Among them, triazole compounds are preferable because they tend to have stable peelability. Examples of triazole compounds include 1,2,3-benzotriazole, carboxybenzotriazole, N',N'-bis(benzotriazolylmethyl)urea, 1H-1,2,4-triazole and 3-amino- 1H-1,2,4-triazole and the like. Examples of sulfur-containing organic compounds include mercaptobenzothiazole, thiocyanuric acid, 2-benzimidazolethiol, and the like. Examples of carboxylic acids include monocarboxylic acids, dicarboxylic acids, and the like. Inorganic materials include metals or alloys of at least one of Ni, Mo, Co, Cr, Fe, Ti, W, P, Zn, and oxides thereof. The thickness of the release layer can be, for example, 1 nm or more and 1 μm or less, preferably 5 nm or more and 500 nm or less.

The metal foil can be composed of, for example, various metal foils, but is preferably composed of copper foil in terms of thickness uniformity and corrosion resistance of the foil. The thickness of the metal foil is not particularly limited because it is appropriately set as desired.

The first metal layer 11B may be provided so that the carrier is on the core resin layer 11A side, or may be provided so that the metal foil is on the core resin layer 11A side. The thickness from the end face of the first metal layer 11B opposite to the core resin layer 11A to the peeling means, that is, the thickness from the end face of the first wiring conductor 12 side to the peeling means, which will be described later, should be 6 μm or more. is preferred, 10 µm or more is more preferred, and 15 µm or more is even more preferred. In the core resin layer peeling step to be described later, when at least the core resin layer 11A is peeled off, the first wiring conductor 12 to the (n+2)th wiring conductor 15B and the first insulating resin layer 13A to the (n+1)th wiring conductor 15B are removed. This is because it is possible to reinforce the insulating resin layer 15A and suppress the breakage thereof. In addition, the thickness from the end face of the first metal layer 11B opposite to the core resin layer 11A to the peeling means, that is, the thickness from the end face on the side of the first wiring conductor 12 described later to the peeling means is 70 μm or less. It is preferably 50 μm or less, more preferably 30 μm or less, and even more preferably 30 μm or less. This is because it takes a long time to remove the remaining first metal layer 11B in the first metal layer removing step, which will be described later.

In addition, the first metal layer 11B can also be composed of a metal foil having a peeling layer as a peeling means. In this case, the release layer is laminated so as to face the core resin layer 11A. Examples of the release layer include a layer containing at least a silicon compound. For example, the release layer can be formed by applying a silicon compound composed of a single silane compound or a combination of multiple silane compounds onto a metal foil. Incidentally, the means for applying the silicon compound is not particularly limited, and for example, known means such as coating can be used. An antirust treatment can be applied to the surface of the metal foil to be adhered to the release layer (to form an antirust treatment layer). Rust prevention treatment can be performed using any one of nickel, tin, zinc, chromium, molybdenum, cobalt, or alloys thereof. The thickness of the release layer is not particularly limited, but is preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 80 nm or less, and particularly preferably 20 nm or more and 60 nm or less, from the viewpoint of removability and peelability. As the metal foil, a copper foil is preferable from the viewpoint of uniformity of thickness and corrosion resistance of the foil. Also in this case, the thickness from the end face of the first metal layer 11B opposite to the core resin layer 11A to the peeling means, that is, the thickness from the end face of the first wiring conductor 12 side described later to the peeling means is the same as described above. It is preferable to do so.

The first laminated body 11 can be produced, for example, by laminating the core resin layer 11A and the first metal layer 11B, heating and pressurizing them, and crimping them. The thickness of the first laminate 11 can be, for example, 20 μm or more and 1000 μm or less, preferably 20 μm or more and 950 μm or less, and more preferably 20 μm or more and 900 μm or less.

<First Wiring Forming Step>
Next, for example, as shown in FIG. 1B, at least one of electrolytic plating and electroless plating is applied to the first metal layer 11B of the first laminate 11 to form the first wiring conductor. 12 is formed (first wiring forming step). Specifically, for example, a plating resist is laminated on the first metal layer 11B, a circuit pattern is printed on the plating resist, developed to form a plating resist pattern, and then patterned electrolytic plating is performed. , the first wiring conductor 12 is formed, and the plating resist is removed.

The plating resist is not particularly limited, and for example, a known one such as a commercially available dry film resist can be appropriately selected and used. Baking, development, and removal of the plating resist are also not particularly limited, and can be performed using known means and devices. Furthermore, pattern electrolytic plating for forming the first wiring conductors 12 is not particularly limited, and known methods can be used as appropriate. The first wiring conductor 12 is preferably formed by copper plating.

The thickness of the first wiring conductor is appropriately set as desired, and is not particularly limited. more preferred. The pattern width of the first wiring conductor is not particularly limited, and the width can be appropriately selected according to the application. be able to.

<Second laminate forming step>
Subsequently, for example, as shown in FIG. 1C, a first insulating resin layer 13A and a second metal layer are formed on the surface of the first laminate 11 on which the first wiring conductors 12 are provided. The layer 13B is laminated in this order to form the second laminated body 13 (second laminated body forming step).

Although the first insulating resin layer 13A is not particularly limited, it can be made of, for example, the same material as the core resin layer 11A (for example, prepreg or insulating film material). The thickness of the first insulating resin layer 13A is appropriately set as desired, and is not particularly limited. The following are more preferred.

The second metal layer 13B can be made of various metal foils, but is preferably made of copper foil in terms of thickness uniformity and corrosion resistance of the foil. The thickness of the second metal layer 13B is appropriately set as desired, and is not particularly limited. is more preferred.

The second laminate forming step is not particularly limited, and can be performed, for example, by the following steps. For example, the surface of the first wiring conductor 12 is roughened as an adhesion treatment for obtaining adhesion to the first insulating resin layer 13A. The first insulating resin layer 13A and the second metal layer 13B can be laminated by placing them in contact with one wiring conductor 12, applying heat and pressure, and peeling off the carrier. The roughening treatment is not particularly limited, and known means can be appropriately used, for example, means using a copper surface roughening liquid.

The metal foil with a carrier with a resin layer is obtained by, for example, laminating a resin layer on the metal foil side of the metal foil with a carrier, the resin layer being the first insulating resin layer 13A, and the metal foil being the second metal layer. 13B. A commercial product can also be used for the metal foil with a carrier with a resin layer, for example, CRS381NSI (product name) manufactured by Mitsubishi Gas Chemical Company, Inc. can be used. The heating and pressurizing conditions for the resin layer-attached carrier-attached metal foil are not particularly limited, and for example, vacuum pressing can be performed under conditions of a temperature of 220±2° C., a pressure of 3±0.2 MPa, and a holding time of 60 minutes.

<Second Wiring Forming Step>
Next, for example, as shown in FIG. 1(D), a non-through hole 14A reaching the first wiring conductor 12 is formed in the first insulating resin layer 13A, and the surface in which the non-through hole is formed is electrolyzed. At least one of plating and electroless plating is applied to form the second wiring conductors 14B (second wiring forming step). The thickness and pattern width of the second wiring conductor 14B are appropriately set as desired, and are not particularly limited.

The means for forming the non-through hole 14A is not particularly limited, and known means such as a laser such as a carbon dioxide laser or a drill can be used. Among them, it is preferable to form the non-through hole 14A with a laser. This is because it is suitable for fine processing. The non-through hole 14A is formed in the first insulating resin layer 13A via the second metal layer 13B, and electrically connects the second wiring conductor 14B and the first wiring conductor 12 formed in this process. provided to connect to The number and size of the non-through holes 14A can be appropriately selected as desired. After forming the non-through hole 14A, desmear treatment can be performed using an aqueous solution of sodium permanganate or the like.

After forming the non-through holes 14A, at least one of electrolytic plating and electroless plating is applied to form a plated film on the inner walls of the non-through holes 14A, and the first wiring conductors 12 and the second metal layers 13B are electrically connected. In addition, the thickness of the second metal layer 13B can be increased to form the second wiring conductor 14B. The method of applying electrolytic copper plating or electroless copper plating is not particularly limited, and known methods can be employed. Plating may be either electrolytic plating or electroless plating, but it is preferable to apply both electrolytic plating and electroless plating. Moreover, the plating is preferably copper plating, and it is preferable to apply at least one of electrolytic copper plating and electroless copper plating.

A method for forming the second wiring conductor 14B is not particularly limited, and for example, known means such as a subtractive method or a semi-additive method can be appropriately employed. In the case of the subtractive method, for example, first, the non-through holes 14A are formed, and at least one of electrolytic plating and electroless plating is applied to the surface on which the non-through holes are formed to reduce the thickness of the second metal layer 13B. Increase and level as needed. Next, for example, a dry film resist or the like is laminated, a negative mask is attached, a circuit pattern is printed, and an etching resist is formed by development. Subsequently, for example, the second metal layer 13B with an increased thickness is etched using an etching resist as a mask to form the second wiring conductors 14B, and the etching resist is removed.

In the case of the semi-additive method, for example, after forming the non-through holes 14A, the second metal layer 13B is completely removed by etching or the like to expose the first insulating resin layer 13A. Next, an electroless copper plating layer having a thickness of 0.4 μm to 2 μm, for example, is formed on the surface of the first insulating resin layer 13A by electroless copper plating. Subsequently, a resist layer is formed by thermocompression bonding of a dry film on the electroless copper plating layer, exposure and development are performed, and a resist pattern is formed by removing a portion for forming the second wiring conductor 14B. Exposure is carried out by, for example, irradiating a predetermined portion of the resist layer with an active energy ray, and the irradiation with the active energy ray may be performed through a mask pattern, or a direct writing method in which the active energy ray is directly applied may be used. After forming the resist pattern, scum (resist residue) is removed by, for example, plasma cleaning, and an electrolytic copper plating layer is formed on the surface of the electroless copper plating layer using the resist pattern as a plating resist. After providing the electrolytic copper plating layer, the resist pattern is removed using a resist stripping solution or the like, and the electroless copper plating layer is etched by flash etching or the like to form a second electroless copper plating layer and an electrolytic copper plating layer. to form a wiring conductor 14B.

<Wiring lamination process>
After the second wiring forming step, for example, as shown in FIG. The same steps as the body forming step and the second wiring conductor forming step are repeated n times to form a buildup structure having (n+2) layers of wiring conductors (wiring lamination step). n is an integer of 1 or more. The number n of repetitions is appropriately set as desired, and is not particularly limited, but can be, for example, 1 or more and 10 or less. Note that FIG. 2 shows a case where the number of repetitions n is three.

Specifically, in the wiring lamination step, for example, the (m+1)th insulating resin layer 15A and the (m+2)th insulating resin layer 15A are placed on the surface on which the (m+1)th wiring conductor of the (m+1)th laminate is provided. The (m+2)-th laminate forming step of forming the (m+2)-th laminate 15 by laminating the metal layers in this order, and the (m+1)-th laminate on the (m+1)-th insulating resin layer 15A The (m+2)th wiring that forms a non-through hole reaching the wiring conductor and applies at least one of electrolytic plating and electroless plating to the surface on which the non-through hole is formed to form the (m+2)th wiring conductor 15B. The forming process is repeated n times in this order to form the second to (n+1)th insulating resin layers 15A and the third to (n+2)th wiring conductors 15B. m is an integer of 1 or more, provided that m≦n.

<Solder Resist Layer Forming Step>
After the wiring lamination step, the (n+2)th wiring conductor 15B is formed on the (n+1)th insulating resin layer 15A and the (n+2)th wiring conductor 15B, as shown in FIG. A solder-resist layer 16A is formed so as to be partially exposed to form a solder-resist layer forming body 16 (solder-resist layer forming step). By forming the solder resist layer 16A before the subsequent core resin layer peeling step, at least when the core resin layer 11A is peeled off and in the first metal layer removing step after peeling, the first metal layer This is to reinforce the first wiring conductor 12 to the (n+2)th wiring conductor 15B and the first insulating resin layer 13A to the (n+1)th insulating resin layer 15A when removing the wiring conductor 11B.

A method for forming the solder resist layer 16A is not particularly limited, and known means can be appropriately adopted. For example, the solder resist layer 16A is formed by applying a solder resist on the (n+1)-th insulating resin layer 15A and the (n+2)-th wiring conductor 15B, that is, the (n+2)-th wiring conductor of the (n+2)-th laminate 15. It can be formed by coating the entire surface on which 15B is formed, curing by exposing through a negative film on which a circuit pattern is formed, and developing the uncured portion. Further, for example, the solder resist layer 16A is formed on the (n+1)-th insulating resin layer 15A and the (n+2)-th wiring conductor 15B, that is, the (n+2)-th wiring conductor 15B of the (n+1)-th laminate 15. It can be formed by pattern-printing a solder resist on the surface on which is formed by screen printing, and curing by irradiation with ultraviolet rays or by heating. That is, the solder-resist layer 16A is after the hardening treatment. Since the solder resist layer 16A is thus hardened, it is possible to prevent contamination of subsequent steps.

<Core resin layer peeling process>
After the solder resist layer forming step, for example, as shown in FIG. 2G, at least the core resin layer 11A is peeled off from the solder resist layer forming body 16 by peeling means for the first metal layer 11B. . As a result, the core resin layer 11A and, in some cases, a portion (eg, carrier) of the first metal layer 11B are peeled off by the peeling means (eg, peeling layer or release layer), leaving the remaining first metal layer. A core in which the first wiring conductor 12 to the (n+2)th wiring conductor 15B, the first insulating resin layer 13A to the (n+1)th insulating resin layer 15A, and the solder resist layer 16A are laminated on the 11B. It becomes the resin layer-removed body 17 (core resin layer peeling step). In the present embodiment, since the cured solder resist layer 16A is provided, sufficient strength can be obtained and damage is suppressed. At least part of the peeling means of the first metal layer 11B may be peeled together with at least the core resin layer 11A, or may remain without being peeled off. Either physical means or chemical means can be adopted as the means for peeling at least the core resin layer 11A in the peeling means. is preferred.

<First Metal Layer Removal Step>
After the core resin layer peeling step, for example, as shown in FIG. (first metal layer removing step). The means for removing the first metal layer 11B is not particularly limited, but it can be removed using, for example, a sulfuric acid-based or hydrogen peroxide-based etchant. The sulfuric acid-based or hydrogen peroxide-based etchant is not particularly limited, and those used in the industry can be used. In this embodiment, since the solder resist layer 16A is hardened, it is possible to reduce the damage caused by the chemical solution.

<Step of Forming Solder Resist Layer on Opposite Side>
After the first metal layer removing step, for example, as shown in FIG. The solder-resist layer 19 is formed so as to be exposed to the surface (opposite surface solder-resist layer forming step). The method of forming the solder resist layer 19 is the same as the solder resist layer forming step.

<Plating finishing process>
After the opposite surface solder resist layer forming step, for example, on both surfaces of the first metal layer removed body 18, the first wiring conductor 12 exposed from the solder resist layer 19 and the (n+2)th (n+2)th conductor exposed from the solder resist layer 16A are removed. ), a gold plating layer is formed on the wiring conductor 15B. Thus, a package substrate for mounting a semiconductor element is obtained.

As described above, according to the present embodiment, solder is applied onto the (n+1)th insulating resin layer 15A and the (n+2)th wiring conductor 15B so that the (n+2)th wiring conductor 15B is partially exposed. After the resist layer 16A is formed, at least the core resin layer 11A is peeled off by the peeling means. 13A to the (n+1)-th insulating resin layer 15A can be reinforced, and breakage thereof can be suppressed. Therefore, a package substrate for mounting a semiconductor element can be manufactured satisfactorily.

In addition, since the solder resist layer 16A is hardened, it is possible to prevent contamination of the subsequent steps and obtain sufficient strength and chemical resistance.

Furthermore, if the thickness of the first metal layer 11B from the end face of the first wiring conductor 12 side to the peeling means is 6 μm or more, further preferably 10 μm or more, and more preferably 15 μm or more, at least the core resin layer 11A can be peeled off. In this case, the first wiring conductor 12 to the (n+2)th wiring conductor 15B and the first insulating resin layer 13A to the (n+1)th insulating resin layer 15A can be further reinforced.

[Second embodiment]
A method of manufacturing a package substrate for mounting a semiconductor element according to the second embodiment of the present invention includes a supporting substrate laminating step between the solder resist layer forming step and the core resin layer peeling step of the first embodiment. , including a support substrate removal step after the first metal layer removal step. Other steps (first laminate preparation step, first wiring formation step, second laminate formation step, second wiring formation step, wiring lamination step, solder resist layer formation step, core resin layer peeling step , the first metal layer removing step, the opposite surface solder resist layer forming step, and the plating finishing step) are the same as those in the first embodiment.

4 and 5 show each step of the manufacturing method of the semiconductor element mounting package substrate according to the second embodiment. In this method of manufacturing a package substrate for mounting a semiconductor element, for example, as in the first embodiment, first, a first laminate preparation step, a first wiring formation step, a second laminate formation step, a second A wiring formation step, a wiring lamination step, and a solder resist layer formation step are performed.

<Support substrate lamination process>
After the solder-resist layer forming step, for example, as shown in FIG. 20 A of board|substrates are laminated|stacked and it is set as the support substrate laminated body 20 (support substrate lamination process). The support substrate 20A is applied with solder when at least the core resin layer 11A is peeled off in the subsequent core resin layer peeling step, and when the first metal layer 11B is removed in the first metal layer removing step after the peeling. Together with the resist layer 16A, the first wiring conductor 12 to the (n+2)th wiring conductor 15B and the first insulating resin layer 13A to the (n+1)th insulating resin layer 15A are reinforced. Also, the support substrate 20A is removed after at least the core resin layer 11A is peeled off, as will be described later.

The support substrate 16A may have, for example, a thermosetting resin layer in addition to the thermoplastic resin layer, or may be composed of only the thermoplastic resin layer. This is because thermoplastic resins have higher toughness than thermosetting resins and can provide high strength. The material of the thermoplastic resin layer is not particularly limited, but examples thereof include dry film resist. Among them, the thermoplastic resin layer is preferably composed of a photosensitive resin layer made of a photosensitive thermoplastic resin. This is because the process of forming wiring conductors can be used. Examples of photosensitive thermoplastic resins include dry film resists used for patterning. Further, the thermoplastic resin layer may be composed of, for example, a UV-releasable resin layer or a thermally-releasable resin layer, and consists of a photosensitive resin layer, a UV-releasable resin layer, and a thermally-releasable resin layer. It is preferable to configure to have at least one selected from the group.

The supporting substrate 20A can be laminated by, for example, placing a film-like or sheet-like supporting substrate 20A on the surface of the solder-resist layer forming body 16 on which the solder-resist layer 16A is provided, and laminating the layers. can. Further, when the thermoplastic resin layer is composed of a photosensitive resin layer, as the step of laminating the photosensitive resin layer, for example, a photosensitive layer is formed on the surface of the solder-resist layer forming body 16 on which the solder-resist layer 16A is provided. After arranging the photosensitive resin layer and laminating, the process of exposing and curing the entire surface of the photosensitive resin layer can be included. By exposing and curing the entire surface of the photosensitive resin layer, the adhesion to the (n+1)th insulating resin layer 15A and the (n+2)th wiring conductor 15B is increased. When the thermoplastic resin layer is composed of a UV-releasable resin layer or a thermally-releasable resin layer, the step of laminating the UV-releasable resin layer or the thermally-releasable resin layer may include, for example, the soldering of the solder resist layer forming body 16. A step of disposing a UV-releasable resin layer or a thermally-releasable resin layer on the surface provided with the resist layer 16A and performing lamination can be included. The thickness of the support substrate 16A is appropriately set as desired, and is not particularly limited.

<Core resin layer peeling step and first metal layer removing step>
After the support substrate lamination step, for example, as shown in FIG. 4G, in the same manner as in the first embodiment, a support substrate laminate 20, that is, a solder resist layer formed body 16 in which a support substrate 20A is laminated. Then, at least the core resin layer 11A is peeled off by the peeling means for the first metal layer 11B to obtain a core resin layer-removed body 17 (core resin layer peeling step). Subsequently, for example, as shown in FIG. 5H-1, in the same manner as in the first embodiment, the remaining first metal layer 11B is removed to form a first metal layer removed body 18. (First metal layer removal step).

<Support substrate removal step>
After the first metal layer removing step, the support substrate 20A is removed from the first metal layer removed body 18 to form a support substrate removed body 21 ( support substrate removal step). The means for removing the support substrate 20A is not particularly limited, and can be appropriately selected according to the material of the support substrate 20A. The support substrate 20A may be removed, for example, with a chemical solution such as an aqueous solution of sodium hydroxide, may be removed with a laser, or may be removed with a plasma treatment. In the case of (2), the layer may be removed by exfoliation by irradiating with light in the ultraviolet region, and in the case of a heat-peelable resin layer, it may be removed by exfoliation by heat treatment.

After the supporting substrate removing process, for example, the opposite surface solder resist layer forming process and the plating finishing process are performed in the same manner as in the first embodiment. Thus, a package substrate for mounting a semiconductor element is obtained.

As described above, according to the present embodiment, after the solder resist layer 16A is formed on the (n+1)th insulating resin layer 15A and the (n+2)th wiring conductor 15B, and the support substrate 20A is laminated, Since at least the core resin layer 11A is peeled off by the peeling means, the first wiring conductor 12 to the (n+2)th wiring conductor 15B, and the first insulating resin layer 13A to the (n+1)th insulating resin layer The layer 15A can be reinforced more strongly, and breakage thereof can be further suppressed.

The present embodiment will be specifically described below with reference to examples, but the present embodiment is not limited by these examples.

[Example 1]
A package substrate for mounting a semiconductor element was produced as follows.
<First laminate preparation step> (see FIG. 1(A))
A prepreg (thickness: 0.100 mm: manufactured by Mitsubishi Gas Chemical Company, Inc., product name: GHPL-830NS ST56) that is B-staged by impregnating a glass cloth (glass fiber) with a bismaleimide triazine resin (BT resin) is used as the core resin layer 11A. Then, on both sides of the core resin layer 11A, an ultra-thin copper foil with a carrier copper foil having a thickness of 18 μm as the first metal layer 11B (ultra-thin copper foil; thickness 5 μm: manufactured by Mitsui Kinzoku Mining Co., Ltd., product name: MT18SD-H -T5) is placed so that the carrier copper foil side is in contact with the core resin layer 11A, and vacuum pressing is performed under the conditions of a temperature of 220 ± 2 ° C., a pressure of 3 ± 0.2 MPa, and a holding time of 60 minutes to form the core resin layer. A first laminate 11 was produced in which the first metal layers 11B were provided on both surfaces of 11A.

<First Wiring Forming Step> (See FIG. 1B)
A dry film resist LDF515F (manufactured by Nikko Materials Co., Ltd., product name) having a thickness of 15 μm was laminated on the first laminate 11 under conditions of a temperature of 110±10° C. and a pressure of 0.50±0.02 MPa. After the circuit pattern was printed on the dry film resist using a parallel exposure machine, the dry film resist was developed using a 1% sodium carbonate aqueous solution to form a resist pattern for plating. Next, pattern electrolytic copper plating (electrolytic copper plating) of about 5 μm to 20 μm is applied on a copper sulfate plating line with a copper sulfate concentration of 60 g/L to 80 g/L and a sulfuric acid concentration of 150 g/L to 200 g/L, to form the first wiring. A conductor 12 was formed. After that, the dry film resist was peeled off using an amine-based resist stripper.

<Second Laminate Forming Step> (See FIG. 1(C))
In order to obtain adhesion to the insulating resin, the surface of the first wiring conductor 12 was roughened using a copper surface roughening liquid CZ-8101 (manufactured by MEC Co., Ltd., product name). Next, on both sides of the first laminate 11 on which the first wiring conductors 12 are formed, a copper foil with a resin layer and an ultra-thin copper foil with a carrier copper foil having a thickness of 18 μm (ultra-thin copper foil (metal layer); Thickness 2 μm, resin layer thickness 0.015 mm: manufactured by Mitsubishi Gas Chemical Co., Ltd., product name: CRS381NSI) was placed so that the resin layer was in contact with the first wiring conductor 12, and the pressure was 3 ± 0.2 MPa and the temperature was 220 ± Vacuum pressing was performed under conditions of 2° C. and holding time of 60 minutes. Thereafter, the carrier copper foil having a thickness of 18 μm is peeled off, and a second laminate 13 is formed by laminating a first insulating resin layer 13A and a second metal layer 13B having a thickness of 2 μm on the first wiring conductor 12. Obtained.

<Second Wiring Forming Step> (See FIG. 1(D))
On both sides of the second laminate 13, using a carbon dioxide laser processing machine ML605GTWIII-5200U (manufactured by Mitsubishi Electric Corporation, product name), beam irradiation diameter Φ 0.06 mm, frequency 500 Hz, pulse width 15 μs, irradiation number 1 shot The non-through holes 14A reaching the first wiring conductors 12 were formed in the first insulating resin layer 13A through the second metal layer 13B.

Next, the second laminate 13 in which the non-through holes 14A are formed is subjected to desmear treatment using an aqueous solution of sodium permanganate at a temperature of 80±5° C. and a concentration of 55±10 g/L. After performing plating with a thickness of 0.4 μm to 0.8 μm by plating, plating with a thickness of 5 μm to 20 μm was performed by electrolytic copper plating. Thereby, the inner wall of the non-through hole 14A is connected by plating, the first wiring conductor 12 and the second metal layer 13B are electrically connected by plating the inner wall of the non-through hole 14, and the second metal layer 13B is electrically connected by plating. The thickness of the metal layer 13B is increased.

Next, the surface of the second metal layer 13B is smoothed, and a dry film resist LDF515F (manufactured by Nikko Materials Co., Ltd., product name) is applied under the conditions of a temperature of 110±10° C. and a pressure of 0.50±0.02 MPa. Laminated. After that, a negative mask was attached, a circuit pattern was printed using a parallel exposure machine, and an etching resist was formed by developing the dry film resist using a 1% sodium carbonate aqueous solution. Then, the portion of the second metal layer 13B without the etching resist was removed by etching with an aqueous solution of ferric chloride, and then the dry film resist was removed with an aqueous solution of sodium hydroxide to form the second wiring conductor 14B.

<Wiring Lamination Process> (See FIG. 2(E))
The same steps as the second laminate forming step and the second wiring conductor forming step were repeated three times to form a fifth laminate 15 having a buildup structure having five layers of wiring conductors.

<Solder Resist Layer Forming Step> (See FIG. 2(F))
After the wiring lamination step, a solder resist layer 16A having a thickness of 10 μm is formed on the fourth insulating resin layer 15A and the fifth wiring conductors 15B so that the fifth wiring conductors 15B are partially exposed. A resist layer-forming body 16 was obtained.

<Core Resin Layer Peeling Step> (See FIG. 2(G))
After obtaining the solder-resist layer-formed body 16, a physical force is applied to the boundary between the ultra-thin copper foil of the first metal layer 11B and the carrier copper foil to remove at least the core resin layer 11A from the solder-resist layer-formed body 16. was peeled off and removed. As a result, a set of core resin layer-removed bodies 17 was obtained.

<First Metal Layer Removal Step> (See FIG. 3(H))
After obtaining the core resin layer-removed body 17, the remaining first metal layer 11B (ultrathin copper foil) is removed using a perhydrate sulfuric acid-based soft etchant, and the first metal layer-removed body 18 is obtained. Obtained.

<Solder Resist Layer Forming Step> (See FIG. 3(I))
After obtaining the first metal layer-removed body 18, a solder resist having a thickness of 10 μm is applied on the first insulating resin layer 13A and the first wiring conductors 12 so that the first wiring conductors 12 are partially exposed. A layer 19 was formed.

<Plating finishing process>
After forming the solder resist layer 19, a gold plating layer is formed on the first wiring conductor 12 or the fifth wiring conductor 15B exposed from the solder resist

layers

16A and 19 to obtain a package substrate for mounting a semiconductor element. rice field. According to this embodiment, no damage was found in the first wiring conductor 12 to the fifth wiring conductor 15B and in the first insulating resin layer 13A to the fourth insulating resin layer 15A, and the package for mounting a semiconductor element was not damaged. A good substrate could be manufactured.

[Example 2]
In the same manner as in Example 1, the first laminate preparation step (see FIG. 1(A)), the first wiring formation step (see FIG. 1(B)), and the second laminate formation step (see FIG. 1 ( C)), a second wiring forming step (see FIG. 1(D)), a wiring lamination step (see FIG. 2(E)), and a solder resist layer forming step (see FIG. 2(F)). . Next, on the surface on which the solder resist layer 16A is provided, a photosensitive resin layer (thermoplastic resin layer) is formed as the support substrate 20A under the conditions of a temperature of 110 ± 10 ° C. and a pressure of 0.50 ± 0.02 MPa. A dry film resist LDF515F (manufactured by Nikko Materials Co., Ltd., product name) having a thickness of 15 μm was laminated. After that, the entire surface was exposed using a parallel exposure machine and cured to obtain a laminate 20 with a supporting substrate in which the supporting substrate 20A was laminated (supporting substrate laminating step; see FIG. 4F-1).

After obtaining the support substrate-equipped laminate 20, in the same manner as in Example 1, the core resin layer peeling step (see FIG. 4(G)) and the first metal layer removing step (see FIG. 5(H)). did Next, the dry film resist, which is the support substrate 20A, was removed using an aqueous sodium hydroxide solution (support substrate removal step; see FIG. 5(I)). Thereafter, a plating finishing process was performed in the same manner as in Example 1 to obtain a package substrate for mounting a semiconductor element. Also in this example, no damage was observed in the first wiring conductor 12 to the fifth wiring conductor 15B and in the first insulating resin layer 13A to the fourth insulating resin layer 15A. was successfully manufactured.

[Comparative Example 1]
In the same manner as in Example 1, after performing the first laminate preparation step, the first wiring formation step, the second laminate formation step, the second wiring formation step, and the wiring lamination step, the first A physical force was applied to the boundary between the ultra-thin copper foil of the metal layer and the carrier copper foil to peel and remove at least the core resin layer from the fifth laminate, thereby obtaining a set of laminates. That is, in Comparative Example 1, in Example 1, the core resin layer peeling process was performed without performing the solder resist layer forming process. After peeling off the core resin layer, an attempt was made to remove the ultra-thin copper foil using a perhydrate sulfuric acid-based soft etchant, but the laminate was damaged.

That is, according to Examples 1 and 2, it was found that the solder-resist layer 16A can be reinforced and damage can be suppressed when the core resin layer 11A is peeled off and in the processing steps after the peeling. rice field.

It can be used to manufacture package substrates for mounting semiconductor devices.

REFERENCE SIGNS LIST 11 First laminate 11A Core resin layer 11B First metal layer 12 First wiring conductor 13 Second laminate 13A First insulating resin layer 13B Second 2 metal layers, 14A... non-through hole, 14B... second wiring conductor, 15... (m+2)th laminate, 15A... (m+1)th insulating resin layer, 15B... (m+2)th wiring conductor, DESCRIPTION OF SYMBOLS 16... Solder-resist layer formation body, 16A... Solder-resist layer, 17... Core resin layer removal body, 18... First metal layer removal body, 19... Solder-resist layer, 20... Support substrate laminate, 20A... Support substrate, 21 ... support substrate removed body

Claims

a first laminated body preparing step of preparing a first laminated body having a core resin layer and a first metal layer provided on at least one side of the core resin layer and provided with a peeling means;
a first wiring forming step of applying at least one of electrolytic plating and electroless plating on the first metal layer to form a first wiring conductor;
A second laminate is formed by laminating a first insulating resin layer and a second metal layer in this order on the surface of the first laminate on which the first wiring conductor is provided. A second laminate forming step to
A non-through hole reaching the first wiring conductor is formed in the first insulating resin layer, and at least one of electrolytic plating and electroless plating is applied to the surface in which the non-through hole is formed to form a second wiring. a second wiring forming step of forming a conductor;
After the second wiring forming step, the (m+1)-th insulating resin layer and the (m+2)-th insulating resin layer are further formed on the surface on which the (m+1)-th wiring conductor of the (m+1)-th laminate is provided. and a metal layer in this order to form an (m+2)-th laminate, and the (m+1)-th wiring on the (m+1)-th insulating resin layer. (m+2)th wiring formation of forming a non-through hole reaching a conductor and applying at least one of electrolytic plating and electroless plating to the surface in which the non-through hole is formed to form a (m+2)th wiring conductor The steps are repeated n times in this order, and a wiring lamination step (m and n are an integer of 1 or more, provided that m ≤ n);
forming a solder-resist layer on the (n+1)-th insulating resin layer and the (n+2)-th wiring conductor so that the (n+2)-th wiring conductor is partially exposed; a solder resist layer forming step;
a core resin layer stripping step of stripping at least the core resin layer from the solder resist formed body by the stripping means to obtain a core resin layer-removed body;
A method of manufacturing a package substrate for mounting a semiconductor device, comprising:
The method of manufacturing a package substrate for mounting a semiconductor element according to claim 1, wherein the core resin layer has a thickness of 1 µm or more.
The method for manufacturing a package substrate for mounting a semiconductor element according to claim 1, wherein the thickness of the first metal layer is 100 µm or less.
2. The method for manufacturing a package substrate for mounting a semiconductor element according to claim 1, wherein the thickness of said first metal layer from the end face of said first wiring conductor side to said peeling means is 6 μm or more.
The method for manufacturing a package substrate for mounting a semiconductor element according to claim 1, wherein the thickness of the first laminate is 20 µm or more and 1000 µm or less.
The method of manufacturing a package substrate for mounting a semiconductor element according to claim 1, wherein each of the first to (n+1)th insulating resin layers has a thickness of 0.1 µm or more and 100 µm or less.
After the solder-resist layer forming step and before the core resin layer peeling step, a supporting substrate having a thermoplastic resin layer is laminated on the surface of the solder-resist layer forming body provided with the solder-resist layer. 2. The method of manufacturing a package substrate for mounting a semiconductor element according to claim 1, further comprising a step of laminating a support substrate.