TW202333366A - Image sensor and method of manufacturing such a sensor - Google Patents

Abstract

The present description concerns an image sensor comprising a support substrate and an array (101) of pixels (PIX) formed on the support substrate, the pixels of the array being regularly arranged, with a constant pitch, in rows and column, each pixel (PIX) comprising at least one photodiode and one transfer transistor, wherein: A) each row of pixels is divided into first and second adjacent row portions; and/or B) each column of pixels is divided into first and second adjacent column portions.

Description

Image sensor and method of manufacturing the same

This disclosure generally relates to the field of electronic equipment. More specifically, the present disclosure is directed to an image sensor, such as one intended to be integrated into an electronic device or fingerprint sensor configured to acquire fingerprints, or configured for facial identification or identification, facial recognition, etc. Image sensors in sensors for tracking and/or gesture recognition. A further object of the present disclosure is a method of manufacturing the image sensor.

Various applications may utilize image sensors. This sensor can be integrated into a mobile phone, a touch pad, a connected watch or a bracelet, for example.

The purpose of the embodiments is to overcome all or part of the shortcomings of known image sensors and manufacturing methods thereof. More specifically, embodiments aim to reduce image acquisition time and obtain large-sized image sensors.

To this end, embodiments provide an image sensor, which includes a support substrate and a pixel array formed on the support substrate. The pixels of the array are regularly arranged in rows and columns with a constant pitch, and each pixel includes at least one photodiode. and a transfer transistor, where: A) Each row of pixels is divided into a first adjacent row portion and a second adjacent row portion, a first conductive row track interconnecting first terminals of the transistors of the pixels of the first row portion, and a second conductive row track interconnecting electrically insulating a first conductive row track connected to a first terminal of a transistor of a second row portion of pixels; and/or B) Each pixel column is divided into a first adjacent column portion and a second adjacent column portion, the first conductive column track interconnecting the second terminals of the transistors of the pixels of the first column portion, and the second conductive column track with The first conductive column tracks interconnecting second terminals of the transistors of the pixels of the second column portion are electrically insulating.

According to an embodiment, in option A), the pixels of the first row part define a first area and the pixels of the second row part define a second area, the pixels of the first area being connected to the same first readout circuit of the sensor and The same first control circuit of the sensor, and the pixels of the second area are connected to the same second readout circuit of the sensor and the same second control circuit of the sensor.

According to an embodiment, each of the first and second areas includes a number of pixels approximately equal to half the total number of pixels of the array.

According to an embodiment, in options A) and B), the pixels in the first row part and the first column part define a first area, the pixels in the second row part and the first column part define a second area, the first row part and The pixels of the second column portion define a third region, and the pixels of the second row portion and the second column portion define a fourth region, the pixels of the first region being connected to the same first readout circuit of the sensor and to the sensing The same first control circuit of the sensor, the pixels of the second area are connected to the same second readout circuit of the sensor and connected to the same second control circuit of the sensor, the pixels of the third area are connected to the same A third readout circuit is connected to the same third control circuit of the sensor, and the pixels of the fourth area are connected to the same fourth readout circuit of the sensor and to the same fourth control circuit of the sensor.

According to an embodiment, each of the first, second, third and fourth regions includes a number of pixels approximately equal to one quarter of the total number of pixels in the array.

According to an embodiment, the first terminal of the transfer transistor is the gate terminal and the second terminal of the transfer transistor is the source or drain terminal.

According to an embodiment, the photodiodes of the pixels are organic photodiodes.

According to an embodiment, the transmission transistor of the pixel is a TFT transistor.

Embodiments provide fingerprint sensors including image sensors such as those described.

The embodiment provides an image sensor manufacturing method, which includes the following steps: a) forming an array of pixels regularly arranged in rows and columns at constant intervals, each pixel including at least one photodiode and one transmission transistor; and b) - For each row of pixels, forming a conductive row track interconnecting the first terminals of the transistors of the pixels in the row, and then regionally etching said conductive row track to separate it into a first conductive row track and to separate it into the first conductive row track a second conductive row track electrically insulated from the conductive row track; and/or - For each pixel column, forming a conductive column track interconnecting the second terminals of the transistors of the pixels in the column, and then regionally etching said conductive column track to separate it into a first conductive column track and to separate it into the first conductive column track The conductive column track electrically insulates the second conductive column track.

Similar features are identified by similar element symbols in the different drawings. In particular, the same structural and/or functional features may have the same reference numerals and may be configured with the same structural, dimensional, and material properties in various embodiments.

For purposes of clarity, only the steps and elements that are useful in understanding the embodiments described herein are shown and described in detail. In particular, the various applications of the described image sensor have not been described in detail, and the described embodiments are compatible with all or most of the applications in which it is possible to utilize image sensors, in particular image sensor integration Applications in fingerprint sensors and/or in facial identification or recognition, facial tracking and/or gesture recognition sensors.

Unless otherwise stated, when reference is made to two elements connected together, this means a direct connection without any intervening elements other than conductors, and when reference is made to two elements coupled together, this means both Elements may be connected or they may be coupled via one or more other elements.

In the following disclosures, unless otherwise stated, when referring to absolute position qualifiers, such as the terms "front", "back", "upper", "lower", "left", "right", etc., or relative positions When defining terms such as "above", "below", "upper", "lower", etc., or orientation qualifiers such as "horizontal", "vertical", etc., reference is made to the orientation shown in the figure.

Unless otherwise stated, the expressions "about", "approximately", "substantially" and "approximately" mean within 10%, and preferably within 5%.

Figure 1 schematically and partially shows an image sensor according to an embodiment. Image sensor 100 is intended, for example, to be integrated into a fingerprint sensor (not shown in Figure 1).

In the example shown, image sensor 100 includes a plurality of pixels PIX. In this example, the pixels PIX are arranged in an array 101 consisting of rows and columns. The rows are, for example, substantially perpendicular to the columns. Each row of pixels PIX of array 101 corresponds, for example, to a horizontal row of adjacent pixels PIX in the orientation of Figure 1 . Each column of pixels PIX of array 101 corresponds, for example, to a vertical row of adjacent pixels PIX in the orientation of Figure 1 . The pixels PIX of the array 101 of the image sensor 100 all have a substantially square shape, for example. The pixels PIX of the array 101 of the image sensor 100 , for example, all have the same lateral dimensions so as to be within manufacturing dispersion. Array 101 has a constant spacing, for example, along the rows of pixels PIX and along the columns of pixels PIX, to within manufacturing dispersion. As an example, array 101 includes at least one thousand rows of pixels PIX (eg, at least two thousand rows of pixels PIX), and at least one thousand columns of pixels PIX.

In the example shown in Figure 1, array 101 includes a first group 101A of adjacent pixels (region 1) and a second group 101B (region 2) of adjacent pixels PIX that are different from the first group 101A of pixels PIX . More precisely, in this example, the first group 101A of pixels PIX includes components of a contiguous column of pixels PIX of array 101 , and the second group 101B of pixels PIX includes another component of a contiguous column of pixels PIX of array 101 . Furthermore, the second group 101B of pixels PIX is adjacent to the first group 101A of pixels PIX, and the column of pixels PIX without array 101 is located between the first group 101A and the second group 101B of pixels PIX. As an example, the first group 101A of pixels PIX corresponds to the columns of pixels PIX in one half of array 101 (the left half in the orientation of Figure 1), and the second group 101B of pixels PIX corresponds to the other half of array 101 In the column of pixels PIX (the right half in the orientation of FIG. 1 ), groups 101A and 101B have substantially the same number of pixels PIX. Each group 101A, 101B of pixels PIX includes, for example, approximately six hundred consecutive columns of pixels PIX of array 101 .

In the example shown, the pixels PIX of the first group 101A are connected to the first readout circuit 103A (ROIC 1) of the image sensor 100 and the pixels PIX of the second group 101B are connected to the image sensor 100 . Second readout circuit 103B (ROIC 2). More precisely, as described in further detail in conjunction with FIGS. 3 to 5 , the pixels PIX of the same column of the first group 101A are, for example, interconnected and connected to the first readout circuit 103A, and the pixels of the same column of the second group 101B The PIX is interconnected and connected to the second readout circuit 103B, for example.

In the example shown in Figure 1, the readout circuits 103A and 103B are connected to the same control unit 105 (UC), such as a microcontroller. Control unit 105 is configured, for example, to control readout circuits 103A and 103B and analyze data originating from pixels PIX of array 101 .

Furthermore, in the example shown, the pixels PIX of the first group 101A are connected to the first control circuit 107A (GOA 1) of the image sensor 100 and the pixels PIX of the second group 101B are connected to the image sensor 100 The second control circuit 107B (GOA 2). In this example, each row of pixels PIX of the array is split into a first row portion and a second row portion, such that its pixels form part of the first group 101A and part of the second group 101B, respectively. More precisely, as will be described later in conjunction with FIGS. 3 and 5 , the pixels PIX of the first group 101A forming part of the same first row portion are, for example, interconnected and connected to the first control circuit 107A, and form the same second row. The pixels PIX of the second group 101B of a part of the row portion are, for example, interconnected and connected to the second control circuit 107B.

An example of an image sensor 100 has been shown in Figure 1 in which each group 101A, 101B of pixels PIX of the array 101 is coupled to a single control circuit 107A, 107B and to a single readout circuit 103A, 103B. As an example, circuits 107A, 107B, 103A, and 103B are respectively integrated on different integrated circuit chips. As an example, each control circuit 107A, 107B is integrated into a single integrated circuit die, and each readout circuit 103A, 103B is integrated into a single integrated circuit die. However, this example is non-limiting. As a variant, each control circuit 107A, 107B may be divided into, for example, a plurality of identical or similar control sub-circuits coupled accordingly to different sub-components of the portion of the row of pixels PIX, and/or each readout circuit 103A, 107B. 103B may be divided into, for example, a plurality of identical or similar readout sub-circuits, which are coupled to different sub-components of the columns of pixels PIX accordingly. Each readout circuit 103A, 103B may, for example, be divided into a plurality of interconnected readout sub-circuits, each readout subcircuit being connected to a sub-section of a consecutive column of pixels PIX of the group 101A, 101B to which the readout circuit 103A, 103B is connected. components. As an example, different control sub-circuits are integrated in different integrated circuit dies, and different readout sub-circuits are integrated in different integrated circuit dies.

An advantage of the image sensor 100 described above in connection with Figure 1 lies in the fact that, for example, the difference between a target whose image is desired to be captured (eg, a user's finger) and a group of pixels in groups 101A, 101B Groups 101A, 101B of pixels PIX of array 101 may be controlled individually, with at least a portion of them vertically aligned without being vertically aligned with pixels of another group 101B, 101A. This allows for acquisition of images by using only one part of the sensor (e.g., the pixels PIX of the first group 101A) without using another part of the sensor (in this example, the pixels PIX of the second group 101B). Like case time gain. In particular, this enables the time for transmitting images to the control unit 105 to be reduced. This further allows for lower energy consumption.

Figure 2 shows schematically and partially another image sensor 200 according to an embodiment. The image sensor 200 is intended to be integrated into a fingerprint sensor (not shown in Figure 2), for example. The image sensor 200 of FIG. 2 includes common components with the image sensor 100 of FIG. 1 . These common elements will not be described in detail below.

The main difference between the image sensor 200 in FIG. 2 and the image sensor 100 in FIG. 1 is that the array 101 of pixels PIX of the image sensor 200 includes a first group 201A (region 201A) of adjacent pixels PIX. 1), the second group 201B (area 2), the third group 201C (area 3) and the fourth group 201D (area 4). In the example shown in Figure 2, each group 201A, 201B, 201C, 201D of pixels PIX is different from the other groups 201A, 201B, 201C, 201D of pixels PIX. As an example, each group of pixels PIX 201A, 201B, 201C, 201D corresponds to a quarter of the array 101 (upper left, upper right, lower left and lower right respectively in the orientation of Figure 2). In the example shown, each row of pixels PIX of array 101 is split into a first row portion such that its pixels PIX form part of a first group 201A or a third group 201C, respectively, and a second row portion, Its pixels PIX form part of the second group 201B or part of the fourth group 201D, respectively. Furthermore, each column of pixels PIX is split into a first column part such that its pixels PIX form part of the first group 201A or part of the second group 201B, respectively, and a second column part such that its pixels PIX accordingly form Part of the third group 201C or part of the fourth group 201D.

In the example shown, the first group 201A, the second group 201B, the third group 201C and the fourth group 201D of pixels PIX are respectively connected to the first readout circuit 203A (ROIC 1), the second readout circuit 203B ( ROIC 2), the third readout circuit 203C (ROIC 3) and the fourth readout circuit 203D (ROIC 4). More precisely, as will be described in detail later in conjunction with Figures 4 and 6: - the pixels PIX of the first group 201A forming part of the same first column part are for example interconnected and connected to the first readout circuit 203A; - the pixels PIX of the second group 201B forming part of the same first column part are for example interconnected and connected to the second readout circuit 203B; - the pixels PIX of the third group 201C forming part of the same second column part are for example interconnected and connected to the third readout circuit 203C; and - the pixels PIX of the fourth group 201D forming part of the same second column part are for example interconnected and connected to the fourth readout circuit 203D;

In the example shown in Figure 2, the readout circuits 203A, 203B, 203C and 203D are connected to the control unit 105 (UC).

Furthermore, in the example shown, the first group 201A, the second group 201B, the third group 201C and the fourth group 201D of the pixels PIX are connected to the first control circuit 207A (GOA 1), the second control circuit 207B (GOA 1), respectively. GOA 2), the third control circuit 207C (GOA 3) and the fourth control circuit 207D (GOA 4). More precisely, as will be described in detail later in conjunction with Figures 4 and 6: - the pixels PIX of the first group 201A forming part of the same row portion are for example interconnected and connected to the first control circuit 207A; - the pixels PIX of the second group 201B forming part of the same second row section are for example interconnected and connected to the second control circuit 207B; - the pixels PIX of the third group 201C forming part of the same first row section are for example interconnected and connected to the third control circuit 207C; and - The pixels PIX of the fourth group 201D forming part of the same second row section are for example interconnected and connected to the fourth control circuit 207D.

An example of an image sensor 200 has been shown in Figure 2, in which each group 201A, 201B, 201C, 201D of pixels PIX of the array 101 is coupled to a single control circuit 207A, 207B, 207C, 207D, and is coupled to Individual readout circuits 203A, 203B, 203C, 203D. As an example, circuits 207A, 207B, 207C, 207D, 203A, 203B, 203C and 203D are respectively integrated in different integrated circuit chips. As an example, each control circuit 207A, 207B, 207C, 207D is integrated into a single integrated circuit die, and each readout circuit 203A, 203B, 203C, 203D is integrated into a single integrated circuit die. However, this example is non-limiting. As a variant, each control circuit 207A, 207B, 207C, 207D can be divided into a plurality of control sub-circuits, and/or each readout circuit 203A, 203B, 203C, 203D can be divided into a plurality of readout sub-circuits, for example similar to the previous The control circuits 107A and 107B and the readout circuits 103A and 103B of the image sensor 100 are described with reference to FIG. 1 .

The image sensor 200 of FIG. 2 has advantages similar to those of the image sensor 100 of FIG. 1 . Since there are four groups of pixels 201A, 201B, 201C and 201D, each group is coupled to the readout circuits 203A, 203B, 203C, 203D and the control circuits 207A, 207B, 207C, 207D, so that the image sensor 200 can be advantageous Benefit from four image acquisition areas that can be controlled independently of each other.

FIG. 3 is an electrical diagram illustrating an example of the embodiment of the image sensor 100 of FIG. 1 .

In the example shown in Figure 1, each pixel PIX of array 101 includes a photodetector 303, such as a photodiode or photodiode, having an anode connected to node 305 applying bias potential VBIAS and a cathode connected to node 307 that stores the charge photogenerated by photodetector 303 . In this example, each pixel PIX of array 101 has a "1T" architecture. More precisely, each pixel PIX includes a pass transistor 309, such as a field effect transistor, having a conductive terminal (eg, drain) connected to node 307 and having another conductive terminal (eg, drain) connected to charge collection node 311 , source). In the example shown, nodes 305 of pixels PIX that form part of the same column of array 101 are interconnected by conductive tracks 313 taken to bias potential VBIAS. Furthermore, in this example, nodes 311 of pixels PIX that form part of the same column of array 101 are interconnected by conductive tracks 315 .

As an example, the photodetector 303 is an organic photodetector, that is, a photodetector including at least one light conversion layer or active layer made of at least one organic material. The transmission transistor 309 is, for example, a thin-film transistor (TFT). The photodetector 303 and the transistor 309 are formed, for example, on the same support substrate, with the interconnection network of the pixel PIX further formed thereon.

The control circuit 107A of the first group 101A of pixels PIX and the control circuit 107B of the second group 101B of pixels PIX are, for example, a "gate-on-array" (GOA) type. In this example, for each first portion of the row of pixels PIX to which first control circuit 107A is connected, the first control circuit includes a switch 321A connected to the pass transistor 309 interconnecting the first row portion of pixels PIX The conductive track of the control terminal (gate) 323A. Similarly, for each second portion of the row of pixels PIX to which second control circuit 107B is connected, the second control circuit includes a switch 321B connected to the pass transistor 309 interconnecting the pixels PIX of the second row portion. Conductive track 323B for control terminal (gate). Conductive track 323A is electrically insulated from conductive track 323B.

In the example shown, each switch 321A, 321B is, for example, of the single-pole double-throw (SPDT) type, and more precisely includes an input terminal IN connected to a conductive track 323A, an input terminal IN connected to an applied potential VON The first output terminal OUT1 of the node 325 is at a high potential (eg, a high potential), and the second output terminal OUT2 is connected to a node 327 at an applied potential VOFF (eg, a low potential, such as ground). More precisely, the values of the potentials VON and VOFF are selected accordingly, for example, so that when the input terminal IN of the switches 312A, 312B of the row section is connected to the first output terminal OUT1, the transistor 309 of the pixel PIX of the same row section is in The on state is taken as the potential VON, and when the input terminal IN of the switches 321A and 321B in the row part is connected to the second output terminal OUT2, the transistor 309 of the pixel PIX in the same row part is in the off state, and is taken as the potential VOFF.

In the example shown in FIG. 3 , for each column of pixels PIX of the first group 101A of the array 101 , the first readout circuit 103A of the image sensor 100 includes photogenerated charges (eg, from the pixels in that column). PIX photodetector 303 photogenerated electrons) integrated circuit 329A. Similarly, for each column of pixels PIX of second group 101B of array 101 , second readout circuit 103B of image sensor 100 includes photogenerated charges (e.g., photogenerated by photodetectors 303 of pixels PIX in that column). electronic) integrated circuit 329B. In the example shown, each circuit 329A is connected to a conductive track 315 interconnecting the conductive terminals 311 of a corresponding column of pixels PIX of the first group 101A, and each circuit 329B is connected to a conductive track 315 interconnecting a corresponding column of the second group 101B. Conductive track 315 of conductive terminal 311 of pixel PIX.

The operational steps of the image sensor 100 in the case where it is desired to capture an image by using only the pixels PIX of the first group 101A of the array 101 of the image sensor 100 will now be described with reference to FIG. 3 .

During the first exposure step, charge photogenerated by photodetectors 303 of pixels PIX of array 1201 accumulates at storage node 307 . The first exposure step corresponds, for example, to the situation where the photodetector 303 of the pixel PIX of the array 101 is exposed to light but it is not desired to capture an image. During the first exposure step, the switch 321A of the control circuit 107A and the switch 321B of the control circuit 107B connect their input terminal IN to their second output terminal OUT2, so that the potential VOFF is applied via the conductive tracks 323A, 323B accordingly. to the gates of the transistors 309 of the first group 101A and the second group 101B of the pixels PIX, so that the transistors 309 are in an off state.

During the reset step after the first exposure step, the photogenerated charges previously accumulated at the storage node 307 during the first exposure step are discharged through the integrated circuit 329A of the readout circuit 103A.

To this end, during the reset step, the switches 321A of the control circuit 107A are controlled one by one in order to connect their input terminal IN to their first output terminal OUT1, thus applying the potential VON to the third output terminal OUT1 via the conductive track 323A. The gates of the transmission transistors 309 in the same first row part of a group of 101A pixels PIX keep the transistors 309 in a conductive state. Accordingly, photogenerated charges previously accumulated at storage nodes 307 of pixels PIX in different first row portions of the first group 101A of pixels PIX of array 101 are continuously (eg, row-by-row portions) transferred to the readout circuit 103A. Integrated circuit 329A.

More precisely, the switch 321A connected to the conductive track 323A of one of the first row portions of the pixels PIX of the array 101 (eg, the first portion of the upper row in the orientation of FIG. 3 ) is first controlled, for example, to change the potential VON is applied to the gate of the pass transistor 309 of this first row portion. This results in the transfer or draining of photogenerated charges from the storage nodes 307 of the pixels PIX of the first row portion to the integrated circuits 329A, each node 307 being coupled to one of the circuits 329A of the first readout circuit 103A during this operation. The photogenerated charges originating from the pixels PIX in the first row portion are then discharged through the output of circuit 329A. Once the charge has been discharged, the switch 321A connected to the first row portion of the pixel PIX whose charge has just been transferred is controlled to apply the potential VOFF to the gate of the transfer transistor 309 of this row to transfer the charge from the integrated circuit 329A This first row portion of pixels PIX is isolated from storage node 307 . The above operation is then repeated for another first row of pixels PIX (eg, a first row portion adjacent to the first row portion whose charge has just been transferred). Thus, all of the first row portion of the first group 101A of pixels PIX of the array 101 is scanned sequentially (eg, from top to bottom in the orientation of FIG. 3 ).

As an example, the resetting step begins when at least one finger is placed on the image sensor 100 in vertical alignment with the first group 101A of pixels PIX of the array 101 .

During the second exposure step, the charge photogenerated by the photodetectors 303 of the pixels PIX of the first group 101A of the array 101 is again accumulated at the storage node 307 . In contrast to the previously described first exposure step, the second exposure step corresponds, for example, to the situation where the photodetector 303 of the pixel PIX of the array 101 is exposed to light and it is desired to capture an image. The second exposure step has, for example, a determined duration adjusted to the ambient brightness, called integration time. For each row section of pixels PIX, the second exposure step begins when, after reset, the transfer transistors of the row section are turned off (blocked).

The method of controlling the image sensor 100 further includes an acquisition step after the second exposure step. In contrast to the reset step in which the photo-generated charge accumulated at the storage node 307 of the pixels PIX of the array 101 is discharged without integration, during the acquisition step, an adjustment of the pixels originating from the first row portion of the first group 101A of the array 101 is provided. The photogenerated charges of PIX are integrated.

During the acquisition step, the switch 321A of the first control circuit 107A is sequentially controlled row-by-row section to transfer the photogenerated charges previously accumulated at the storage node 307 of the pixel PIX of the different first row sections of the first group 101A of the array 101 transmitted to the integration circuit 329A of the first readout circuit 103A. Control of the switch 321 is, for example, similar to what was previously discussed above in connection with the reset step.

Although the situation where it is desired to capture an image by using only the pixels PIX of the first group 101A of the array 101 of the image sensor 100 has been described above with reference to FIG. 3 , those skilled in the art can certainly convert the above steps. It is desirable to capture an image only by using the second group 101B of pixels PIX based on instructions of the present disclosure.

As an example, each integrated circuit 329A, 329B includes an operational amplifier (not shown in Figure 3) having an inverting input connected to an input terminal (connected to conductive track 315) and having an applied reference potential ( For example, a non-inverting input terminal of a node that is grounded) and has an output terminal connected to the output terminals of circuits 329A, 329B. In this example, each circuit 329A, 329B further includes capacitive elements (eg, capacitors) and switches, not detailed in FIG. 3 . The capacitive element and the switch are connected in parallel between the input terminals and the output terminals of the circuits 329A and 329B, for example.

In the example of using only the first group 101A of pixels PIX to acquire an image, the charge photogenerated by the photodetector 303 of the pixels PIX is passed through the transistor 309 and connected to the input of the integrated circuit 329A during the reset step. Conductive tracks 315 of terminals are transmitted from storage node 307 to readout circuit 103A. When the switch of the circuit 329A is in the on state, the photogenerated charges will not accumulate at the terminals of the capacitive element, but will be discharged directly through the output terminal of the circuit 329A. In contrast, during the acquisition step, the switch of circuit 329A is in the off state and photogenerated charge accumulates at the terminals of the capacitive element. Therefore, the operational amplifier delivers a signal at its output that is a function of the amount of photogenerated charge accumulated at the terminals of the capacitive element. This signal is then transmitted, for example, to one or more other circuits of the image sensor 100, such as to a correlated double sampling (CDS) and an analog-to-digital converter (ADC). circuit.

FIG. 4 is an electrical diagram illustrating an example of the embodiment of the image sensor 200 of FIG. 2 . The example embodiment of image sensor 200 of FIG. 4 includes elements in common with the example embodiment of image sensor 100 of FIG. 3 . These common elements will not be described in detail below.

In this example: - for each first row portion of pixels PIX of the first group 201A to which the first control circuit 207A is connected, the first control circuit includes a switch 421A connected to interconnect the first row portion of pixels of the first group 201A The conductive track 423A of the control terminal (gate) of the PIX transmission transistor 309; - for each second row portion of pixels PIX of the second group 201B to which the second control circuit 207B is connected, the second control circuit includes a switch 421B connected to interconnect the second row portion of pixels of the second group 201B The conductive track 423B of the control terminal of the PIX transmission transistor 309; - For each first row portion of pixels PIX of the third group 201C to which the third control circuit 207C is connected, the third control circuit includes a switch 421C connected to interconnect the first row portion of pixels of the third group 201C The conductive track 423C of the control terminal of the PIX transmission transistor 309; - For each second row portion of pixels PIX of the fourth group 201D to which the fourth control circuit 207D is connected, the fourth control circuit includes a switch 421D connected to interconnect the second row portion of pixels of the fourth group 201D Conductive track 423D of the control terminal of the PIX transmission transistor 309 .

Conductive tracks 423A, 423B, 423C and 423D are electrically insulated from each other.

In the example shown, each switch is, for example, of the single-pole double-throw type, and more precisely includes an input terminal IN connected to the conductive rails 423A, 423B, 423C and 423D, respectively, a node 325 connected to the applied potential VON. An output terminal OUT1 and a second output terminal OUT2 connected to the node 327 to which the potential VOFF is applied.

In the example of the embodiment of image sensor 200 shown in Figure 4: - for each first column portion of pixels PIX of the first group 201A, the first readout circuit 203A includes an integration circuit 429A of charges photogenerated by the photodetectors 303 of the first column portion of the pixels PIX of the first group 201A ; - for each first column portion of pixels PIX of the second group 201B, the second readout circuit 203B includes an integration circuit 429B of charges photogenerated by the photodetectors 303 of the first column portion of the pixels PIX of the second group 201B ; - For each second column portion of the pixels PIX of the third group 201C, the third readout circuit 203C includes an integration circuit 429C of charges photogenerated by the photodetectors 303 of the pixels PIX of the second column portion of the third group 201C ; - For each second column portion of the pixels PIX of the fourth group 201D, the fourth readout circuit 203D includes an integration circuit 429D of charges photogenerated by the photodetectors 303 of the pixels PIX of the second column portion of the fourth group 201D .

The circuits 429A, 429B, 429C, and 429D of the image sensor 200 are, for example, the same as or similar to the circuits 329A, 329B of the image sensor 100 .

In the example shown: - each circuit 429A of the first readout circuit 203A is connected to a conductive track 415A interconnecting the conductive terminals 311 of the pixels PIX of the same first column portion of the first group 201A; - each circuit 429B of the second readout circuit 203B is connected to a conductive track 415B interconnecting the conductive terminals 311 of the pixels PIX of the same first column portion of the second group 201B; - Each circuit 429C of the third readout circuit 203C is connected to a conductive track 415C interconnecting the conductive terminals 311 of the pixels PIX of the same second column portion of the third group 201C; and - Each circuit 429D of the fourth readout circuit 203D is connected to a conductive track 415D interconnecting the conductive terminals 311 of the pixels PIX of the same second column portion of the fourth group 201D.

In the example shown in Figure 4, nodes 305 of pixels PIX forming part of the same column of array 101 are interconnected by conductive tracks 313 taken to bias potential VBIAS. In this example, the conductive track 313 is connected to the third readout circuit 203C for forming the columns of pixels that are part of the first group 201A and the third group 201C, or to the fourth readout circuit 203D for forming the second Group 201B and a part of the pixel columns of the fourth group 201D.

As a variant, a first assembly of conductive tracks may be provided, each conductive track interconnecting the nodes 305 of the pixels PIX forming part of the same first column portion of the array 101 , and the conductive tracks being electrically insulated from the conductive tracks of the first assembly. A second component, each conductive track interconnects a node 305 of a pixel PIX that forms part of the same second column portion of array 101 . In this case, the potential VBIAS is applied to the column portions of the pixels PIX of the groups 201A, 201B, 201C and 201D, respectively, for example by the readout circuits 203A, 203B, 203C and 203D.

FIG. 5 is a partially simplified top view illustrating an example of an interconnection network of pixels PIX of the image sensor 100 of FIG. 1 . For the sake of simplicity, only a portion of the interconnection network of the pixels PIX of array 101 is shown in Figure 5 to avoid overloading the figure.

In the example shown, the interconnect network includes two stacked conductive metal layers M1 and M2 separated by an insulating layer (not visible in Figure 5). The interconnection network may also include metal vias (not shown) connecting the two metal layers M1 and M2 through an insulating layer.

The fabrication of an interconnection network includes, for example, the following consecutive steps.

During the first deposition step, a plurality of conductive tracks 323 are formed substantially parallel to the row direction (horizontal direction in the orientation of Figure 5) of the array 101 of pixels PIX. Each conductive track 323 interconnects, for example, the control electrodes of all pixels PIX of the same row of the array. The conductive elements formed during this first deposition step define a first conductive layer M1 of the interconnection network.

During the etching step, the conductive track 323 is split, for example by removing portions of the conductive track 323 located between two adjacent pixel columns of the array 101 . Accordingly, the first group 101A and the second group 101B of pixels PIX are delimited and electrically insulated conductive tracks 323A and 323B are formed.

During the third deposition step, conductive tracks 323A and 323B are covered by insulating material (not visible in the figure).

During the third deposition step, conductive tracks 315 are formed on the insulating material substantially parallel to the column direction (vertical direction in the orientation of Figure 5) of the array 101 of pixels PIX.

As shown in Figure 5, the pixel pitch is constant throughout the array 101. In particular, the distance between the last column of the group 101A and the first column of the group 101B in the row direction at the level of the interrupted area of the conductive track 323 is equal to the distance between any two adjacent columns of the group 101A or 101B.

FIG. 6 is a partially simplified top view illustrating an example of an interconnection network of pixels PIX of the image sensor 200 of FIG. 2 . For the sake of simplicity, only a portion of the interconnection network of the pixels PIX of array 101 is shown in Figure 6 to avoid overloading the figure.

The interconnection network of FIG. 6 includes the same components as the interconnection network of FIG. 5 . These identical elements will not be described in detail below. The main difference between the interconnection network in Figure 6 and the interconnection network in Figure 5 is that the conductive tracks 315 are substantially parallel to the column direction of the array 101 of pixels PIX (vertical direction in the orientation of Figure 5), and the conductive tracks 315 are respectively are split into two parts to form tracks 415A and 415C for the first and third sets 201A and 201C of pixels PIX, and tracks 415B and 415D for the second and fourth sets 201B and 201D of pixels PIX.

As an example, the interconnection network of the image sensor 200 is obtained by similar fabrication steps to those previously described in connection with FIG. 5 for the interconnection network of the image sensor 100 , the method further comprising a second etching step, for example after the third deposition step, to detach the conductive track 315.

As shown in Figure 6, the pitch of the pixels is constant throughout the array 101. In particular, at the level of the interruption area of the conductive track 323, the distance in the row direction between the last column of the groups 201A and 201C and the first column of the groups 201B and 201D is equal to any of the groups 201A and 201C or the groups 201B and 201D. The distance between two adjacent columns. Furthermore, at the level of the interrupted area of conductive track 315, the distance in the column direction between the last row of groups 201A and 201B and the first row of groups 201C and 201D is equal to any of the groups 201A and 201B or the groups 201C and 201D. The distance between two adjacent rows.

Figure 7 shows schematically and partially another image sensor 700 according to an embodiment. Image sensor 700 is intended, for example, to be integrated in a fingerprint sensor and/or facial identification or recognition, facial tracking and/or gesture recognition sensor (not shown in Figure 7). The image sensor 700 of FIG. 7 includes common components with the image sensor 100 of FIG. 1 . These common elements will not be described in detail below.

The main difference between the image sensor 700 of FIG. 7 and the image sensor 100 of FIG. 1 is that in the sensor 700, the array 101 of pixels PIX is vertically divided into two different row components. More precisely, in this example, array 101 includes a first group 701A of pixels PIX (region 1) and a second group 701B of pixels PIX (region 2), the first group including components of consecutive rows of pixels PIX of array 101 , and this second group includes another component of the consecutive rows of array 101 pixels PIX. Furthermore, the second group 701B of pixels PIX is adjacent to the first group 701A of pixels PIX, and the row of pixels PIX without array 101 is located between the first group 701A and the second group 701B of pixels PIX. As an example, a first group 701A of pixels PIX corresponds to rows of pixels PIX in one half of array 101 (the upper half in the orientation of Figure 7 ), and a second group 701B of pixels PIX corresponds to the other half of array 101 Groups 701A and 701B have substantially equal numbers of pixels in rows of pixels PIX (lower half in the orientation of Figure 7 ).

As an example, for a sensor with a substantially square shape (with a side length approximately equal to 5 cm), each group of pixels PIX 701A, 701B includes, for example: - For a pixel pitch (the center-to-center distance between two adjacent pixels) of approximately 105 μm, approximately 476 columns and approximately 238 rows; and - For a pixel pitch of approximately 200 μm, approximately 250 columns and approximately 125 rows.

As a variant, for a sensor with a substantially square shape (with a side length approximately equal to 25 mm), each group of pixels PIX 701A, 701B for example includes: for a pixel pitch of approximately 20 μm, approximately 1250 columns and About 625 lines.

However, the examples of shapes, sizes, and numbers of pixels in each group 701A, 701B indicated above are non-limiting, and those skilled in the art will be able to adapt the described embodiments to those having pixels in each group 701A, 701B. Sensors of any shape, size and quantity.

Similar to what was previously described in connection with sensor 100 of FIG. 1 , the pixels PIX of the first group 701A are connected to the first readout circuit 103A (ROIC 1 ) of the image sensor 700 , and the pixels of the second group 701B PIX is connected to the second readout circuit 103B (ROIC 2) of the image sensor 700 . In this example, each column of pixels PIX of the array is split into a first column portion and a second column portion, such that its pixels PIX form part of a first group 701A and a part of a second group 701B, respectively. The pixels PIX of the first group 701A forming part of the first column part are e.g. interconnected and connected to the first readout circuit 103A, and the pixels PIX of the second group 701B forming part of the same second column part are e.g. interconnected and connected to the second readout circuit 103B.

In the example shown in Figure 7, the readout circuits 103A and 103B are connected to the control unit 105 (UC).

Furthermore, in the example shown, the pixels PIX of the first group 701A are, for example, interconnected and connected to the first control circuit 107A (GOA 1) of the image sensor 100 , and the pixels PIX of the second group 701B are, for example, interconnected and Connected to the second control circuit 107B (GOA 2) of the image sensor 100.

As an example, the readout circuits 103A and 103B, the control unit 105 and the control circuits 107A and 107B of the sensor 700 are arranged relative to the array 101 of pixels PIX, as shown in Figure 7 . In the example shown, readout circuits 103A and 103B are respectively arranged on either side of the array 101 of pixels PIX. More precisely, readout circuit 103A is located in front of a first side of array 101 and readout circuit 103B is located in front of a second side of array 101 opposite the first side. Furthermore, in this example, control circuit 107A is located in front of a third side of array 101 that is orthogonal to the first and second sides, and control circuit 107B is located in front of a fourth side of array 101 that is opposite the third side. In the example shown in Figure 7, control circuit 107A extends laterally parallel to the third side of array 101 in front of group 701A of pixels PIX, and does not extend in front of group 701B of pixels PIX. Similarly, control circuitry 107B extends laterally parallel to the fourth side of array 101 in front of group 701B of pixels PIX, and does not extend in front of group 701A of pixels PIX. The first, second, third and fourth sides of the array 101 respectively correspond to the lower, upper, left-hand and right-hand sides of the array in the orientation of Figure 7 .

In the example shown, the sensor 700 further includes a first bias line 703A and a second bias line 703B arranged on either side of the array 101 of pixels PIX and connected to the readout circuits 103A and 103B respectively. . In the example shown in Figure 7, bias line 703A extends laterally parallel to the fourth side of array 101 in front of group 701A of pixels PIX, and does not extend in front of group 701B of pixels PIX. Similarly, bias line 703B extends laterally parallel to the third side of array 101 in front of group 701B of pixels PIX, and does not extend in front of group 701A of pixels PIX.

Each bias line 703A, 703B is set to a bias potential VBIAS, for example. As an example, bias line 703A is connected to a first conductive layer common to all pixels PIX in area 701A of array 101, such as a transparent metal layer extending in front of the pixels PIX in area 701A. Similarly, the bias line 703B is connected to, for example, a second conductive layer common to all pixels PIX in the area 701B of the array 101, such as another transparent metal layer extending in front of the pixels PIX in the area 701B, the second conductive layer being the same as the first conductive layer. layer of electrical insulation. As a variant, bias lines 703A and 703B are connected to a conductive track common to all pixels PIX of array 101, such as a transparent metal layer extending in front of the pixels PIX of array 101.

In the example shown, sensor 700 has a symmetrical arrangement of readout circuitry, control circuitry and bias circuitry associated with different groups of pixels. Therefore, the available space around the array of pixels PIX is optimally occupied. This further enables providing the readout circuit 103B and the control circuit 107B connected to the group 701B of pixels PIX with the same operation as the readout circuit 103A and the control circuit 107A connected to the group 701A of pixels PIX. This specifically enables the readout circuit 103B and the control circuit 107B to be designed identically to the readout circuit 103A and the control circuit 107A, specifically addressing the circuit 107B using the same control signals as the circuit 107A. In other words, this enables the groups 701A and 701B of pixels PIX of array 101 to be driven as if there were two identical arrays of pixels PIX.

As an example, the rows of pixels PIX forming part of group 701A are read from the center of array 101 towards the first side of the array (the upper side in the orientation of Figure 7), and the rows of pixels PIX forming part of group 701B are read from The center of the array 101 is read towards the second side of the array (the lower side in the orientation of Figure 7).

Various embodiments and modifications have been described. Those skilled in the art will understand that certain features of these various embodiments and variations may be combined, and those skilled in the art will appreciate other variations. An example of an embodiment has been described in connection with Figure 1, in which horizontal interconnecting conductive tracks are interrupted to divide the array into two different groups of columns. As a variant, a sensor may be provided in which the horizontal interconnecting conductive tracks are uninterrupted and the vertical interconnecting conductive tracks are interrupted to divide the array into two different groups of rows. Each group of rows may then include a specific readout circuit 103 and a specific control circuit 107 .

Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of those skilled in the art.

100:Image sensor 101:Array 101A: The first group of pixel PIX 101B: The second group of pixel PIX 103A: First readout circuit 103B: Second readout circuit 105:Control unit (UC) 107A: First control circuit 107B: Second control circuit 201A: The first group of pixel PIX 201B: The second set of Pixel PIX 201C: The third group of pixel PIX 201D: The fourth group of pixel PIX 203A: First readout circuit 203B: Second readout circuit 203C: The third readout circuit 203D: Fourth readout circuit 207A: First control circuit 207B: Second control circuit 207C: Third control circuit 207D: Fourth control circuit 303: Photoelectric detector 305:node 307:node 309:Transmission transistor 311: Charge collection node 313: Conductive track 315: Conductive track 321: switch 321A: switch 321B: switch 323: Conductive track 323A: Conductive track 323B: Conductive track 325:node 327:node 329A: Integrated circuit 329B: Integrated circuit 415A: Conductive track 415B: Conductive track 415C: Conductive track 415D: Conductive track 421A: switch 421B: switch 421C: switch 421D: switch 423A: Conductive track 423B: Conductive track 423C: Conductive track 423D: Conductive track 429A: Integrated circuit 429B: Integrated circuit 429C: Integrated circuit 429D: Integrated circuit 700:Image sensor 701A: The first group of pixel PIX 701B: The second group of pixel PIX 703A: The third group of pixel PIX 703B: The fourth group of pixel PIX VON: potential VOFF:potential VBIAS: bias potential IN: input terminal OUT1: The first output terminal OUT2: The second output terminal PIX: pixel M1: Conductive metal layer M2: Conductive metal layer ROIC 1: First readout circuit ROIC 2: Second readout circuit Area 1: First group of pixels PIX Area 2: Second group of pixels PIX GOA 1: First control circuit GOA 2: Second control circuit UC: control unit

The above features and advantages, among others, will be described in detail in the remainder of the present disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

Figure 1 schematically and partially illustrates an image sensor according to an embodiment;

Figure 2 schematically and partially illustrates another image sensor according to an embodiment;

Figure 3 is an electrical diagram illustrating an example of the embodiment of the image sensor of Figure 1;

Figure 4 is an electrical diagram illustrating an example of the embodiment of the image sensor of Figure 2;

Figure 5 is a partially simplified top view illustrating an example of an embodiment of an interconnection network of pixels of the image sensor of Figure 1;

Figure 6 is a partially simplified top view illustrating an example of an embodiment of an interconnection network of pixels of the image sensor of Figure 2; and

Figure 7 shows schematically and partially a further image sensor according to an embodiment.

Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without

100:Image sensor

101:Array

101A: The first group of pixel PIX

101B: The second group of pixel PIX

103A: First readout circuit

103B: Second readout circuit

105:Control unit (UC)

107A: First control circuit

107B: Second control circuit

Claims (14)

An image sensor includes a support substrate and an array (101) of pixels (PIX) formed on the support substrate. The pixels of the array are regularly arranged in rows and columns with a constant pitch, each The pixel (PIX) includes at least one photodiode (308) and a transmission transistor (309), where: A) Each row of pixels is divided into a first adjacent row portion and a second adjacent row portion, a first conductive row track (323A; 423A, 423C) interconnecting the transistors of the pixels in the first row portion and a second conductive row track (323B; 423B, 423D) electrically insulated from the first conductive row track interconnecting the first terminals of the transistors of the pixels of the second row portion ;and/or B) Each pixel column is divided into a first adjacent column portion and a second adjacent column portion, and a first conductive column track (415A, 415B) interconnects the transistors of the pixels in the first column portion. second terminals, and a second conductive column track (415C, 415D) is electrically insulated from the first conductive column track interconnecting the second terminals of the transistors of the pixels of the second column portion, wherein the The first row or column portion or the second row or column portion is formed by a group of adjacent pixels. The sensor of claim 1, in option B), wherein the pixels of the first column portion define a first area (701A) and the pixels of the second column portion define a In the second area (701B), the pixels (PIX) of the first area (701A) are connected to a same first readout circuit (103A) of the sensor and to a same first readout circuit (103A) of the sensor. a control circuit (107A), and the pixels (PIX) of the second area (701B) are connected to a same second readout circuit (103B) of the sensor and to a same second readout circuit (103B) of the sensor. 2. Control circuit (107B). The sensor of claim 2, wherein the first readout circuit (103A) is arranged in front of a first side of the array (101) of pixels (PIX), and the second readout circuit (103B) Arranged in front of a second side of the array (101) of pixels (PIX) opposite the first side. The sensor of claim 3, wherein the first control circuit (107A) is arranged in a third of the array (101) of pixels (PIX) orthogonal to the first side and the second side. side front, and the second control circuit (107B) is arranged in front of a fourth side of the array (101) of pixels (PIX) opposite to the third side. The sensor of claim 4, further comprising a first bias line and a second bias line respectively arranged in front of the fourth side and the third side of the array (101) of pixels (PIX) Line (703A, 703B). The sensor of claim 1, in option A), wherein the pixels of the first row portion define a first area (101A) and the pixels of the second row portion define a In the second area (101B), the pixels (PIX) of the first area (101A) are connected to a same first readout circuit (103A) of the sensor and to a same first readout circuit (103A) of the sensor. control circuit (107A), and the pixels of the second area (101B) are connected to a same second readout circuit (103B) of the sensor and to a same second control circuit of the sensors (107B). The sensor of claim 2, wherein each of the first regions (101A; 701A) and the second regions (101B; 701B) includes approximately as many pixels as the array (101) A number that is half the total number of pixels (PIX). The sensor of claim 1, in options A) and B), wherein the pixels (PIX) of the first row portion and the first column portion define a first area (201A) , the pixels (PIX) in the second row part and the first column part define a second area (201B), and the pixels (PIX) in the first row part and the second column part A third area (201C) is defined, and the pixels (PIX) of the second row portion and the second column portion define a fourth area (201D), and the pixels (PIX) of the first area (201A) The pixels (PIX) are connected to a same first readout circuit (203A) of the sensor and to a same first control circuit (207A) of the sensor, the pixels of the second area (201B) (PIX) connected to an identical second readout circuit (203B) of the sensor and connected to an identical second control circuit (207B) of the sensor, the pixels of the third region (201C) ( PIX) is connected to an identical third readout circuit (203C) of the sensor and to an identical third control circuit (207C) of the sensor, and the pixels ( PIX) is connected to an identical fourth readout circuit (203D) of the sensor and to an identical fourth control circuit (207D) of the sensor. The sensor of claim 8, wherein each of the first area (201A), the second area (201B), the third area (201C) and the fourth area (201D) includes approximately A number of pixels equal to one quarter of the total number of pixels of the array (101). The sensor of claim 1, wherein the first terminal of the transmission transistor (309) is a gate terminal, and the second terminal of the transmission transistor (309) is a source terminal or a drain terminal. . The sensor of claim 1, wherein the photodiodes (308) of the pixels (PIX) are organic photodiodes. The sensor of claim 1, wherein the transmission transistors (309) of the pixels (PIX) are TFT transistors. A fingerprint sensor including the image sensor described in claim 1. An image sensor manufacturing method, which includes the following steps: a) Form an array (101) of pixels (PIX) regularly arranged in rows and columns at a constant pitch, each pixel (PIX) including at least one photodiode (308) and a transmission transistor (309); as well as b) - For each pixel row, forming a conductive row track interconnecting the first terminals of the transistors of the pixels in the row, and then regionally etching the conductive row track to divide it into a first conductive row track ( 323A; 423A, 423C) and dividing it into a second conductive row track (323B; 423B, 423D) electrically insulated from the first conductive row track; and/or - For each pixel column, forming a conductive column track interconnecting the second terminals of the transistors of the pixels in the column, and then regionally etching the conductive column track to divide it into a first conductive column track ( 415A, 415B) and divide it into a second conductive column track (415C, 415D) that is electrically insulated from the first conductive column track.