TW201143063A - Inter-wafer interconnects for stacked CMOS image sensors - Google Patents

Inter-wafer interconnects for stacked CMOS image sensors Download PDF

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TW201143063A
TW201143063A TW099146547A TW99146547A TW201143063A TW 201143063 A TW201143063 A TW 201143063A TW 099146547 A TW099146547 A TW 099146547A TW 99146547 A TW99146547 A TW 99146547A TW 201143063 A TW201143063 A TW 201143063A
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wafer
sensor
charge
voltage conversion
inter
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Cristian A Tivarus
John P Mccarten
Joseph R Summa
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Eastman Kodak Co
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers

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Abstract

An image sensor includes a sensor wafer and a circuit wafer electrically connected to the sensor wafer. The sensor wafer includes unit cells with each unit cell having at least one photodetector and a charge-to-voltage conversion region. The circuit wafer includes unit cells with each unit cell having an electrical node that is associated with each unit cell on the sensor wafer. An inter-wafer interconnect is connected between each charge-to-voltage conversion region on the sensor wafer and a respective electrical node on the circuit wafer. A location of a portion of the unit cells on the sensor wafer and a location of a corresponding portion of the unit cells on the circuit wafer are shifted a predetermined distance with respect to the locations of the remaining unit cells on the sensor and circuit wafers.

Description

201143063 六、發明說明： 【發明所屬之技術領域^ 本發明大體上係關;^互補金氧半㈣(cmqs)影像感測 器，且更明確地說’係關於具有兩個獨立堆疊式半導體晶圓 之CMOS影像感測器，其中每一晶圓包括電路之一部分。 更明確地說’本發明係關於用於具有兩個獨立堆疊式半導體 晶圓之CMOS影像感測器的晶圓間互連。 【先前技術】 圖1為根據先前技術之一具體例中的具有兩個半導體晶 圓之影像感測器的橫剖面圖。感測器晶圓1〇〇包括光偵測器 102、104、電荷至電麼轉換區i〇6(sw)，及用於將光生電荷 分別自光偵測器102、104傳送至電荷至電壓轉換區i〇6(sw) 之傳送閘108、110。 電路晶圓112包括用於感測器晶圓100上之電路的支援電 路。晶圓間互連114將電荷至電壓轉換區1 〇6(sw)連接至電 路晶圓112上之電荷至電壓轉換區1〇6(cw)。如圖j中所展 示，電荷至電壓轉換區l〇6(sw)與l〇6(cw)彼此垂直對準， 以使得晶圓間互連114追隨該兩個電荷至電壓轉換區之間 的直線。 圖2為感測器晶圓1〇〇之一部分的俯視圖之圖形說明。感 測器晶圓100包括單元晶胞200,其中每一單元晶胞具有四 個光偵測器 102、104、202、204、傳送閘 108、110、208、 099146547 201143063 210、電荷至電壓轉換區106(sw)及晶圓間互連114(以虛線 展示）。互連間距或兩個相鄰之晶圓間互連或互連接觸點之 間的距離為影響堆疊式影像感測器之大小及構造的一個因 素。在圖2中，將兩個行相鄰（在同一列中）之晶圓間互連之 間的互連間距標識為距離a，而將兩個列相鄰（在同一行中） 之晶圓間互連之間的互連間距標識為距離b。如可在矩形形 狀之光偵測器中發生，當距離b大於距離a時，最小互連間 距為距離a。 影像感測器可具有五百萬至一千萬像素，其中每一像素小 至1.4微米。且由於對較高影像解析度之需求增加，未來影 像感測器將具有更小尺寸之像素。就此類小像素尺寸而論， 互連間距可為幾微米。不幸的是，當前半導體製造程序並非 總是能夠可靠地製造具有此類小互連間距之晶圓間互連。 【發明内容】 一種影像感測器包括一感測器晶圓及一電連接至該感測 器晶圓之電路晶圓。該感測器晶圓包括單元晶胞，其中每一 單元晶胞具有至少一個光偵測器及一電荷至電壓轉換區。該 電路晶圓包括單元晶胞，其中每一單元晶胞具有一與該感測 器晶圓上之每一單元晶胞相關聯的電節點。一晶圓間互連連 接於該感測器晶圓上之每一電荷至電壓轉換區與該電路晶 圓上之一各別電節點之間。該感測器晶圓上之該等單元晶胞 之一部分的一位置及該電路晶圓上之該等單元晶胞之一對 5 099146547 5 201143063 應邛刀的位置相對於該感測裔晶圓及該電路晶圓上之剩 餘單元晶胞之位置而移位達一預定距離。 【實施方式】 遍及本說明書及申請專利範圍，以下術語採用本文中明確 相關聯之含義，除非上下文另有清楚指示。「―」及「該」 之料包括複數參考，「在……中」之含義包括「在......中」 及在 上」。術語「連接」意謂經連接之物品之間的直 接電連接《思4經由-或多個被動或主動中間裝置之間接 連接術°吾冑路」意謂連接起來以提供所要功能的單-組 =多個組件，無論是主動組件或是被動組件。術語「信號」 意謂至少一電流、電壓或資料信號。 上方」、「頂部」、「底部」 另外，諸如「在……上」、「在 方向考所描述之圖式的定向來加以使用。因為本 發明之具體例之組件可以許多不同定向來定位，因此方向性 術語僅用於達成說明目的而決非限•當結合影像感測器晶 圓或對應影像感職之層來使用時，方向性術語意欲廣義地 、解因此不應解釋為排除一或多個介入層或其他介 入景緣感测器特徵或元件之存在。因此，本文中描述為形成 於另層上或形成於另—層上方之給定層可藉由一或多個 額外層而與該另一層分離。 且最後’術S#「晶圓」及「基板」將理解為基於半導體之 材料’包括但不限於梦、絕緣體上邦01)技術藍寶石上 099146547 201143063 梦（SOS)技術、推雜及非推雜之车道興 上之遙晶層或井區，及其鮮導體結構/成於半導體基板 參看圖式’相減字献諸圖指神似部分。 圖3為根據本發明之具體例中的影_ 塊圖。影像㈣置在圖3中實施為數位=之= 藝者應瞭解到，數位相機僅為可利用併有本發明、減 器的影像擷取裴置之一個實& 月之影像感測 (諸如，蜂巢式電二:類型之影像咖 本發明 減、及触視簡錄機)可用於 在數位相機300中，來自主雜場景之光 304。成像級3〇4可包括習知元件，諸至成像級 光器、光圈及快門。光302藉由成像級綱聚焦以 測器306上形成影像。影像感測器·藉由將入射光轉換成 電信號而擷取一或多個影像。數位相機3〇〇進一步包括處理 器308、記憶體31。、顯示器312及一或多個額外:入/輸出 (I/O)兀件314。儘管在圖3之具體例中展示為獨立元件，但 成像級304可與影像感測器遍整合且可能與數位相機_ 之-或多個額外元件整合以形成相機模組。舉例而言，在根 據本發明之具體例中，處理器或記憶體可與影像感測器3〇6 整合於一相機模組中。 處理器308可實施（例如）為微處理器、中央處理單元 (CPU)、特殊應用積體電路(ASIC)、數位信號處理器（DSp)， 099146547 7 201143063 或其他處理震置，或多個此類裝置之組合。成像級304及影 像感測器306之久括-从奸 上 ’、 種兀件可藉由自處理器308供應之時序信 號或其他信號來控制。 " 記憶體310可鈿吨决/ 、、且態為任何類型之記憶體，諸如隨機存取記 憶體(RAM)、唯讀記憶體(R〇M)、快閃記憶體、基於磁碟之 5己憶體、抽取式記憶體，或其他類型之儲存元件，按照任一 組合形式來組態。藉由影像感測器3G6摘取之給予影像可藉 由處理器通儲存於記憶體31〇中且在顯示器312上呈現。 顯示器312通常為主動式矩陣彩色液晶顯示器(lcd)，何 使用其他類型之顯示器。額外1/〇元件314可包括(例如)各 種螢幕上之控制件、按城其他使用者介面、網路介面，或 記憶卡介面。 應瞭解，圖3中所展示之數位相機可包含熟悉技藝者已知 之類型的辦或替航件。本文中未具體展示或描述之元件 可自此項技射已知之元件選擇。如先前所註明，本發明可 實施於各種影像齡袭置中。此外，本文中所描述之具體例 的某些態樣可至少部分以藉由影像齡裝置之-或多個處 理元件執行的軟體之形式來實施。如闕技藝者將瞭解，給 予提供於本文中之教示，此峰體可以直接之方式來實施。 現參看圖4,展示根據本發明之具體例中的影像感刺器之 俯視圖的方塊圖。影像感測器鄕包括許多像素棚，其通 常配置及行，該料及行形成像素_他。影像感測 099146547 201143063 器306進-步包括行解瑪器4〇4、列解碼器4〇6、數位邏輯 408、多個類比或數位輸出電路41()及時序產生器41 素陣列402中的像素權之每一行電連接至-輸出電路 、410。時序產生器412產生自像素陣列402讀出信號所需之 信號。 在根據本發明之具體例中，影像感測器3 〇 6實施為形成於 兩個或兩個以上半導體晶圓上的x_y可定址影像感測器，諸 如堆疊式互補金氧半導體(CM0S)影像感測器。因此，行解 碼器404、列解碼器4〇6、數位邏輯4〇8、類比或數位輸出 通道410及時序產生器412實施為操作性地連接至像素陣列 400之標準CMOS電子電路。 與像素陣列402之取樣及讀出以及對應影像資料之處理 相關聯的功此性可至少部分以儲存於記憶體41〇(見圖4)中 且藉由處理器408執行的軟體之形式來實施。取樣及讀出電 路之部分可配置於影像感測器3〇6外部或與像素陣列4〇2 整體地形成於（例如）與光偵測器及像素陣列之其他元件共 有之積體電路上。熟悉技藝者應瞭解到，其他周邊電路組態 或架構可實施於根據本發明之其他具體例中。 圖5為根據本發明之可在具有兩個半導體晶圓之影像感 測器中實施的第一像素架構的示意圖。光偵測器5〇〇、傳送 閘502及電荷至電壓轉換區5〇4(sw)裝設於感測器晶圓5〇6 上。在根據本發明之具體例中，光偵測器5〇〇、傳送閘5〇2201143063 VI. Description of the Invention: [Technical Field of the Invention] The present invention is generally related to a ^^ complementary gold-oxygen (C) image sensor, and more specifically 'with respect to having two independently stacked semiconductor crystals A circular CMOS image sensor in which each wafer includes a portion of a circuit. More specifically, the present invention relates to inter-wafer interconnections for CMOS image sensors having two independently stacked semiconductor wafers. [Prior Art] Fig. 1 is a cross-sectional view of an image sensor having two semiconductor wafers according to a specific example of the prior art. The sensor wafer 1 includes a photodetector 102, 104, a charge-to-electric conversion region i 〇 6 (sw), and is used to transfer photo-generated charges from the photodetectors 102, 104 to the charge-to-voltage Transfer gates 108, 110 of transition zone i 〇 6 (sw). Circuit wafer 112 includes support circuitry for circuitry on sensor wafer 100. The inter-wafer interconnect 114 connects the charge-to-voltage conversion region 1 〇 6 (sw) to the charge on the circuit wafer 112 to the voltage conversion region 1 〇 6 (cw). As shown in Figure j, the charge-to-voltage conversion regions 106(sw) and 106(cw) are vertically aligned with each other such that the inter-wafer interconnect 114 follows the two charge-to-voltage conversion regions. straight line. 2 is a graphical illustration of a top view of a portion of the sensor wafer 1 。. The sensor wafer 100 includes a unit cell 200, wherein each unit cell has four photodetectors 102, 104, 202, 204, transfer gates 108, 110, 208, 099146547 201143063 210, charge to voltage conversion region 106 (sw) and inter-wafer interconnect 114 (shown in dashed lines). The interconnect pitch or the distance between two adjacent inter-wafer interconnect or interconnect contact points is a factor influencing the size and configuration of the stacked image sensor. In FIG. 2, the interconnection pitch between the inter-wafer interconnections of two rows adjacent (in the same column) is identified as the distance a, and the wafers of two columns adjacent (in the same row) are The interconnect spacing between interconnects is identified as distance b. If it occurs in a rectangular photodetector, when the distance b is greater than the distance a, the minimum interconnection distance is the distance a. The image sensor can have from five to ten million pixels, with each pixel being as small as 1.4 microns. And because of the increased demand for higher image resolution, future image sensors will have smaller pixels. For such small pixel sizes, the interconnect pitch can be a few microns. Unfortunately, current semiconductor fabrication processes are not always able to reliably manufacture inter-wafer interconnects with such small interconnect pitches. SUMMARY OF THE INVENTION An image sensor includes a sensor wafer and a circuit wafer electrically connected to the sensor wafer. The sensor wafer includes a unit cell, wherein each unit cell has at least one photodetector and a charge to voltage conversion region. The circuit wafer includes a unit cell, wherein each unit cell has an electrical node associated with each unit cell on the sensor wafer. An inter-wafer interconnect is connected between each of the charge-to-voltage conversion regions on the sensor wafer and a respective one of the electrical nodes on the circuit crystal. a position of a portion of the unit cells on the sensor wafer and a position of the unit cells on the circuit wafer 5 099146547 5 201143063 The position of the file is relative to the sensing wafer And shifting the position of the remaining unit cells on the circuit wafer by a predetermined distance. [Embodiment] Throughout the specification and claims, the following terms are to be explicitly referred to herein, unless the context clearly indicates otherwise. The materials of "" and "the" include plural references. The meaning of "in" includes "in" and above. The term "connected" means a direct electrical connection between connected items "Si 4 through- or a plurality of passive or active intermediate devices connected to each other" means a single-group that is connected to provide the desired function. = Multiple components, either active or passive. The term "signal" means at least one current, voltage or data signal. "Top", "Top", "Bottom" In addition, such as "on", "the orientation of the drawings described in the direction of the test is used. Because the components of the specific examples of the present invention can be positioned in many different orientations, Therefore, directional terminology is used for illustrative purposes only and is in no way limited. When used in conjunction with an image sensor wafer or a layer corresponding to the image, the directional terminology is intended to be broadly defined and therefore should not be construed as excluding one or The presence of multiple intervening layers or other intervening edge sensor features or elements. Thus, a given layer described herein as being formed on another layer or formed over another layer may be by one or more additional layers. Separate from the other layer. Finally, 'S1' "wafer" and "substrate" will be understood as semiconductor-based materials 'including but not limited to dreams, insulators on the state 01. Technology sapphire on 099146547 201143063 Dream (SOS) technology, The noisy and non-hybrid lanes are on the crystal layer or well area, and the structure of the fresh conductor/formed on the semiconductor substrate is shown in the figure. Fig. 3 is a block diagram of a specific example in accordance with the present invention. The image (4) is implemented in Figure 3 as a digital = = The artist should understand that the digital camera is only a real & month image sensing of the image capture device that can be utilized and has the invention and the reducer (such as The honeycomb type 2: type of image coffee, the invention minus, and the touch recorder can be used in the digital camera 300, the light 304 from the main scene. Imaging stage 3〇4 can include conventional components, such as imaging level light, aperture, and shutter. Light 302 is imaged by detector 306 by imaging stage focusing. Image sensor - captures one or more images by converting incident light into an electrical signal. The digital camera 3 further includes a processor 308 and a memory 31. Display 312 and one or more additional: In/Out (I/O) components 314. Although shown as a separate component in the specific example of FIG. 3, imaging stage 304 can be integrated with the image sensor and possibly integrated with the digital camera or multiple additional components to form a camera module. For example, in a particular embodiment of the invention, the processor or memory can be integrated with a video sensor 3〇6 in a camera module. The processor 308 can be implemented, for example, as a microprocessor, central processing unit (CPU), special application integrated circuit (ASIC), digital signal processor (DSp), 099146547 7 201143063 or other processing, or multiple A combination of class devices. The imaging stage 304 and the image sensor 306 can be controlled by a timing signal or other signal supplied from the processor 308. " Memory 310 can be any type of memory, such as random access memory (RAM), read-only memory (R〇M), flash memory, disk-based 5 Remembrance, removable memory, or other types of storage components, configured in any combination. The image given by the image sensor 3G6 can be stored in the memory 31 by the processor and presented on the display 312. Display 312 is typically an active matrix color liquid crystal display (LCD), and other types of displays are used. Additional 1/〇 elements 314 may include, for example, various on-screen controls, other user interfaces by network, a network interface, or a memory card interface. It will be appreciated that the digital camera shown in Figure 3 can comprise a server or a navigational member of the type known to those skilled in the art. Elements not specifically shown or described herein may be selected from the elements known in the art. As noted previously, the present invention can be implemented in a variety of image ageing settings. Moreover, certain aspects of the specific examples described herein can be implemented, at least in part, in the form of software executed by the image-age device or the plurality of processing elements. As will be appreciated by those skilled in the art, given the teachings provided herein, this peak can be implemented in a straightforward manner. Referring now to Figure 4, there is shown a block diagram of a top view of an image feeler in accordance with a particular embodiment of the present invention. Image sensor 鄕 includes a number of pixel sheds, which are typically configured and lined, and the material and lines form pixels. Image sensing 099146547 201143063 306 step-by-step includes row solver 4〇4, column decoder 4〇6, digital logic 408, multiple analog or digital output circuits 41(), and timing generator 41 in the array 402 Each row of pixel weights is electrically coupled to an -output circuit, 410. Timing generator 412 generates the signals required to read signals from pixel array 402. In a specific example in accordance with the invention, image sensor 3 实施 6 is implemented as an x_y addressable image sensor formed on two or more semiconductor wafers, such as stacked complementary metal oxide semiconductor (CMOS) images. Sensor. Accordingly, row decoder 404, column decoder 4〇6, digital logic 4〇8, analog or digital output channel 410, and timing generator 412 are implemented as standard CMOS electronic circuits operatively coupled to pixel array 400. The functionality associated with the sampling and reading of pixel array 402 and the processing of corresponding image data may be implemented, at least in part, in the form of software stored in memory 41 (see FIG. 4) and executed by processor 408. . Portions of the sampling and readout circuitry may be disposed external to image sensor 3〇6 or integrally formed with pixel array 4〇2, for example, on an integrated circuit common to the photodetector and other elements of the pixel array. Those skilled in the art will appreciate that other peripheral circuit configurations or architectures can be implemented in other specific embodiments in accordance with the present invention. Figure 5 is a schematic illustration of a first pixel architecture that can be implemented in an image sensor having two semiconductor wafers in accordance with the present invention. The photodetector 5, the transfer gate 502, and the charge-to-voltage conversion region 5〇4 (sw) are mounted on the sensor wafer 5〇6. In a specific example according to the present invention, the photodetector 5〇〇, the transfer gate 5〇2

099146547 Λ S 201143063 及電荷至電壓轉換區504(sw)在感測器晶圓506上形成一例 示性單元晶胞。 電荷至電壓轉換區504(cw)、重設電晶體508、電位VDD 510、放大器512及列選擇電晶體514建構於電路晶圓516 上。在根據本發明之具體例中，電荷至電壓轉換區504(sw)、 504(cw)實施為浮動擴散區，且放大器512實施為源極追隨 器電晶體。列選擇電晶體514之一個源極/汲極電極連接至 放大器512之一源極/汲極電極，而列選擇電晶體514之另 一個源極/汲極電極連接至輸出線518。重設電晶體508及放 大器512兩者之源極/汲極電極維持於電位vDD 51〇。電節點 519將重設電晶體508之另一個源極/汲極電極、放大器5 之閘極及電荷至電壓轉換區5〇4(CW)連接到一起。 晶圓間互連520將感測器晶圓506上之電荷至電壓轉換區 504(sw)連接至電路晶圓516上之電節點519。 光偵測器500回應於入射光而收集電荷。傳送閘5〇2選擇 性地將收集到之電荷自光偵測器5〇〇傳遞至電荷至電壓轉 換區504(sw)。晶圓間互連520將該電荷自感測器晶圓5〇6 上之電荷至電壓轉換區504(sw)傳輪至電路晶圓516上之電 荷至電壓轉換區504(cw)。 電荷至電壓轉換區504㈣將電荷轉換成接著由放大器 5!2感測並緩衝之電壓。當列選擇電晶體μ致能時，將該 電壓傳送至輸出線518。重設電晶體用以將電荷至電廢 099146547 201143063 轉換區504(sw)、5〇4(cw)重設至已知電位51〇。 在根據本發明之具體例中，電荷至電壓轉換區5()4㈣及 放大器包括於電路晶圓516上之一單元晶胞中。在根據 、本u之其他具體例中，重設電晶體5Q8及列選擇電晶體 514(個別地或組合起來)可包括於電路晶圓516上之該單元 晶胞中。 圖6為根據本發明之具體财的可在具有兩個半導體晶 圓之影像感測器中實施的第二像素架構的示意圖。光偵測器 600、傳送閘602、電荷至電壓轉換區6〇4及重設電晶體6〇6 裝设於感測器晶圓608上。重設電晶體606之-個源極/汲 極電極連接至電荷至電壓轉換區刚’而重設電晶體祕之 另-個源極/汲極電極維持於電位Vdd61〇。在根據本發明之 具體例中，光侧器_、傳送閘6〇2、電荷至電壓轉換區 604及重設電晶體606在感測器晶圓6〇8上形成一例示性單 凡晶胞。 放大器612及列選擇電晶體614建構於電路晶圓616上。 列選擇電晶體614之-個源極/域電極連接至放大器612 之-源極/汲極電極’而闕擇電晶體614之另—個源極/沒 '極電極連接至輸出線618。放大器612之另一個源極/沒極電 極維持於電位Vdd61()。在根據本發明之具體例中，電荷至 電壓轉換區604實施為浮動擴散區，且放大器612實施為源 極追隨器電晶體。099146547 Λ S 201143063 and charge-to-voltage conversion region 504 (sw) form an exemplary unit cell on the sensor wafer 506. Charge-to-voltage conversion region 504 (cw), reset transistor 508, potential VDD 510, amplifier 512, and column select transistor 514 are constructed on circuit wafer 516. In a specific example in accordance with the invention, charge to voltage transition regions 504 (sw), 504 (cw) are implemented as floating diffusion regions, and amplifier 512 is implemented as a source follower transistor. One source/drain electrode of column select transistor 514 is coupled to one source/drain electrode of amplifier 512, and the other source/drain electrode of column select transistor 514 is coupled to output line 518. The source/drain electrodes of both reset transistor 508 and amplifier 512 are maintained at potential vDD 51 〇. Electrical node 519 connects the other source/drain electrode of reset transistor 508, the gate of amplifier 5, and the charge-to-voltage conversion region 5〇4 (CW). The inter-wafer interconnect 520 connects the charge-to-voltage conversion region 504 (sw) on the sensor wafer 506 to the electrical node 519 on the circuit wafer 516. The photodetector 500 collects electric charges in response to incident light. The transfer gate 5〇2 selectively transfers the collected charge from the photodetector 5〇〇 to the charge-to-voltage conversion region 504 (sw). The inter-wafer interconnect 520 transfers the charge from the sensor wafer 5〇6 to the voltage conversion region 504 (sw) to the charge on the circuit wafer 516 to the voltage conversion region 504 (cw). The charge-to-voltage conversion region 504 (4) converts the charge into a voltage that is then sensed and buffered by the amplifier 5!2. This voltage is delivered to output line 518 when column select transistor μ is enabled. The transistor is reset to reset the charge to the electrical waste 099146547 201143063 conversion region 504(sw), 5〇4(cw) to a known potential 51〇. In a specific example in accordance with the present invention, the charge-to-voltage conversion region 5() 4(4) and the amplifier are included in one of the unit cells on the circuit wafer 516. In other embodiments according to the present invention, the reset transistor 5Q8 and the column select transistor 514 (individually or in combination) may be included in the unit cell on the circuit wafer 516. Figure 6 is a schematic illustration of a second pixel architecture that can be implemented in an image sensor having two semiconductor wafers in accordance with the teachings of the present invention. The photodetector 600, the transfer gate 602, the charge-to-voltage conversion region 6〇4, and the reset transistor 6〇6 are mounted on the sensor wafer 608. A source/thoracic electrode of the reset transistor 606 is connected to the charge-to-voltage conversion region just after the transistor is reset, and the other source/drain electrode is maintained at the potential Vdd61〇. In a specific example according to the present invention, the photo side device _, the transfer gate 〇2, the charge-to-voltage conversion region 604, and the reset transistor 606 form an exemplary single-cell cell on the sensor wafer 〇8. . Amplifier 612 and column select transistor 614 are constructed on circuit wafer 616. One source/domain electrode of column select transistor 614 is coupled to the source/drain electrode of amplifier 612 and the other source/no electrode of select transistor 614 is coupled to output line 618. The other source/no-pole of amplifier 612 is maintained at potential Vdd61(). In a particular example in accordance with the invention, charge to voltage transition region 604 is implemented as a floating diffusion region and amplifier 612 is implemented as a source follower transistor.

S 099146547 201143063 晶圓間互連620將感測器晶圓608上之電荷至電壓轉換區 604連接至電路晶圓616上之放大器612之閘極。在根據本 發明之具體例中，放大器612之閘極被視為電路晶圓616 上之一電節點。另外’在根據本發明之具體例中，放大器 612包括於電路晶圓616上之一單元晶胞中。在根據本發明 之其他具體例中，列選擇電晶體614可包括於電路晶圓616 上之該單元晶胞中。 現參看圖7，展示根據本發明之具體例中的可在具有兩個 半導體晶圓之影像感測器中實施的共用架構的示意圖。兩個 光偵測器700、702、兩個傳送閘704、706及一電荷至電壓 轉換區708(sw)裝設於感測器晶圓710上。在根據本發明之 具體例中’該兩個光偵測器700、702、兩個傳送閘704、706 及電荷至電壓轉換區708(sw)在感測器晶圓71〇上形成一例 不性单7〇晶胞。 電荷至電壓轉換區708(cw)、重設電晶體712、電位vDD 714、放大器716及列選擇電晶體718建構於電路晶圓 上。在根據本發明之具體例中，電荷至電壓轉換區708(sw)、 7〇8(cw)實施為浮動擴散區，且放大器716實施為源極追隨 器電晶體。列選擇電晶體718之—個源極成極電極連接至 放大器716之一源極/汲極電極，而另一個源極/汲極電極連 接至輸出線722。重設電晶體712及放大器716兩者之一個 源極/沒極電極維持於電位VDD714。電節點723將重設電晶 099146547 12 ⑧ 201143063 體712之另一個源極/汲極電極、放大器716之閘極及電荷 至電壓轉換區708(cw)連接到一起。 晶圓間互連724將感測器晶圓710上之電荷至電壓轉換區 708(sw)電連接至電路晶圓720上之電節點723。電容器726 表示晶圓間互連724與一屏蔽件（圖7中未示）之間的電容， 此情形將結合圖14更詳細地加以描述。 圖8為圖7中所展示之具體例的單元晶胞之俯視圖的圖形 說明。如早先所描述，每一光偵測器700、702回應於入射 光而收集電荷。傳送閘704、706選擇性地且分別地將收集 到之電荷自光偵測器700、702傳遞至共用之電荷至電壓轉 換區708(sw)。接觸點800電連接至晶圓間互連724。 圖9為根據本發明之具體例中的替代單元晶胞之俯視圖 的圖形說明。在圖9中所展示之具體例中，四個光偵測器 900、902、904、906共用一感測器晶圓上之一個電荷至電 壓轉換區908(sw)。傳送閘910、912、914、916選擇性地且 分別地將電荷自光偵測器900、902、904、906傳遞至共用 之電荷至電壓轉換區908(sw)。光偵測器900、902通常裝設 於一像素陣列中之像素的一列（或行）中，且光偵測器904、 906通常裝設於該像素陣列中之一相鄰列（或行）中。 接觸點918電連接至一晶圓間互連。該晶圓間互連將電荷 至電壓轉換區908(sw)電連接至一電路晶圓上之各別電節 點。在根據本發明之一或多個具體例中，該電節點可連接至 099146547 13 201143063 電荷至電壓轉換區或放大器。僅舉例而言，在根據本發明之 具體例中，該電路晶圓如同圖7中所展示之電路晶圓720 般組態。 現參看圖10,展示根據本發明之具體例中的具有兩個半 導體晶圓之第一影像感測器之一部分的簡化說明。感測器晶 圓1000包括多個單元晶胞1002。每一單元晶胞1002包括 至少一個光债測器及一電荷至電壓轉換區（未圖示）。 電路晶圓1004亦包括多個單元晶胞1006。在圖10之具 體例中，每一單元晶胞1006包括一電荷至電壓轉換區（未圖 示）。單元晶胞1002、1006被標記1、2、3及4且配置成列 及行。橢圓形指示在感測器晶圓及電路晶圓1000、1004上 存在更多單元晶胞1002、1006。 晶圓間互連1007將感測器晶圓1000上之每一電荷至電壓 轉換區電連接至電路晶圓1004上之一電節點。在圖10中所 展示之具體例中，該電節點連接至一電荷至電壓轉換區。在 根據本發明之另一具體例中，該電節點為一放大器之閘極， 如圖6中所描繪。 感測器晶圓及電路晶圓上的標記為「1」、「2」、「3」、「4」 之單元晶胞表示在先前技術之影像感測器中在該兩個晶圓 上本該處於相同列中的對應單元晶胞。根據本發明之具體例 使感測器晶圓1000上的單元晶胞1002之一部分的位置及電 路晶圓1004上之對應單元晶胞1006的位置相對於該等晶圓 099146547 14 ⑧ 201143063 上之其他單元晶胞而移位。在圖10之具體例令，感測器晶 圓1002上的每隔一行1〇08、1〇1〇之單元晶胞及電路晶圓 1004上之對應行〗012、10〗4中的單元晶胞之位置在箭頭 1016所指示之方向上移位。在根據本發明之具體例中，行 1008、1010、1〇12、〗014中之單元晶胞的位置移位達一列 光偵測器。根據本發明之其他具體例可使單元晶胞之位置以 任何方向、以任何距離、或以方向與距離兩者之組合來移 位。該距離可包括但不限於一列之分率、多個列，或其某組 合。 使感測器晶圓及電路晶圓兩者上之對應單元晶胞刪、 之。卩77的位置移位使互連間距增加，此情形現將參 看圖11加以描述。 圖11為根據本發明之具體例中的第-感測器晶圓之-部 分之俯視__朗。當每隔—行之單元晶财的單元晶 胞之位置上下移位達—列光^貞測器時，最小互連間距「〇」 可用數學方式表達成：S 099146547 201143063 The inter-wafer interconnect 620 connects the charge-to-voltage conversion region 604 on the sensor wafer 608 to the gate of the amplifier 612 on the circuit wafer 616. In a particular embodiment in accordance with the invention, the gate of amplifier 612 is considered to be an electrical node on circuit wafer 616. Further, in a specific example according to the present invention, the amplifier 612 is included in one of the unit cells on the circuit wafer 616. In other embodiments in accordance with the present invention, column select transistor 614 can be included in the unit cell on circuit wafer 616. Referring now to Figure 7, a schematic diagram of a common architecture that can be implemented in an image sensor having two semiconductor wafers in accordance with an embodiment of the present invention is shown. Two photodetectors 700, 702, two transfer gates 704, 706 and a charge-to-voltage conversion region 708 (sw) are mounted on the sensor wafer 710. In the specific example according to the present invention, the two photodetectors 700, 702, the two transfer gates 704, 706 and the charge-to-voltage conversion region 708 (sw) form an inaccuracy on the sensor wafer 71A. Single 7 〇 unit cell. Charge-to-voltage conversion region 708 (cw), reset transistor 712, potential vDD 714, amplifier 716, and column select transistor 718 are constructed on the circuit wafer. In a specific example in accordance with the invention, charge to voltage transition regions 708 (sw), 7 〇 8 (cw) are implemented as floating diffusion regions, and amplifier 716 is implemented as a source follower transistor. One source electrode of column select transistor 718 is coupled to one source/drain electrode of amplifier 716 and the other source/drain electrode is coupled to output line 722. One of the reset transistor 712 and the amplifier 716 is maintained at the potential VDD714. Electrical node 723 connects the other source/drain electrodes of transistor 712146547 12 8 201143063 body 712, the gate of amplifier 716, and the charge-to-voltage conversion region 708 (cw). The inter-wafer interconnect 724 electrically connects the charge-to-voltage conversion region 708 (sw) on the sensor wafer 710 to the electrical node 723 on the circuit wafer 720. Capacitor 726 represents the capacitance between inter-wafer interconnect 724 and a shield (not shown in Figure 7), which will be described in more detail in connection with Figure 14. Fig. 8 is a graphical illustration of a plan view of a unit cell of the specific example shown in Fig. 7. As described earlier, each photodetector 700, 702 collects charge in response to incident light. Transfer gates 704, 706 selectively and separately transfer the collected charge from photodetectors 700, 702 to a common charge-to-voltage conversion region 708 (sw). Contact point 800 is electrically coupled to inter-wafer interconnect 724. Figure 9 is a graphical illustration of a top view of an alternative unit cell in accordance with a specific example of the present invention. In the particular example shown in Figure 9, four photodetectors 900, 902, 904, 906 share a charge on a sensor wafer to voltage conversion region 908 (sw). Transfer gates 910, 912, 914, 916 selectively and separately transfer charge from photodetectors 900, 902, 904, 906 to a common charge-to-voltage conversion region 908 (sw). The photodetectors 900, 902 are typically mounted in a column (or row) of pixels in a pixel array, and the photodetectors 904, 906 are typically mounted in one adjacent column (or row) of the pixel array. in. Contact 918 is electrically connected to an inter-wafer interconnect. The inter-wafer interconnect electrically connects the charge-to-voltage conversion region 908 (sw) to respective electrical nodes on a circuit wafer. In one or more embodiments according to the present invention, the electrical node can be connected to a 099146547 13 201143063 charge-to-voltage conversion region or amplifier. By way of example only, in a particular embodiment in accordance with the invention, the circuit wafer is configured like the circuit wafer 720 shown in FIG. Referring now to Figure 10, there is shown a simplified illustration of a portion of a first image sensor having two semiconductor wafers in accordance with an embodiment of the present invention. The sensor wafer 1000 includes a plurality of unit cells 1002. Each unit cell 1002 includes at least one optical debt detector and a charge to voltage conversion region (not shown). Circuit wafer 1004 also includes a plurality of unit cells 1006. In the specific embodiment of Figure 10, each unit cell 1006 includes a charge-to-voltage conversion region (not shown). The unit cells 1002, 1006 are labeled 1, 2, 3, and 4 and are arranged in columns and rows. The ellipse indicates the presence of more unit cells 1002, 1006 on the sensor wafer and circuit wafers 1000, 1004. Inter-wafer interconnect 1007 electrically connects each charge-to-voltage conversion region on sensor wafer 1000 to one of the electrical nodes on circuit wafer 1004. In the particular example shown in Figure 10, the electrical node is coupled to a charge to voltage transition region. In another embodiment in accordance with the invention, the electrical node is a gate of an amplifier, as depicted in FIG. The unit cells labeled "1", "2", "3", and "4" on the sensor wafer and the circuit wafer represent the same on the two wafers in the prior art image sensor. The corresponding unit cells in the same column. The position of a portion of the unit cell 1002 on the sensor wafer 1000 and the position of the corresponding unit cell 1006 on the circuit wafer 1004 are relative to the other of the wafers 099146547 14 8 201143063, in accordance with an embodiment of the present invention. The unit cell is displaced. In the specific example of FIG. 10, the cell of every other row on the sensor wafer 1002, and the cell in the corresponding row 012, 10, 4 on the circuit wafer 1004. The position of the cell is shifted in the direction indicated by arrow 1016. In a specific example according to the present invention, the position of the unit cells in rows 1008, 1010, 1〇12, and 014 is shifted by a column of photodetectors. Other embodiments of the invention may position the unit cell in any direction, at any distance, or in a combination of both direction and distance. The distance may include, but is not limited to, a column of divisions, a plurality of columns, or a combination thereof. Corresponding cell cells on both the sensor wafer and the circuit wafer are deleted. The positional shift of 卩77 increases the interconnect pitch, which will now be described with reference to FIG. Figure 11 is a plan view of a portion of a first-sensor wafer in accordance with a specific example of the present invention. When the position of the unit cell of the unit cell is shifted up and down to the column light detector, the minimum interconnection pitch "〇" can be mathematically expressed as:

CC

-TO 4 -」為兩個列相鄰(在同-行中)之晶圓間互連之間 的距離，X「a」為兩個行相鄰(在同一列中)之互連之間的 垂直於「b」的輯。當b=a時，互㈣縣-財向（水平 方向)上自3增加至Ul8a，增加達12%。在垂直方向上， 099146547 15 5 201143063 互連間距為a。使互連間距在水平方向上增加可使影像感測 器之製造程序較可靠。 表1針對在l.〇a至2.〇a之範圍中的b值以百分比形式列 出當每隔一行之單元晶胞上下移位達一列光偵測器時的最 小互連間距。 [表1] b(a為單元） sqrt(aA2+bA2/4) (a為單元） 間距增加％ 1 1.118033989 12 1.1 1.141271221 14 1.2 1.166190379 17 1.3 1.192686044 19 1.4 1.220655562 22 1.5 1.25 25 1.6 1.280624847 28 1.7 1.312440475 31 1.8 1.345362405 35 1.9 1.379311422 38 2 1.414213562 41 圖11中之每一單元晶胞1100包括兩個光偵測器1102、 1104、兩個傳送閘1106、1108及由該兩個光偵測器1102、 1104共用之一個電荷至電壓轉換區m〇。接觸點m2電連 接至晶圓間互連1114(由虛線表示）。 圖12為根據本發明之具體例中的第二感測器晶圓之一部 分之俯視圖的圖形說明。圖12中之每一單元晶胞1200包括 四個光偵測器1202、1204' 1206、1208、四個傳送閘1210、 1212、1214、1216 及由該四個光偵測器 1202、1204、1206、 1208共用之一個電荷至電壓轉換區1218。接觸點1220電連 099146547 16 ⑧ 201143063 接至晶圓間互連1222(由虛線表示）。當交替行之單元晶胞中 的單元晶胞之位置向上移位達一列光偵測器時，表1中之值 適用於圖12中所展示之具體例。 現參看圖13 ’展示根據本發明之具體例中的沿圖12中之 線B-B的橫剖面圖。感測器晶圓13〇〇包括光偵測器12〇2、 1204、1206、1208、傳送閘1214、1216及電荷至電壓轉換 區1218。彩色濾光器陣列（CFA)13〇2及微透鏡13〇4裝設於 感測器晶圓1300之表面上。在根據本發明之具體例中，一 黑色彩色濾光器元件13〇5(在CFA 1302中）可裝設於電荷至 電壓轉換區1218上方。 電路晶圓1306包括電荷至電壓轉換區π〇8、重設電晶體 之閘極1310、電位VDD 1312、一放大器之一閘極1314， 及該放大器之輸出端1316。在圖13中所展示之具體例中， 晶圓間互連1222將感測器晶圓1300上之電荷至電壓轉換區 1218電連接至電路晶圓1306上之電荷至電壓轉換區1308。 晶圓間互連1222以裝設於金屬層Ml至M10之間的導電區 段來構成。金屬層]y[8及M9形成裝設於感測器晶圓1300 與電路晶圓1306之間的界面處之晶圓至晶圓電互連。 圖14為根據本發明之具體例中的沿圖11中之線C-C的 橫剖面圖。感測器晶圓1400包括光偵測器1102、1104、傳 送閘1106、1108及電荷至電壓轉換區mo。電路晶圓14〇2 包括電荷至電壓轉換區14〇4、重設電晶體之閘極14〇6、電 099146547 5 17 201143063 位VDD 1408、-放大器之閘極141〇，及該放大器之輸出端 1412。在圖14中所展示之具體例中，晶圓間互連1114將感 測器晶圓1400上之電荷至電壓轉換區111〇電連接至電路晶 圓1402上之電荷至電壓轉換區14〇4。 晶圓間互連1114由可任選金屬屏蔽件1414環繞。金屬屏 蔽件1414由每一金屬層中之金屬區段組成。金屬屏蔽件 1414經由電連接器1416而電連接至放大器之輸出端1412。 將金屬屏蔽件1414連接至輸出端1412使電荷至電壓轉換區 1404之有效電容減小。另外，金屬屏蔽件1414使晶圓間互 連1114之相鄰導線之間的電容性耦合減小，此情形減小電 串擾。 現參看圖15，展示根據本發明之具體例中的具有兩個半 導體晶圓之第二影像感測器之一部分的簡化說明。感測器晶 圓1500包括多個單元晶胞1502。在根據本發明之具體例 中，每一單元晶胞1502包括至少一個光偵測器及一電荷至 電壓轉換區（未圖示）。 電路晶圓1504亦包括多個單元晶胞1506。橢圓形指示在 感測器晶圓及電路晶圓1500、1504上分別存在更多單元晶 胞1502、1506。晶圓間互連1507將感測器晶圓上之每一電 荷至電壓轉換區電連接至電路晶圓上之一電節點。舉例而 言，該電節點可連接至電荷至電壓轉換區（如圖5及圖7中 所展示）或連接至放大器之閘極(如圖6中所描繪）。 099146547 18 201143063 在根據本發明之一個具體例中，晶圓間互連1507之至少 -部分的位置相對於連接至經移位之晶圓間互連之感測器 晶圓或電路晶圓上的―組件而移位或震設於不同位置處。在 根據本發明之另一個具體例中’晶圓間互連1507之至少一 部分的位置相對於連接至經移狀晶圓間互連之兩個晶圓 上的組件而移位或裝設於不同位置處。—個或兩個晶圓上之 單元晶胞可能或可能不相對於彼此㈣位，或相對於同一晶 圓上之其他單元晶胞而移位。使晶圓間互連之至少一部分的 位置移位可增加互制距，此情形現將參看圖16來加以描 述0 圖^為根據本發明之具體例中的具有經移位之互連的第 感測器曰曰圓之一部分之俯視圖的圖形說明。晶圓間互連 〇 1602以虛線來描繪於其各別經移位之位置處。箭頭 1604表不針對晶圓間互連_之位置的移位方向，而箭頭 祕表示針姆晶圓間互連職之位置的移位方向。 在圖16中’距離「d」為兩個行相鄰(在同一列中）之晶圓 門互連1600、16〇2之間的沿X軸之距離。距離「❺」為兩個 J才鄰(在同—行中）之晶圓間互連160G之間的沿y軸之距 離0距離「f 关 v 」為一個晶圓間互連1600與接觸點1608之間 的距離。該兩個行相鄰之晶圓間互連“⑻、⑽2之間的最 小互連間距Dl賴學方式表達成：-TO 4 -" is the distance between the inter-wafer interconnections of two columns adjacent (in the same-row), X "a" is the interconnection between two rows adjacent (in the same column) Vertical to the series of "b". When b=a, the mutual (four) county-financial (horizontal direction) increased from 3 to Ul8a, increasing by 12%. In the vertical direction, 099146547 15 5 201143063 The interconnection pitch is a. Increasing the interconnect pitch in the horizontal direction makes the image sensor manufacturing process more reliable. Table 1 lists, in percentages, the minimum interconnect spacing when cell elements of every other row are shifted up and down by a column of photodetectors for b values in the range of l.〇a to 2.〇a. [Table 1] b (a is a unit) sqrt(aA2+bA2/4) (a is a unit) Pitch increase % 1 1.118033989 12 1.1 1.141271221 14 1.2 1.166190379 17 1.3 1.192686044 19 1.4 1.220655562 22 1.5 1.25 25 1.6 1.280624847 28 1.7 1.312440475 31 1.8 1.345362405 35 1.9 1.379311422 38 2 1.414213562 41 Each unit cell 1100 in Figure 11 includes two photodetectors 1102, 1104, two transfer gates 1106, 1108, and is shared by the two photodetectors 1102, 1104. One charge to voltage conversion region m〇. Contact point m2 is electrically coupled to inter-wafer interconnect 1114 (shown by dashed lines). Figure 12 is a graphical illustration of a top view of a portion of a second sensor wafer in accordance with a particular embodiment of the present invention. Each unit cell 1200 in FIG. 12 includes four photodetectors 1202, 1204' 1206, 1208, four transfer gates 1210, 1212, 1214, 1216 and by the four photodetectors 1202, 1204, 1206 And 1208 shares a charge to voltage conversion region 1218. Contact 1220 is connected to 099146547 16 8 201143063 to inter-wafer interconnect 1222 (indicated by the dashed line). The values in Table 1 apply to the specific example shown in Fig. 12 when the positions of the unit cell in the unit cell of the alternate row are shifted upward by a column of photodetectors. Referring now to Figure 13', a cross-sectional view taken along line B-B of Figure 12 in a specific example of the present invention is shown. The sensor wafer 13A includes photodetectors 12A2, 1204, 1206, 1208, transfer gates 1214, 1216, and a charge-to-voltage conversion region 1218. A color filter array (CFA) 13〇2 and a microlens 13〇4 are mounted on the surface of the sensor wafer 1300. In a particular embodiment in accordance with the invention, a black color filter element 13 〇 5 (in CFA 1302) can be mounted over charge to voltage transition region 1218. The circuit wafer 1306 includes a charge-to-voltage conversion region π8, a gate 1310 of the reset transistor, a potential VDD 1312, a gate 1314 of an amplifier, and an output 1316 of the amplifier. In the particular example shown in FIG. 13, inter-wafer interconnect 1222 electrically connects the charge-to-voltage conversion region 1218 on sensor wafer 1300 to the charge on circuit wafer 1306 to voltage conversion region 1308. The inter-wafer interconnects 1222 are formed by conductive regions disposed between the metal layers M1 to M10. The metal layers]y[8 and M9 form a wafer-to-wafer electrical interconnection at the interface between the sensor wafer 1300 and the circuit wafer 1306. Figure 14 is a cross-sectional view taken along line C-C of Figure 11 in a specific example of the present invention. The sensor wafer 1400 includes photodetectors 1102, 1104, transfer gates 1106, 1108, and a charge to voltage transition region mo. The circuit wafer 14〇2 includes a charge-to-voltage conversion region 14〇4, a reset transistor gate 14〇6, an electric 099146547 5 17 201143063 bit VDD 1408, an amplifier gate 141〇, and an output of the amplifier. 1412. In the specific example shown in FIG. 14, the inter-wafer interconnect 1114 electrically connects the charge-to-voltage conversion region 111 on the sensor wafer 1400 to the charge on the circuit wafer 1402 to the voltage conversion region 14〇4. . The inter-wafer interconnect 1114 is surrounded by an optional metal shield 1414. Metal shield 1414 is comprised of metal segments in each metal layer. Metal shield 1414 is electrically coupled to output 1414 of the amplifier via electrical connector 1416. Connecting metal shield 1414 to output 1412 reduces the effective capacitance of charge to voltage transition region 1404. In addition, the metal shield 1414 reduces the capacitive coupling between adjacent wires of the inter-wafer interconnect 1114, which reduces electrical crosstalk. Referring now to Figure 15, a simplified illustration of a portion of a second image sensor having two semiconductor wafers in accordance with a particular embodiment of the present invention is shown. The sensor crystal 1500 includes a plurality of unit cells 1502. In a particular embodiment in accordance with the invention, each unit cell 1502 includes at least one photodetector and a charge to voltage transition region (not shown). Circuit wafer 1504 also includes a plurality of unit cells 1506. The ellipse indicates that there are more cell cells 1502, 1506 on the sensor wafer and circuit wafers 1500, 1504, respectively. Inter-wafer interconnect 1507 electrically connects each charge-to-voltage conversion region on the sensor wafer to one of the electrical nodes on the circuit wafer. For example, the electrical node can be connected to a charge-to-voltage conversion region (as shown in Figures 5 and 7) or to a gate of an amplifier (as depicted in Figure 6). 099146547 18 201143063 In one embodiment of the invention, at least a portion of the inter-wafer interconnect 1507 is positioned relative to a sensor wafer or circuit wafer connected to the inter-displaced inter-wafer interconnect ―The components are shifted or shaken at different positions. In another embodiment of the present invention, the position of at least a portion of the inter-wafer interconnect 1507 is shifted or mounted differently than the components on the two wafers connected to the inter-transmissive inter-wafer interconnect. Location. The unit cells on one or both wafers may or may not be displaced relative to each other (four) bits, or relative to other unit cells on the same crystal. Displacement of at least a portion of the inter-wafer interconnect may increase the inter-modulation distance, which will now be described with reference to Figure 16 which is a cross-connected interconnect in accordance with a specific example of the present invention. A graphical illustration of a top view of a portion of the sensor's circle. Inter-wafer interconnects 602 1602 are depicted in dashed lines at their respective shifted positions. Arrow 1604 indicates the direction of displacement for the position of the inter-wafer interconnect, and the arrow indicates the direction of shifting of the position between the inter-wafer interconnects. In Fig. 16, the 'distance 'd' is the distance along the X-axis between the wafer gate interconnections 1600, 16〇2 adjacent to each other (in the same column). The distance "❺" is the distance between the inter-wafer interconnections 160G between the two J-neighbors (in the same line) along the y-axis. The distance "f off v" is an inter-wafer interconnection 1600 and the contact point. The distance between 1608. The inter-wafer interconnection between the two rows "the minimum interconnection spacing between (8) and (10) 2 is expressed as:

Dl = ^d2+4f2 099146547 201143063 同一行中之兩個晶圓間互連16〇〇之間的最小互連間距 D2用數學方式表達成： D2 = yfd2 + (e^2/j^ 在圖16中所展示之具體例中，所有晶圓間互連ι6〇〇、ΐ6〇2 移位至兩個絲卿之間的位置。根據本發明之其他具體例 可使晶圓間互連之一部分的位置相對於一個晶圓上之一組 件而移位，或使晶圓間互連之-部分的位置相對於兩個晶圓 上之多個組件而移位。圖17_18說明根據本發明之具體例中 的具有經移位之互連位置的感測器晶圓之替代俯視圖。 在圖17中’晶圓間互連1700之位置並不移位，而晶圓間 互連1702之位置相對於感測器晶圓上之相鄰單元晶胞17〇4 而移位。一導電層1706將晶圓間互連1〇72電連接至各別接 觸點1708。在圖17中，移位每隔一行中之晶圓間互連之位 置。其他具體例可使晶圓間互連之位置的一部分不同地移 位。僅舉例而言，可移位每隔一列中之晶圓間互連的位置。 圖中所展示之具體例使晶圓間互連之位置全部移位， 其中一部分1800之位置在一個方向上移位且另一部分18〇2 之位置在相反方向上移位。一導電層1804將晶圓間互連 1800、1802電連接至各別接觸點1806。在圖ι8中，晶圓間 互連之位置移位達等於一光偵測器1808之長度的一半之距 離。其他具體例可使晶圓間互連之位置不同地移位。 現參看圖19,展示根據本發明之具體例中的沿圖Η中之 099146547 201143063 線D-D的影像感測器之橫剖面圖。感測器晶圓1900包括光 偵測器1808、傳送閘1902及電荷至電壓轉換區1904。導電 層1804將電荷至電壓轉換區1904電連接至晶圓間互連 1800之各別末端。在根據本發明之具體例中，導電層1804 以一額外金屬層形成。 一晶圓至晶圓電互連1906裝設於感測器晶圓1900與電路 晶圓1910之間的界面1908處。在根據本發明之具體例中， 晶圓間互連1800將感測器晶圓1900上之電荷至電壓轉換區 1904電連接至電路晶圓1910上之電荷至電壓轉換區1912。 如圖19中所展示，晶圓間互連1800之位置相對於感測器晶 圓及電路晶圓上之對應單元晶胞而移位或裝設於不同位置 處。在所說明之具體例中，晶圓間互連18〇〇之位置相對於 連接至晶圓間互連1800之一個組件而移位或裝設於不同位 置處。晶圓間互連1800相對於感測器晶圓19〇〇上之電荷至 電壓轉換區1904之位置而移位或裝設於不同位置處。晶圓 間互連1800並不追隨感測器晶圓19〇〇上之電荷至電壓轉換 區1904與電路晶圓1910上之電荷至電壓轉換區19i2之間 的直線。 圖19描繪感測器晶圓19〇〇上之電荷至電壓轉換區19〇4 與晶圓間互連1800之間的導電層18〇4。在根據本發明之另 一具體例中，晶圓間互連18〇〇相對於電路晶圓191〇上之電 荷至電壓轉換區1912之位置而移位或裝設於不同位置處。Dl = ^d2+4f2 099146547 201143063 The minimum interconnection spacing D2 between the two inter-wafer interconnections 16 同一 in the same row is mathematically expressed as: D2 = yfd2 + (e^2/j^ in Figure 16 In the specific example shown in the example, all inter-wafer interconnections ι6〇〇, ΐ6〇2 are shifted to positions between the two filaments. According to other embodiments of the present invention, one of the inter-wafer interconnections may be The position is displaced relative to one of the components on one wafer, or the position of the inter-wafer interconnection is displaced relative to the plurality of components on the two wafers. Figures 17-18 illustrate a specific example in accordance with the present invention. An alternative top view of the sensor wafer with shifted interconnect locations. In Figure 17, the location of the inter-wafer interconnect 1700 is not shifted, and the position of the inter-wafer interconnect 1702 is relative to the sense The adjacent cell cells 17〇4 on the detector wafer are shifted. A conductive layer 1706 electrically connects the inter-wafer interconnects 1 to 72 to the respective contact points 1708. In Figure 17, shifts every other row. The location of the inter-wafer interconnects. Other embodiments may shift a portion of the location of the inter-wafer interconnects differently. For example, Shift the position of the inter-wafer interconnections in every other column. The specific example shown in the figure shifts the positions of the inter-wafer interconnections, wherein the position of one portion 1800 is shifted in one direction and the other portion is 18〇 The position of 2 is shifted in the opposite direction. A conductive layer 1804 electrically connects the inter-wafer interconnects 1800, 1802 to the respective contact points 1806. In Figure ι8, the positional shift of the inter-wafer interconnect is equal to one light. The distance of the detector 1808 is half the distance. Other embodiments may shift the position of the inter-wafer interconnection differently. Referring now to Figure 19, the line 099146547 201143063 along the figure in the specific example of the present invention is shown. A cross-sectional view of the image sensor of DD. The sensor wafer 1900 includes a photodetector 1808, a transfer gate 1902, and a charge-to-voltage conversion region 1904. The conductive layer 1804 electrically connects the charge-to-voltage conversion region 1904 to the wafer. The respective ends of the interconnects 1800. In a specific example in accordance with the invention, the conductive layer 1804 is formed as an additional metal layer. A wafer-to-wafer electrical interconnect 1906 is mounted on the sensor wafer 1900 and the circuit crystal At interface 1908 between circles 1910. In accordance with this In a specific example, the inter-wafer interconnect 1800 electrically connects the charge-to-voltage conversion region 1904 on the sensor wafer 1900 to the charge on the circuit wafer 1910 to the voltage conversion region 1912. As shown in Figure 19, the crystal The position of the inter-circle interconnect 1800 is displaced or mounted at different locations relative to the corresponding cell cells on the sensor wafer and the circuit wafer. In the illustrated example, the inter-wafer interconnect 18 turns The position of the crucible is displaced or mounted at a different location relative to a component connected to the inter-wafer interconnect 1800. The inter-wafer interconnect 1800 is displaced or mounted at different locations relative to the location of the charge on the sensor wafer 19A to the voltage conversion region 1904. The inter-wafer interconnect 1800 does not follow the charge on the sensor wafer 19 to the line between the voltage conversion region 1904 and the charge on the circuit wafer 1910 to the voltage conversion region 19i2. FIG. 19 depicts the conductive layer 18〇4 between the charge on the sensor wafer 19A and the voltage conversion region 19〇4 and the inter-wafer interconnect 1800. In another embodiment in accordance with the present invention, the inter-wafer interconnect 18 is displaced or mounted at a different location relative to the location of the charge on the circuit wafer 191 to the voltage transition region 1912.

099146547 01 S 201143063 導電層1804因此將電荷至電壓轉換區1912電連接至晶圓間 互連1800。 另外，在根據本發明之又一具體例中，晶圓間互連18〇〇 可將感測器晶圓1900上之電荷至電壓轉換區19〇4連接至一 放大器之一閘極。導電層18〇4可用以將感測器晶圓19〇〇 上之電荷至電壓轉換區1904連接至晶圓間互連18〇〇或用以 將電路晶圓1910上之該放大器之該閘極連接至晶圓間互連 1800。 圖20為根據本發明之具體例中的沿圖18中之線D_D的 替代影像感測器之橫剖面圖。感測器晶圓2〇〇〇包括光偵測 器1808、傳送閘2002及電荷至電壓轉換區2〇〇4。導電層 1804將電荷至電壓轉換區2004電連接至晶圓間互連1800 之各別末端。 一晶圓至晶圓電互連2006裝設於感測器晶圓2000與電路 晶圓2010之間的界面2008處。在根據本發明之具體例中， 導電層2012將晶圓間互連18〇〇電連接至各別電荷至電壓轉 換區2014。在根據本發明之具體例中，導電層及2012 各自以一額外金屬層形成。 如圖20中所展示，晶圓間互連1800之位置相對於連接至 經移位之晶圓間互連18〇〇之兩個組件而移位或裝設於不同 位置處。在所說明之具體例中，晶圓間互連18〇〇之位置相 對於感測器晶圓2000上之電荷至電壓轉換區2004的位置且 099146547 22 ⑧ 201143063 相對於電路晶圓2010上之電荷至電壓轉換區2014的位置而 移位或裝設於不同位置處。晶圓間互連18〇〇並不追隨感測 器晶圓2000上之電荷至電壓轉換區2〇〇4與電路晶圓2〇1〇 上之電荷至電壓轉換區2014之間的直線。 或者’在根據本發明之其他具體例中，晶圓間互連1800 可將感測器晶圓2000上之電荷至電壓轉換區2004連接至電 路晶圓2010上的一放大器之一閘極。導電層18〇4、2〇12 可分別用以將晶圓間互連1800電連接至電荷至電壓轉換區 2004且連接至電路晶圓2010上的該放大器之該閘極。 【圖式簡單說明】 參看以下圖式來更好地理解本發明之具體例。該等圖式之 元件未必相對於彼此按比例繪製。 圖1為根據先前技術之具有兩個半導體晶圓之影像感測 器的橫剖面圖； 圖2為圖1中所展示之感測器晶圓100之一部分的俯視圖 之圖形說明； 圖3為根據本發明之具體例中的影像擷取裝置之簡化方 塊圖； 圖4為根據本發明之具體例中的影像感測器之俯視圖的 方塊圖； 圖5為根據本發明之可在具有兩個半導體晶圓之影像感 測器中實施的第-像素架構的示意圖； 099146547 201143063 圖6為根據本發明之可在具有兩個半導體晶圓之影像感 測器中實_第〜像素架構的示意圖； 圖7為根據本發明之可在具有兩個半導體晶圓之影像感 測器中實施的共用架構的示意圖； 圖8為圖6中所展示之具體例的單元晶胞之俯視圖的圖形 說明； 圖9為根據本發明之具體例中的替代單元晶胞之俯視圖 的圖形說明； 圖1〇為根據本發明之具體例中的具有兩個半導體晶圓之 第一影像感測器之一部分的簡化擴大說明； 圖11為根據本發明之具體例中的第一感測器晶圓之一部 分之俯視圖的圖形說明； 圖12為根據本發明之具體例中的第二感測器晶圓之一部 分之俯視圖的圖形說明； 圖13為根據本發明之具體例中的沿圖12中之線Β·Β的 橫剖面圖； 圖Μ為根據本發明之具體例中的沿圖u中之線c_c的 橫剖面圖； 圖15為根據本發明之具體例中的具有兩個半導體晶圓之 第二影像感測器之一部分的簡化擴大說明； 圖16為根據本發明之具體例中的具有經移位之互連的第 一感測器晶圓之一部分之俯視圖的圖形說明； 099146547 24 ⑧ 201143063 圖17為根據本發明之具體例中的具有經移位之互連的第 一感測器晶圓之一部分之俯視圖的圖形說明； 圖18為根據本發明之具體例中的具有經移位之互連的第 二感測器晶圓之俯視圖； 圖19為根據本發明之具體例中的沿圖18中之線D-D的 影像感測器之橫剖面圖；及 圖20為根據本發明之具體例中的沿圖18中之線D-D的 替代影像感測器之橫剖面圖。 【主要元件符號說明】 100 感測益晶圓 102 光偵測器 104 光4貞測器 106(sw) 電荷至電壓轉換區 106(cw) 電荷至電壓轉換區 108 傳送閘 110 傳送閘 112 電路晶圓 114 晶圓間互連 200 早元晶胞 202 光偵測器 204 光偵測器 208 傳送閘 099146547 25 201143063 210 傳送閘 300 影像擷取裝置 302 光 304 成像級 306 影像感測器 308 處理器 310 記憶體 312 顯示器 314 其他輸入/輸出 400 像素 402 像素陣列 404 行解碼器 406 列解碼器 408 數位邏輯 410 類比或數位輸出電路 412 時序產生器 500 光偵測器 502 傳送閘 504(sw) 感測器晶圓上之電荷至電壓轉換區 504(cw) 電路晶圓上之電荷至電壓轉換區 506 感測盗晶圓 508 重設電晶體 099146547 26 ⑧ 201143063 510 電位 512 放大器 514 列選擇電晶體 516 電路晶圓 518 輸出線 519 電節點 520 晶圓間互連 600 光偵測器 602 傳送閘 604 電荷至電壓轉換區 606 重設電晶體 608 感測β晶圓 610 電位 612 放大器 614 列選擇電晶體 616 電路晶圓 618 輸出線 620 晶圓間互連 700 光偵測器 702 光偵測器 704 傳送閘 706 傳送閘 099146547 27 201143063 708(sw) 感測器晶圓上之電荷至電壓轉換區 708(cw) 電路晶圓上之電荷至電壓轉換區 710 感測益晶圓 712 重設電晶體 714 電位 716 放大器 718 列選擇電晶體 720 電路晶圓 722 輸出線 723 電節點 724 晶圓間互連 726 電容 800 接觸點 900 光偵測器 902 光偵測器 904 光偵測器 906 光偵測器 908(sw) 感測器晶圓上之電荷至電壓轉換區 910 傳送閘 912 傳送閘 914 傳送閘 916 傳送閘 099146547 28 201143063 918 接觸點 1000 感測益晶圓 1002 單元晶胞 1004 電路晶圓 1006 早元晶胞 1007 晶圓間互連 1008 早元晶胞之行 1010 早元晶胞之行 1012 單元晶胞之行 1014 單元晶胞之行 1016 表示移位方向之箭頭 1100 早元晶胞 1102 光Y貞測器 1104 光偵測器 1106 傳送閘 1108 傳送閘 1110 電荷至電壓轉換區 1112 接觸點 1114 晶圓間互連 1200 早元晶胞 1202 光偵測器 1204 光偵測器 099146547 29 201143063 1206 光偵測器 1208 光偵測器 1210 傳送閘 1212 傳送閘 1214 傳送閘 1216 傳送閘 1218 電荷至電壓轉換區 1220 接觸點 1222 晶圓間互連 1300 感測斋晶圓 1302 彩色濾光器陣列 1304 微透鏡 1305 黑色彩色濾光器元件 1306 電路晶圓 1308 電荷至電壓轉換區 1310 重設電晶體之閘極 1312 電位 1314 放大器之閘極 1316 放大器之輸出端 1400 感測晶圓 1402 電路晶圓 1404 電荷至電壓轉換區 099146547 30 201143063 1406 重設電晶體之閘極 1408 電位 1410 放大器之閘極 1412 放大器之輸出端 1414 金屬屏蔽件 1416 電連接器 1500 感測器晶圓 1502 單元晶胞 1504 電路晶圓 1506 單元晶胞 1507 晶圓間互連 1600 晶圓間互連 1602 晶圓間互連 1604 表示移位方向之箭頭 1606 表示移位方向之箭頭 1700 晶圓間互連 1702 晶圓間互連 1704 單元晶胞 1706 導電層 1708 接觸點 1800 晶圓間互連 1802 晶圓間互連 099146547 31 導電層 接觸點 光偵測器 感測器晶圓 傳送閘 電荷至電壓轉換區 晶圓至晶圓電互連 感測盗晶圓與電路晶圓之間的界面 電路晶圓 電荷至電壓轉換區 感測器晶圓 傳送閘 電荷至電壓轉換區 晶圓至晶圓電互連 感測器晶圓與電路晶圓之間的界面 電路晶圓 導電層 電荷至電壓轉換區 兩個相鄰之晶圓間互連之間的距離 兩個相鄰之晶圓間互連之間的距離 互連間距 兩個相鄰之晶圓間互連之間的距離 32 201143063 e 兩個相鄰之晶圓間互連之間的距離 f 晶圓間互連與接觸點之間的距離 D1 互連間距 D2 互連間距 Ml 金屬層 M2 金屬層 M3 金屬層 M4 金屬層 M5 金屬層 M6 金屬層 M7 金屬層 M8 金屬層 M9 金屬層 M10 金屬層099146547 01 S 201143063 Conductive layer 1804 thus electrically connects charge-to-voltage conversion region 1912 to inter-wafer interconnect 1800. Additionally, in yet another embodiment in accordance with the present invention, the inter-wafer interconnect 18A can connect the charge-to-voltage conversion region 19〇4 on the sensor wafer 1900 to one of the gates of an amplifier. The conductive layer 18〇4 can be used to connect the charge-to-wafer via 1904 on the sensor wafer 19 to the inter-wafer interconnect 18 or to the gate of the amplifier on the circuit wafer 1910. Connected to the inter-wafer interconnect 1800. Figure 20 is a cross-sectional view of an alternative image sensor taken along line D_D of Figure 18 in accordance with a specific example of the present invention. The sensor wafer 2 includes a photodetector 1808, a transfer gate 2002, and a charge-to-voltage conversion region 2〇〇4. Conductive layer 1804 electrically connects charge-to-voltage conversion region 2004 to respective ends of inter-wafer interconnect 1800. A wafer-to-wafer electrical interconnect 2006 is installed at interface 2008 between the sensor wafer 2000 and the circuit wafer 2010. In a specific example in accordance with the present invention, conductive layer 2012 electrically connects inter-wafer interconnects 18A to respective charge-to-voltage conversion regions 2014. In a specific example according to the invention, the electrically conductive layer and 2012 are each formed as an additional metal layer. As shown in Figure 20, the position of the inter-wafer interconnect 1800 is displaced or mounted at a different location relative to the two components connected to the displaced inter-wafer interconnect 18A. In the illustrated embodiment, the position of the inter-wafer interconnect 18 is relative to the charge on the sensor wafer 2000 to the location of the voltage conversion region 2004 and 099146547 22 8 201143063 relative to the charge on the circuit wafer 2010 It is displaced or mounted at different positions to the position of the voltage conversion region 2014. The inter-wafer interconnect 18 does not follow the line between the charge on the sensor wafer 2000 to the voltage conversion region 2〇〇4 and the charge on the circuit wafer 2〇1〇 to the voltage conversion region 2014. Alternatively, in other embodiments in accordance with the present invention, the inter-wafer interconnect 1800 can connect the charge-to-voltage conversion region 2004 on the sensor wafer 2000 to one of the gates of an amplifier on the circuit wafer 2010. Conductive layers 18〇4, 2〇12 can be used to electrically connect inter-wafer interconnect 1800 to charge-to-voltage conversion region 2004 and to the gate of the amplifier on circuit wafer 2010, respectively. BRIEF DESCRIPTION OF THE DRAWINGS A specific example of the present invention will be better understood by referring to the following drawings. Elements of the drawings are not necessarily drawn to scale relative to each other. 1 is a cross-sectional view of an image sensor having two semiconductor wafers according to the prior art; FIG. 2 is a pictorial illustration of a top view of a portion of the sensor wafer 100 shown in FIG. 1. FIG. FIG. 4 is a block diagram of a top view of an image sensor in a specific example of the present invention; FIG. 5 is a block diagram of a semiconductor sensor according to the present invention; Schematic diagram of a first-pixel architecture implemented in an image sensor of a wafer; 099146547 201143063 FIG. 6 is a schematic diagram of a real-to-pixel architecture in an image sensor having two semiconductor wafers in accordance with the present invention; 7 is a schematic diagram of a common architecture that can be implemented in an image sensor having two semiconductor wafers according to the present invention; FIG. 8 is a graphical illustration of a top view of a unit cell of the specific example shown in FIG. 6; Is a schematic illustration of a top view of an alternative unit cell in accordance with a specific example of the present invention; FIG. 1A is a portion of a first image sensor having two semiconductor wafers in accordance with a specific example of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 11 is a pictorial illustration of a top view of a portion of a first sensor wafer in accordance with a specific example of the present invention; FIG. 12 is a second sensor wafer in accordance with a specific example of the present invention. FIG. 13 is a cross-sectional view along line Β·Β in FIG. 12 in a specific example of the present invention; FIG. 13 is a line c_c along the line u in the specific example according to the present invention. FIG. 15 is a simplified enlarged illustration of a portion of a second image sensor having two semiconductor wafers in accordance with a specific example of the present invention; FIG. 16 is a shift in a specific example according to the present invention. Graphical illustration of a top view of a portion of a first sensor wafer interconnected; 099146547 24 8 201143063 FIG. 17 is a first sensor wafer with shifted interconnects in accordance with a specific example of the present invention FIG. 18 is a plan view of a second sensor wafer having a shifted interconnect in accordance with a specific example of the present invention; FIG. 19 is a cross-sectional view of a specific example according to the present invention. 18 in the line DD shadow Cross-sectional view of the sensor; and FIG. 20 is a cross section through an alternative specific embodiment of the image in the present invention taken along line D-D in FIG. 18 of the sensor of FIG. [Main component symbol description] 100 Sense wafer 104 Photodetector 104 Light 4 Detector 106 (sw) Charge to voltage conversion region 106 (cw) Charge to voltage conversion region 108 Transfer gate 110 Transfer gate 112 Circuit crystal Circle 114 Inter-wafer Interconnect 200 Early Element Cell 202 Light Detector 204 Photo Detector 208 Transfer Gate 099146547 25 201143063 210 Transfer Gate 300 Image Capture Device 302 Light 304 Imaging Stage 306 Image Sensor 308 Processor 310 Memory 312 Display 314 Other Input/Output 400 Pixels 402 Pixel Array 404 Row Decoder 406 Column Decoder 408 Digital Logic 410 Analog or Digital Output Circuit 412 Timing Generator 500 Photodetector 502 Transfer Gate 504 (sw) Sensor Charge on the wafer to voltage conversion region 504 (cw) charge on the circuit wafer to voltage conversion region 506 sensing the stolen wafer 508 reset transistor 099146547 26 8 201143063 510 potential 512 amplifier 514 column selection transistor 516 circuit crystal Circle 518 Output Line 519 Electrical Node 520 Inter-wafer Interconnect 600 Photo Detector 602 Transfer Gate 604 Charge to Voltage Conversion Zone 606 reset transistor 608 sense beta wafer 610 potential 612 amplifier 614 column select transistor 616 circuit wafer 618 output line 620 inter-wafer interconnect 700 photodetector 702 photodetector 704 transfer gate 706 transfer gate 099146547 27 201143063 708(sw) Charge-to-voltage conversion region 708 on the sensor wafer (cw) Charge-to-voltage conversion region 710 on the circuit wafer Sense wafer 712 Reset transistor 714 Potential 716 Amplifier 718 Column selection Transistor 720 Circuit Wafer 722 Output Line 723 Electrical Node 724 Inter Wafer Interconnect 726 Capacitor 800 Contact Point 900 Light Detector 902 Light Detector 904 Light Detector 906 Light Detector 908 (sw) Sensor Charge-to-voltage conversion region on the wafer 910 Transfer gate 912 Transfer gate 914 Transfer gate 916 Transfer gate 099146547 28 201143063 918 Contact point 1000 Sensing wafer 1002 Unit cell 1004 Circuit wafer 1006 Early unit cell 1007 Wafer room Interconnect 1008 Early Element Cell Line 1010 Early Element Cell Line 1012 Unit Cell Line 1014 Unit Cell Line 1016 Indicates Shift Direction Arrow 1100 Early Cell 1102 Light Y Detector 1104 Light Detector 1106 Transfer Gate 1108 Transfer Gate 1110 Charge to Voltage Conversion Zone 1112 Contact Point 1114 Inter Wafer Interconnect 1200 Early Element Cell 1202 Light Detector 1204 Light Detector 099146547 29 201143063 1206 Photodetector 1208 Photodetector 1210 Transmitter 1212 Transmitter 1214 Transmitter 1216 Transmitter 1218 Charge to Voltage Conversion Zone 1220 Contact Point 1222 Inter Wafer Interconnect 1300 Sensing Fastener 1302 Color Filter Array 1304 microlens 1305 black color filter component 1306 circuit wafer 1308 charge to voltage conversion region 1310 reset transistor gate 1312 potential 1314 amplifier gate 1316 amplifier output 1400 sense wafer 1402 circuit wafer 1404 Charge-to-voltage conversion region 099146547 30 201143063 1406 Reset transistor gate 1408 Potential 1410 Amplifier gate 1412 Amplifier output 1414 Metal shield 1416 Electrical connector 1500 Sensor wafer 1502 Unit cell 1504 Circuit crystal Circle 1506 unit cell 1507 inter-wafer interconnect 1600 inter-wafer interconnect 1 602 Inter-wafer interconnect 1604 represents the direction of the shift arrow 1606 represents the direction of the shift arrow 1700 inter-wafer interconnect 1702 inter-wafer interconnect 1704 unit cell 1706 conductive layer 1708 contact point 1800 inter-wafer interconnect 1802 crystal Inter-circle interconnection 099146547 31 Conductive layer contact point photodetector sensor wafer transfer gate charge to voltage conversion area wafer to wafer electrical interconnection sensing interface between chip and circuit wafer circuit wafer Charge-to-voltage conversion region sensor wafer transfer gate charge to voltage conversion region wafer to wafer electrical interconnection sensor wafer and circuit wafer interface circuit wafer conductive layer charge to voltage conversion region The distance between adjacent inter-wafer interconnects. The distance between two adjacent inter-wafer interconnects. The spacing between two adjacent inter-wafer interconnects. 32 201143063 e Two adjacent Distance between inter-wafer interconnections f Distance between inter-wafer interconnections and contact points D1 Interconnection pitch D2 Interconnection pitch Ml Metal layer M2 Metal layer M3 Metal layer M4 Metal layer M5 Metal layer M6 Metal layer M7 Metal layer M8 gold Subordinate layer M9 metal layer M10 metal layer

S 099146547 33S 099146547 33

Claims (1)

201143063 七、申請專利範圍： 1. 一種影像感測器，其包含： 一感測器晶圓，其包含第一複數個單元晶胞，每一單元晶 胞包含至少一個光偵測器及一電荷至電壓轉換區； 一電路晶圓，其包含第二複數個單元晶胞，每一單元晶胞 包括一用於該感測器晶圓上之每一單元晶胞的電節點；及 一晶圓間互連，其連接於該感測器晶圓上之每一電荷至電 壓轉換區與該電路晶圓上之一各別電節點之間，其中該感測 器晶圓上之該等單元晶胞之一部分的一位置及該電路晶圓 上之該等單元晶胞之一對應部分的一位置相對於該感測器 晶圓及該電路晶圓上之5亥專剩餘早元晶胞的* -位置而移位 達一預定距離。 2. 如申請專利範圍第1項之影像感測器，其中，該電路晶 圓上之每一電節點連接至該電路晶圓上之一電荷至電壓轉 換區。 3. 如申請專利範圍第1項之影像感測器，其中，該電路晶 圓上之每一電節點連接至該電路晶圓上之一放大器之一閘 極。 4·如申請專利範圍第1項之影像感測器，其中，該感測器 晶圓上之每一單元晶胞包括兩個光偵測器及一共用之電荷 至電壓轉換區。 5.如申請專利範圍第1項之影像感測器，其中，該感測器 099146547 34 ⑧ 201143063 晶圓上之每一單元晶胞包括四個光偵測器及一共用之電荷 至電壓轉換區。 6. —種影像擷取裝置，其包含： 一影像感測器，其包含： 一感測器晶圓，其包含第一複數個單元晶胞，每一單元 晶胞包含至少一個光彳貞測器及一電荷至電壓轉換區； 一電路晶圓，其包含第二複數個單元晶胞，每一單元晶 胞包括一用於該感測器晶圓上之每一單元晶胞的電節點；及 一晶圓間互連，其連接於該感測器晶圓上之每一電荷至 電壓轉換區與該電路晶圓上之一各別電節點之間，其中該感 測器晶圓上之該等單元晶胞之一部分的一位置及該電路晶 圓上之該等單元晶胞之一對應部分的一位置相對於該感測 器晶圓及該電路晶圓上之該等剩餘單元晶胞的一位置而移 位達一預定距離。 7. 如申請專利範圍第6項之影像擷取裝置，其中，該電路 晶圓上之每一電節點連接至該電路晶圓上之一電荷至電壓 轉換區。 8. 如申請專利範圍第6項之影像擷取裝置，其中，該電路 晶圓上之每一電節點連接至該電路晶圓上之一放大器之一 閘極。 9. 如申請專利範圍第6項之影像擷取裝置，其中，該感測 器晶圓上之每一單元晶胞包括兩個光偵測器及一共用之電 099146547 35 201143063 荷至電壓轉換區。 10·如申請專利範圍第6項之影像擷取裝置，其中，該感 測器晶圓上之每一單元晶胞包括四個光偵測器及一共用之 電荷至電壓轉換區。 099146547 36 ⑧201143063 VII. Patent Application Range: 1. An image sensor comprising: a sensor wafer comprising a first plurality of unit cells, each unit cell comprising at least one photodetector and a charge a voltage conversion region; a circuit wafer comprising a second plurality of unit cells, each unit cell including an electrical node for each unit cell on the sensor wafer; and a wafer Inter-connector, which is connected between each charge-to-voltage conversion region on the sensor wafer and a respective electrical node on the circuit wafer, wherein the unit crystals on the sensor wafer a position of a portion of the cell and a position of a corresponding portion of the unit cell on the circuit wafer relative to the sensor wafer and the 5 MW residual early unit cell on the circuit wafer* - Position shifted by a predetermined distance. 2. The image sensor of claim 1, wherein each electrical node on the circuit circle is coupled to a charge-to-voltage conversion region on the circuit wafer. 3. The image sensor of claim 1, wherein each electrical node on the circuit circle is coupled to one of the gates of one of the amplifiers on the circuit wafer. 4. The image sensor of claim 1, wherein each unit cell on the sensor wafer comprises two photodetectors and a common charge to voltage conversion region. 5. The image sensor of claim 1, wherein the sensor unit 099146547 34 8 201143063 each unit cell on the wafer comprises four photodetectors and a common charge-to-voltage conversion region . 6. An image capture device comprising: an image sensor comprising: a sensor wafer comprising a first plurality of unit cells, each unit cell comprising at least one optical spectrometer And a charge-to-voltage conversion region; a circuit wafer comprising a second plurality of unit cells, each unit cell including an electrical node for each unit cell on the sensor wafer; And an inter-wafer interconnection, which is connected between each charge-to-voltage conversion region on the sensor wafer and a respective electrical node on the circuit wafer, wherein the sensor is on the wafer a position of a portion of the unit cells and a position of a corresponding portion of the unit cells on the circuit wafer relative to the sensor wafer and the remaining unit cells on the circuit wafer One position is shifted by a predetermined distance. 7. The image capture device of claim 6, wherein each electrical node on the circuit wafer is coupled to a charge-to-voltage conversion region on the circuit wafer. 8. The image capture device of claim 6, wherein each electrical node on the circuit wafer is connected to one of the gates of one of the amplifiers on the circuit wafer. 9. The image capturing device of claim 6, wherein each unit cell on the sensor wafer comprises two photodetectors and a common electric 099146547 35 201143063 load-to-voltage conversion region . 10. The image capture device of claim 6, wherein each unit cell on the sensor wafer comprises four photodetectors and a common charge to voltage conversion region. 099146547 36 8
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