TW202327025A - Memory device and method of forming the same - Google Patents

Abstract

A memory device includes a source layer on a substrate, a single crystalline silicon channel vertically disposed on the source layer, a word line gate surrounding a top portion of the single crystalline silicon channel, and a plate line gate surrounding a bottom portion of the single crystalline silicon channel. The plate line gate is parallel to the word line gate. In an extending direction of the single crystalline silicon channel, a thickness of the plate line gate is about 2 to 5 times of a thickness of the word line gate.

Description

Memory device and manufacturing method thereof

The disclosure relates to a memory device and a manufacturing method thereof.

In recent years, the structure of semiconductor devices has been constantly changing, and the storage capacity of semiconductor devices has been increasing. Memory devices are used as storage elements in many products (such as digital cameras, mobile phones, and computers, etc.). As these applications increase, the demand for memory devices is focused on small size and large storage capacity. In order to satisfy this condition, a memory device with high device density and small size and its manufacturing method are required.

Therefore, it is desirable to develop a three-dimensional (3D) memory device with a greater number of stacked planes to achieve greater storage capacity, improve quality, and maintain a small size of the memory device.

An embodiment of the present disclosure is a memory device, comprising a source layer disposed on a substrate, a monocrystalline silicon channel vertically disposed on the source layer, and a word line gate surrounding the upper part of the monocrystalline silicon channel , and the plate-line gate around the lower part of the monocrystalline silicon channel. The plate-line gate is parallel to the word-line gate, wherein the thickness of the plate-line gate is about two to five times the thickness of the word-line gate along the extending direction of the monocrystalline silicon channel.

In some embodiments, the memory device further includes a source line vertically disposed on the source layer, wherein the extending direction of the source line is parallel to the extending direction of the word line gate.

In some embodiments, the memory device further includes a bit line connected to the monocrystalline silicon channel, wherein the extending direction of the bit line is perpendicular to the extending direction of the word line gate.

In some embodiments, the memory device further includes an N-type contact region, the N-type contact region connects the bit line and the monocrystalline silicon channel, and the monocrystalline silicon channel includes P-type dopant.

In some embodiments, the memory device further includes an oxide layer disposed between the source layer and the line gate.

In some embodiments, an oxide layer surrounds the monocrystalline silicon channel.

Another embodiment of the present disclosure is a method of manufacturing a memory device, comprising forming a source layer on a substrate; forming a monocrystalline silicon channel vertically disposed on the source layer; forming a word line gate surrounding the monocrystalline silicon The upper part of the channel; and the lower part of the channel forming a plate line gate surrounding the single crystal silicon channel. The plate-line gate is parallel to the word-line gate, wherein the thickness of the plate-line gate is about two to five times the thickness of the word-line gate along the extending direction of the monocrystalline silicon channel.

In some embodiments, the steps of forming the word line gate and forming the plate line gate include forming a plurality of sacrificial layers respectively surrounding the upper portion and the lower portion of the single crystal silicon channel; a plurality of cavities at the upper and lower parts of the cavity; and depositing a high-k dielectric layer and a gate metal in the cavities.

In some embodiments, after forming the single crystal silicon channel vertically disposed on the source layer, further comprising forming an oxide layer on the upper surface of the source layer and sidewalls of the single crystal silicon channel, wherein the oxide layer is on the source electrode The thickness of the first portion of the upper surface of the layer is greater than the thickness of the second portion of the oxide layer on the sidewall of the monocrystalline silicon channel.

In some embodiments, the method of manufacturing the memory device further includes etching the oxide layer to remove the first portion of the oxide layer and thin the second portion of the oxide layer, wherein the line gate is formed on the thinned oxide layer. on the second part of the oxide layer.

The memory device of the present disclosure uses monocrystalline silicon as the channel region. Compared with the conventional channel using polysilicon, the memory device of the present disclosure has high current, fast response speed, and can reduce manufacturing defects. Monocrystalline silicon channels can be used with high-k metal gates to enhance the performance of memory devices. In addition, by dividing the gates into word line gates and plate line gates, the use of capacitors can be omitted, making the fabrication of memory devices easier.

The following will clearly illustrate the spirit of the disclosure with drawings and detailed descriptions. Anyone with ordinary knowledge in the technical field can make changes and modifications based on the techniques taught in the disclosure after understanding the preferred embodiments of the disclosure. It does not depart from the spirit and scope of this disclosure.

Referring to FIG. 1 to FIG. 23 , they are cross-sectional views of different steps of a manufacturing method of a memory device according to an embodiment of the present disclosure. First, in step S11 of FIG. 1 , a substrate 100 is provided, wherein the substrate 100 is a single crystal silicon substrate, and the substrate 100 is doped with a P-type dopant, such as boron or germanium, so that the substrate 100 serves as a P-type well.

Next, as shown in step S12 of FIG. 2 , a dry oxidation process is performed to form an oxide layer 110 with sufficient thickness on the substrate 100 . Compared with the oxide formed by chemical vapor deposition, the oxide layer 110 formed by the dry oxidation process is more suitable for wet etching solution (such as dilute hydrofluoric acid or buffered oxide etchant (Buffered Oxide Etch) ) will have better corrosion resistance.

Next, as shown in step S13 of FIG. 3, a series of exposure lithography processes are performed to pattern the oxide layer 110, and the substrate 100 is etched using the patterned oxide layer 110 as a hard mask. , and etch the substrate 100 to a predetermined depth. In this way, the semiconductor column 104 on the P-type well 102 can be obtained, wherein the semiconductor column 104 is a P-type doped single crystal silicon column.

Next, as shown in step S14 of FIG. 4, a nitride layer is deposited on the surfaces of the substrate 100 and the oxide layer 110, and then anisotropic etching is performed to remove the upper surfaces of the substrate 100 and the oxide layer 110. The nitride layer on the sidewalls of the substrate 100 and the oxide layer 110 is retained as the spacer 120 . The anisotropic etching used in step S14 can be, for example, reactive ion etching (reactive ion etching, RIE), which combines physical ion bombardment and chemical reaction etching, and has both anisotropy and high Etching selectivity and other advantages. The oxide layer 110 protects the semiconductor pillars 104 from anisotropic etching.

Next, as shown in step S15 of FIG. 5, ion implantation is performed on the exposed P-type well 102. At this time, the implanted ions are N-type dopants, such as phosphorus or arsenic, and the implanted N-type ions The concentration of is greater than the concentration of the P-type dopant in the P-type well 102 . Next, an annealing process is performed to drive N-type ions into the P-type well 102 to form an N-type source layer 106 .

Next, as shown in step S16 of FIG. 6 , the spacer 120 (see FIG. 5 ) is removed to expose the oxide layer 110 and the sidewalls of the semiconductor pillars 104 .

Next, as shown in step S17 of FIG. 7 , an oxide layer 130 is grown on the sidewall of the semiconductor pillar 104 and the surface of the N-type source layer 106 . Since the growth rate of the oxide on the N-type heavily doped silicon material (such as the N-type source layer 106) is significantly greater than that of the oxide on the undoped silicon material or the P-type lightly doped silicon material (such as the semiconductor pillar 104), therefore, the thickness T1 of the first part 132 of the grown oxide layer 130 on the upper surface of the N-type source layer 106 will also be significantly greater than the second part 134 of the oxide layer 130 on the side wall of the semiconductor pillar 104 The thickness T2.

In some embodiments, the thickness T1 of the first portion 132 of the oxide layer 130 on the upper surface of the N-type source layer 106 is about three to three times the thickness T2 of the second portion 134 of the oxide layer 130 on the sidewall of the semiconductor pillar 104 . six times. For example, the thickness T1 of the first portion 132 is about 100 Å, and the thickness T2 of the second portion 134 is about 300 Ř600 Å.

Next, as shown in step S18 of FIG. 8 , a wet etching process is performed to completely remove the second portion 134 of the oxide layer 130 on the sidewall of the semiconductor pillar 104 . The first portion 132 of the oxide layer 130 on the upper surface of the N-type source layer 106 and the oxide layer 110 as a hard mask will also be partially removed during this process, so that the thickness thereof is slightly reduced accordingly ( is thinned).

Then, as shown in step S19 of FIG. 9, a sacrificial layer 140 is formed on the structure shown in FIG. layer 110. The sacrificial layer 140 can be, for example, a nitride layer.

Next, as shown in step S20 of FIG. 10 , the sacrificial layer 140 is etched back to expose part of the semiconductor pillars 104 . The depth to which the sacrificial layer 140 is removed by the etch back can be well controlled.

Next, as shown in step S21 of FIG. 11, another oxide layer 150 is formed on the structure shown in FIG. mask oxide layer 110 .

Next, as shown in step S22 of FIG. 12 , the oxide layer 150 is etched back to expose part of the semiconductor pillars 104 again. The depth to which the oxide layer 150 is removed by the etch back can be well controlled. Repeat step S19 to step S22 again to form a stack of sacrificial layer 140 and oxide layer 150 surrounding semiconductor pillar 104, as shown in FIG. The thickness T3 of 140 is greater than the thickness T4 of the upper sacrificial layer 140 farther away from the N-type source layer 106 . In some embodiments, the thickness T3 of the lower sacrificial layer 140 is about two to five times the thickness T4 of the upper sacrificial layer 140 .

Next, as shown in step S23 of FIG. 14 , a capping oxide layer 160 is deposited on the structure shown in FIG. 13 . A capping oxide layer 160 is deposited on the topmost oxide layer 150 and the top surfaces of the semiconductor pillars 104 .

Next, as shown in step S24 of FIG. 15 , a plurality of trenches 170 are formed in the structure shown in FIG. 14 , wherein the trenches 170 are interposed between the semiconductor pillars 104 . The trench 170 extends through the stack of the sacrificial layer 140 and the oxide layer 150 and through the first portion 132 of the oxide layer 130 to expose the N-type source layer 106 .

Next, as shown in step S25 of FIG. 16 , wet etching is performed to remove the sacrificial layer 140 (see FIG. 15 ), wherein the etchant used for wet etching has an etch rate greater than that of oxides or nitrides. Silicon etch rate. After performing the wet etching, the sacrificial layer 140 is removed, and the sidewalls of the semiconductor pillars 104 are exposed between the oxide layers 150 . In other words, the cavity 172 is formed between the oxide layers 150 , and the sidewalls of the semiconductor pillars 104 are exposed from the cavity 172 . Corresponding to the different thicknesses of the removed sacrificial layer 140 , the two cavities 172 also have different thicknesses respectively, and the thickness T3 of the lower cavity 172 is greater than the thickness T4 of the upper cavity 172 .

Next, as shown in step S26 of FIG. 17 , a gate stack 180A and a gate stack 180B are formed in the cavity 172 (see FIG. 16 ). Forming the gate stack 180A and the gate stack 180B includes sequentially depositing a buffer layer (not shown in the figure), a gate dielectric layer 182 and filling a gate metal 184 in the cavity 172 . In some embodiments, the buffer layer may be an oxide layer. The gate dielectric layer 182 includes one or more layers of high-k dielectric layers, such as HfO _x and the like. The gate dielectric layer 182 may optionally further include a work function adjusting layer. The gate metal 184 can be, for example, titanium nitride (TiN) or tungsten (W).

Since the thicknesses of the two cavities 172 are different, after the gate stack 180A and the gate stack 180B are formed, the etching process can be performed again, so that the sidewalls of the gate stack 180A and the gate stack 180B are aligned with the sidewalls of the oxide layer 150 . In this way, the gate stack 180A and the gate stack 180B surrounding the semiconductor pillar 104 are formed, and the thickness T3 of the lower gate stack 180A is two to five times the thickness T4 of the upper gate stack 180B.

Furthermore, the semiconductor pillar 104 is surrounded by the gate stack 180A and the gate stack 180B, and serves as a channel region of the memory device. The semiconductor pillar 104 is a vertical channel region, and is a channel region of monocrystalline silicon. The upper gate stack 180B serves as a word line (WL) gate, and the lower gate stack 180A serves as a plate line (PL) gate. The direction of the gate stack 180A and the gate stack 180B is perpendicular to the direction of the semiconductor pillar 104 .

The first portion 132 of the oxide layer 130 is located between the N-type source layer 106 and the gate stack 180A, and the first portion 132 of the oxide layer 130 is disposed around the semiconductor pillar 104 .

Next, as shown in step S27 of FIG. 18, an isolation layer 190 is formed on the sidewall of the trench 170 (see FIG. 17). The step of forming the isolation layer 190 includes depositing a dielectric material, such as oxide, in the trench 170, and then performing anisotropic etching, such as reactive ion etching, to remove part of the dielectric material and expose the N-type source again. Layer 106 , the dielectric material remaining on the sidewalls of trench 170 serves as isolation layer 190 .

Next, metal is filled into the trench 170 to form the source line 200 , and the filled metal can be, for example, titanium nitride or tungsten. After the metal is filled into the trench 170 , a planarization process can be performed to make the top surface of the source line 200 flush with the top surface of the capping oxide layer 160 . The top surface of the semiconductor pillar 104 is lower than the top surface of the source line 200 .

Next, as shown in step S28 of FIG. 19 , a dielectric layer 210 is deposited on the structure shown in FIG. 18 to cover the source line 200 and the capping oxide layer 160 .

Next, as shown in step S29 of FIG. 20 , an opening 220 is formed above the semiconductor pillar 104 , and the opening 220 passes through the dielectric layer 210 and the capping oxide layer 160 to expose the semiconductor pillar 104 .

Next, as shown in step S30 of FIG. 21 , ion implantation is performed on the semiconductor pillar 104 through the opening 220 , and the implanted ions are N-type dopants, such as phosphorus or arsenic. The concentration of the implanted N-type ions is greater than the concentration of the P-type dopant in the semiconductor pillar 104 to form an N-type contact region 230 at the top of the semiconductor pillar 104 .

Next, as shown in step S31 of FIG. 22, a contact pad 240 is formed in the opening 220 (see FIG. 21), including filling metal into the opening 220 to form the contact pad 240, and the contact pad 240 is physically connected to the N-type contact area 230 .

The filling metal can be, for example, titanium nitride or tungsten. After the metal is filled into the opening 220 , a planarization process can be performed to make the top surface of the contact pad 240 flush with the top surface of the dielectric layer 210 .

Finally, as shown in step S32 of FIG. 23, a bit line (bit line, BL) 250 is formed on the contact pad 240, wherein the direction of the bit line 250 is perpendicular to the direction of the source line 200, and the direction of the bit line 250 The direction is also perpendicular to the direction of gate stack 180A and gate stack 180B. The step of forming the bit lines 250 includes depositing a metal layer on the top surface of the dielectric layer 210 and then patterning the metal layer to leave the bit lines 250 on the top surface of the dielectric layer 210 and connected to the contact pads 240 .

Please refer to FIG. 23 and FIG. 24 at the same time, wherein FIG. 24 is a top view of a memory device according to an embodiment of the present disclosure, and FIG. 23 is a cross-sectional view along line A-A in FIG. 24 . The memory device 300 includes a semiconductor pillar 104 extending along the Z-axis direction, wherein the semiconductor pillar 104 is a channel region of monocrystalline silicon. The memory device 300 includes a gate stack 180A and a gate stack 180B extending along the Y axis and arranged in parallel, wherein the gate stack 180B serves as a word line gate, and the gate stack 180A serves as a plate line gate. The thickness T3 of the gate stack 180A is twice to five times the thickness T4 of the gate stack 180B, wherein the thicknesses T3 and T4 are defined along the extending direction of the semiconductor pillar 104 (ie, the Z-axis direction).

The memory device 300 includes source lines 200 extending along the Y-axis direction, and in this embodiment, the source lines 200 and the gate stacks 180A are arranged alternately, and a single row of semiconductor pillars 104 is arranged between the source lines 200 between. The memory device 300 includes a bit line 250 extending along the X-axis direction, wherein the bit line 250 extends above the semiconductor pillar 104, and the direction of the bit line 250 is perpendicular to the source line 200, the gate stack 180A and the gate direction of pole stack 180B.

Referring to FIG. 25 , it is a top view of a memory device according to another embodiment of the present disclosure. The difference between the memory device 300' of this embodiment and the memory device 300 in FIG. 24 is that multiple rows of semiconductor pillars 104 are arranged between the source lines 200, and these rows of semiconductor pillars 104 are slightly apart from each other. misaligned.

To sum up, the memory device of the present disclosure uses monocrystalline silicon as the channel region. Compared with the conventional channel using polysilicon, the memory device of the present disclosure has high current, fast response speed, and can reduce manufacturing defects. Monocrystalline silicon channels can be used with high-k metal gates to enhance the performance of memory devices. In addition, by dividing the gates into word line gates and plate line gates, the use of capacitors can be omitted, making the fabrication of memory devices easier.

Although this disclosure has been disclosed as above with the embodiment, it is not intended to limit this disclosure. Anyone who is familiar with this technology can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the protection of this disclosure The scope shall be defined by the appended patent application scope.

100: Substrate 102: P-type well 104: Semiconductor pillar 106: Source layer 110: oxide layer 120: spacer 130: oxide layer 132: Part 1 134: Part Two 140: sacrificial layer 150: oxide layer 160: capping oxide layer 170: Groove 172: cavity 180A, 180B: gate stack 182: gate dielectric layer 184:Gate metal 190: isolation layer 200: source line 210: dielectric layer 220: opening 230: N-type contact area 240: contact pad 250: bit line 300,300': memory device S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, S31, S32: steps T1, T2, T3, T4: Thickness X, Y, Z: axes A-A: line segment

In order to make the purpose, features, advantages and embodiments of this disclosure more obvious and easy to understand, the detailed description of the accompanying drawings is as follows: FIG. 1 to FIG. 23 are cross-sectional views of different steps of a manufacturing method of a memory device according to an embodiment of the present disclosure. FIG. 24 is a top view of a memory device according to an embodiment of the disclosure. FIG. 25 is a top view of a memory device according to another embodiment of the disclosure.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

100: Substrate

102: P-type well

104: Semiconductor pillar

106: Source layer

130: oxide layer

132: Part 1

150: oxide layer

160: capping oxide layer

180A, 180B: gate stack

190: isolation layer

200: source line

210: dielectric layer

230: N-type contact area

240: contact pad

250: bit line

300: memory device

S32: step

T3, T4: Thickness

Claims (10)

A memory device comprising: a source layer disposed on a substrate; a single crystal silicon channel vertically arranged on the source layer; a word line gate surrounding the upper portion of the monocrystalline silicon channel; and a plate-line gate surrounding the lower portion of the monocrystalline silicon channel parallel to the word-line gate, wherein the plate-line gate has a thickness of approximately the word-line gate in a direction extending along the monocrystalline silicon channel Two to five times the thickness of the line gate. The memory device as described in claim 1, further comprising: A source line is vertically arranged on the source layer, wherein the extending direction of the source line is parallel to the extending direction of the word line gate. The memory device as described in claim 1, further comprising: A bit line is connected with the single crystal silicon channel, wherein the extending direction of the bit line is perpendicular to the extending direction of the word line gate. The memory device as described in claim 3, further comprising: An N-type contact region connects the bit line and the single-crystal silicon channel, and the single-crystal silicon channel contains P-type dopant. The memory device as described in claim 1, further comprising: An oxide layer is disposed between the source layer and the line gate. The memory device according to claim 5, wherein the oxide layer surrounds the single crystal silicon channel. A method of manufacturing a memory device, comprising: forming a source layer on a substrate; forming a single crystal silicon channel vertically arranged on the source layer; forming a word line gate surrounding the upper portion of the single crystal silicon channel; and forming a plate-line gate around the lower portion of the single-crystal silicon channel, the plate-line gate parallel to the word-line gate, wherein along the extending direction of the single-crystal silicon channel, the plate-line gate The thickness is about two to five times that of the word line gate. The method for manufacturing a memory device according to claim 7, wherein the steps of forming the word line gate and forming the plate line gate include: forming a plurality of sacrificial layers respectively surrounding the upper part and the lower part of the single crystal silicon channel; removing the sacrificial layers to form a plurality of cavities respectively surrounding the upper and lower portions of the monocrystalline silicon channel; and A high-k dielectric layer and a gate metal are deposited in the cavities. The method for manufacturing a memory device according to claim 7, after forming a single crystal silicon channel vertically disposed on the source layer, further comprising: forming an oxide layer on the upper surface of the source layer and sidewalls of the single crystal silicon channel, wherein a first portion of the oxide layer on the upper surface of the source layer has a thickness greater than that of the oxide layer on the single crystal silicon channel The thickness of a second portion of the sidewall of the silicon channel. The manufacturing method of the memory device as described in Claim 9, further comprising: etching the oxide layer to remove the first portion of the oxide layer and thin the second portion of the oxide layer, wherein the line gate is formed on the thinned second portion of the oxide layer partly on.

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