TW202230634A - Three-dimensional dynamic random access memory (dram) and methods of forming the same - Google Patents

Abstract

Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.

Description

Three-dimensional dynamic random access memory and method of forming the same

The examples described herein relate generally to the field of semiconductor processing, and more particularly, to three-dimensional (3D) dynamic random access memory (DRAM) and methods of forming 3D DRAM.

Technological advances in semiconductor processing have pushed integrated circuits to the physical limits of Moore's Law. These advances have led to new models of components and structures in integrated circuits. For example, various three-dimensional (3D) components have been developed for integrated circuits. However, such 3D components may present a new set of challenges for handling and manufacturing.

Embodiments of the present disclosure include a method for semiconductor processing. A film stack is formed on a substrate. The film stack includes a plurality of cell stacks, and each cell stack has a first dielectric layer, a semiconductor layer disposed on the first dielectric layer, and a second dielectric layer disposed on the semiconductor layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening to form a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening is formed through the film stack. The second opening is disposed laterally from where the first opening is formed. The gate structure is laterally disposed between the second opening and where the first opening is formed. The portion of the semiconductor layer is pulled back from the second opening to form a second lateral recess. A capacitor is formed in the region where the second lateral recess is provided. The capacitor contacts the portion of the semiconductor layer.

Embodiments of the present disclosure include a method for semiconductor processing. A film stack is formed on a substrate. The membrane stack includes a plurality of cell stacks, and each cell stack has a first layer and a second layer disposed on the first layer. A first opening is formed through the film stack. Pulling the first layer back from the first opening forms a first lateral recess. A first conformal layer is formed in the first lateral recess. A first filler material is formed on the first conformal layer and in the first lateral recess. The first conformal layer is pulled back from the first opening to form a second lateral recess. A gate structure is formed in the second lateral recess and disposed on and below the semiconductor layer. The semiconductor layer is horizontally aligned with the second layer. A second opening is formed through the film stack. The second opening is disposed laterally from where the first opening is formed. The gate structure is laterally disposed between the second opening and where the first opening is formed. The second layer is pulled back from the second opening to form a third lateral recess into the semiconductor layer. A capacitor is formed in the region where the third lateral recess is provided. The capacitor contacts the semiconductor layer.

Embodiments of the present disclosure include a method for semiconductor processing. A film stack is formed on a substrate. The film stack includes at least five layers. Each of the at least five layers is formed from a material selected from the group of materials comprising no more than three different materials. Using the film stack as a mold, pairs of vertically stacked mirrored DRAM pairs are formed on the substrate. Each of the vertically stacked mirrored DRAM pairs includes a contact, a first transistor, a second transistor, a first capacitor, and a second capacitor. The first transistor includes a first gate structure, a first source/drain region and a second source/drain region. The first source/drain region contacts the contact. The second transistor includes a second gate structure, a third source/drain region and a fourth source/drain region. The third source/drain region contacts the contact. The second transistor mirrors the first transistor around the contact. The first capacitor has a first outer plate, a first capacitor dielectric layer and a first inner plate. The first outer plate contacts the second source/drain region. The second capacitor has a second outer plate, a second capacitor dielectric layer, and a second inner plate. The second outer plate contacts the fourth source/drain region.

The examples described herein relate generally to semiconductor processing, and more particularly to three-dimensional (3D) dynamic random access memory (DRAM) and methods of forming 3D DRAM. According to various examples, a film stack is formed on a substrate. The film stack includes, for example, five or more layers, wherein each of the five or more layers is formed from a material selected from the group of no more than three different materials, and further, in some examples , the material is selected from the group of no more than two different materials. The membrane stack is formed from one or more unit stacks, wherein each unit stack is formed from no more than two or three different materials. The film stack is used as a mold to form 3D DRAM elements. In particular, the die is used to form two or more vertically stacked mirrored DRAM pairs. When using a mold process, an increase in the number of different materials used for the layers of the mold can lead to increased processing costs, including the use of additional deposition and etching processes. Reducing the number of different materials used for layers (eg, with the various examples described herein) can reduce processing costs, such as by having fewer deposition and etching processes, and thus can result in more cost-effective devices. Furthermore, various numbers of vertically stacked mirrored DRAM pairs can be achieved without adding additional different materials. The different examples in this paper can also implement single or dual gate transistors for 3D DRAM.

Various examples are described below. Although various features of different examples may be described together in process flows or systems, each of the various features can be implemented separately or individually and/or in different process flows or different systems. Furthermore, various process flows are described as being performed sequentially; other examples can implement the process flows in a different order and/or more or fewer operations. Furthermore, although source and drain nodes and source and drain regions are described in various examples, such descriptions can be more generally with respect to source/drain nodes or source/drain regions. Again, in some examples, n-type transistors are described, and more generally, any type of transistor can be implemented.

1 is a schematic circuit diagram of a dynamic random access memory (DRAM) cell according to some examples of the present disclosure. The DRAM cell includes an n-type transistor 2 and a capacitor 4 . The drain node 6 of the n-type transistor 2 is electrically connected to a bit line (BL) node 8 . The source node 10 of the n-type transistor 2 is electrically connected to the first terminal of the capacitor 4, and the second terminal (opposite the first terminal) of the capacitor 4 is electrically connected to a power supply node (eg, a ground node). The gate node 12 of the n-type transistor 2 is electrically connected to a word line (WL) node.

2 is a perspective view of a mirrored DRAM pair according to some examples of the present disclosure. Figure 2 depicts two DRMA cells that are mirrored along a vertical axis, which for convenience may be referred to herein as a mirrored DRAM pair. As will become apparent from the description below, multiple pairs of mirrored DRAM pairs (eg, two pairs, three pairs, etc.) may be stacked vertically in a DRAM structure. In order to avoid unnecessarily obscuring the various aspects of the drawings, mirroring one DRAM cell of a DRAM pair is designated with a reference numeral, and one of ordinary skill in the art will readily understand the mirror in the other DRAM cell of a mirroring DRAM pair. shoot parts.

The DRAM cell includes an n-type transistor 22 and a capacitor 24 . The n-type transistor 22 includes a semiconductor material 26 that forms the active region of the n-type transistor 22 . For example, the semiconductor material 26 may be substantially p-type doped. Drain region 28 and source region 30 are disposed in semiconductor material 26 while a channel region is located in semiconductor material 26 between drain region 28 and source region 30 . In this example, drain region 28 and source region 30 are n-type doped. Gate dielectric layer 32 is disposed on semiconductor material 26 (eg, on a top surface of semiconductor material 26 ), and gate electrode 34 is disposed on gate dielectric layer 32 .

Capacitor 24 includes outer plate 36 , capacitor dielectric layer 38 and inner plate 40 . The outer plate 36 is a conductive material, such as a metal or metal-containing material. The outer panel 36 generally has the shape of a single-capped cylinder, a single-capped rectangular prism, or the like. Outer plate 36 generally extends laterally from n-type transistor 22 and has a cap end that contacts source region 30 of n-type transistor 22 to electrically connect source region 30 to capacitor 24 . The end of the outer plate 36 opposite to the n-type transistor 22 is open. The capacitor dielectric layer 38 is a dielectric material that is conformally disposed along the inner surface of the outer plate 36 . The dielectric material of capacitor dielectric layer 38 can be a high-k dielectric material (eg, having a k value greater than 4.0). The inner plate 40 is a conductive material, such as a metal or metal-containing material, and is disposed on the capacitor dielectric layer 38 and fills the remaining interior portion of the outer plate 36 .

Bit line contacts 42 are provided to laterally contact drain region 28 of n-type transistor 22 . The bit line contacts 42 extend vertically and a vertical axis along which the DRAM pair is mirrored extends along the bit line contacts 42 . Power supply contacts 44 (eg, ground contacts) are provided to laterally contact the inner plate 40 of the capacitor 24 .

3 is a perspective view of a mirrored DRAM pair according to some examples of the present disclosure. The 3D DRAM cell of FIG. 3 is similar to the 3D DRAM cell of FIG. 2, and the common description is omitted for brevity. The DRAM cell includes n-type transistor 52 and capacitor 24 . The n-type transistor 52 includes a semiconductor material 54 that forms the active region of the n-type transistor 52 . For example, semiconductor material 54 may generally be p-type doped. Drain region 56 and source region 58 are disposed in semiconductor material 54 and a channel region is located in semiconductor material 54 between drain region 56 and source region 58 . In this example, drain region 56 and source region 58 are n-type doped. Top gate dielectric layer 60 is disposed on semiconductor material 54 (eg, on the top surface of semiconductor material 54 ), and bottom gate dielectric layer 62 is disposed on semiconductor material 54 opposite top gate dielectric layer 60 on one side (eg, on the bottom surface of semiconductor material 54). Top gate electrode 64 is disposed on (eg, above) top gate dielectric layer 60 , and bottom gate electrode 66 is disposed on (eg, below) bottom gate dielectric layer 62 .

The cap end of outer plate 36 contacts source region 58 of n-type transistor 52 to electrically connect source region 58 to capacitor 24 . Bit line contact 42 is provided to laterally contact drain region 56 of n-type transistor 52 .

4-12 are cross-sectional views of intermediate structures during a first method of forming a 3D DRAM cell, according to some examples of the present disclosure. A 3D DRAM cell formed according to the first method of FIGS. 4-12 can be similar to that shown in FIG. 2 .

Referring to FIG. 4 , a film stack is deposited on a substrate 100 . The film stack includes multiple cell stacks (eg, two cell stacks in the example shown) that are partially utilized sacrificially to form 3D DRAM cells. As can be seen, this method forms a two-layer 3D DRAM cell. In other examples, cell stacks of repeated film stacks can form additional layers of 3D DRAM cells. Also, an example of using a cell stack in a film stack enables the formation of a one-layer 3D DRAM cell.

Substrate 100 includes any suitable semiconductor substrate, such as a bulk substrate, a semiconductor-on-insulator (SOI) substrate, and the like. In some examples, the semiconductor substrate is a bulk silicon wafer. Examples of substrate dimensions include, among others, 200 mm diameter, 350 mm diameter, 400 mm diameter, 450 mm diameter, and the like. The substrate 100 can further include any layer (eg, any number of other dielectric layers) or structures on the semiconductor substrate.

The film stack includes a plurality of cell stacks, where the cell stack includes a first dielectric layer 102 , a semiconductor layer 104 and a second dielectric layer 106 . The unit stack of film stacks is or consists of a first dielectric layer 102, a semiconductor layer 104 on the first dielectric layer 102, and a second dielectric layer 106 on the semiconductor layer 104. In FIG. 4 , two examples of this cell stack are stacked on substrate 100 . The first dielectric layers 102 can each be of the same dielectric material, and the second dielectric layers 106 can each be of the same dielectric material, the second dielectric layer having a different dielectric material than the first dielectric layer The dielectric material of the first dielectric layer 102 has an etch selectivity between the dielectric materials of the first dielectric layer 102 . The semiconductor layers 104 can each be of the same semiconductor material. As can be appreciated, the substantially different layers of material allow for selective etching of the target layer during processing. The film stack serves as a mold for forming DRAM cells. In some examples, the first dielectric layer 102 is silicon oxide; the second dielectric layer 106 is silicon nitride; and the semiconductor layer 104 is silicon (eg, amorphous or polycrystalline, which may be p-type doped) or InGaZnO. Each of the first dielectric layer 102, the semiconductor layer 104, and the second dielectric layer 106 can be deposited by any suitable deposition technique, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like.

In FIG. 5, openings 108 are formed through the film stack (eg, through first dielectric layer 102, semiconductor layer 104, and second dielectric layer 106). The openings 108 can be formed by using anisotropic etching, such as reactive ion etching (RIE) or the like.

In FIG. 6 , the second dielectric layer 106 is pulled back from the opening 108 , while the lateral recess 110 is formed from the opening 108 . The pullback process can be any suitable isotropic etch that selectively etches the second dielectric layer 106 . For example, when the second dielectric layer 106 is silicon nitride, a thermal phosphoric acid etch process can be used to pull back the second dielectric layer 106 . Multiple layers in the film stack (eg, first dielectric layer 102 and semiconductor layer 104 ) can reduce the likelihood of collapse when second dielectric layer 106 is pulled back.

FIG. 7 illustrates gate dielectric layer 112 , gate barrier and/or work function adjustment (“barrier/adjustment”) layer 114 , gate electrode fill material 116 , and dielectric fill material 118 . Gate dielectric layers 112 are formed on surfaces of the respective semiconductor layers 104 that are exposed through openings 108 and lateral recesses 110 . The gate dielectric layer 112 can be any suitable dielectric material formed by any suitable process. In some examples, gate dielectric layer 112 is an oxide formed by an oxidation process (eg, by oxidizing exposed surfaces of semiconductor layer 104 ). In some examples, gate dielectric layer 112 can be another material formed by a conformal deposition process, such as atomic layer deposition (ALD).

Then, a gate barrier/adjustment layer 114 is conformally formed along the surface of the lateral recess 110, and a gate electrode filling material 116 is formed on the gate barrier/adjustment layer 114. In some examples, gate barrier/adjustment layer 114 is formed using a conformal deposition process (eg, ALD). The conformal deposition process can form a conformal layer on the surface defining the opening 108 and the lateral recess 110 (eg, including the gate dielectric layer 112 ). The conductive material of gate electrode fill material 116 can then be deposited on the conformal layer by any suitable deposition process. A node separation process is performed to remove some conductive material of gate electrode fill material 116 and some conformal layers of gate barrier/adjustment layer 114 to form gate barrier/adjustment in respective lateral recesses 110 layer 114 and gate electrode fill material 116 . The node separation process can include performing an anisotropic etch (eg, RIE) followed by a selective isotropic etch of the gate barrier/adjustment layer 114 and gate electrode fill material 116 materials. The anisotropic etch removes the conductive material of the gate electrode fill material 116 and the gate barrier/adjustment layer 114 between the second dielectric layer 106 defining the opening 108 and the vertical sidewalls of the first dielectric layer 102 Conformal layer. The isotropic etch laterally recesses the gate electrode fill material 116 and the gate barrier/adjustment layer 114 to have vertical sidewalls that are offset from the semiconductor layer 104 and the first dielectric layer 102 that define the opening 108 vertical surface. In some examples, gate barrier/adjustment layer 114 can be any suitable diffusion barrier material and/or can be any work function adjusting material, such as TiN or the like, to adjust the threshold voltage of the transistor. In some examples, gate electrode fill material 116 can be any conductive material, such as a metal, such as tungsten.

Then, a dielectric fill material 118 is formed in the openings 108 and the remaining unfilled portions of the lateral recesses 110 . The dielectric fill material 118 can be any suitable dielectric material deposited by any suitable deposition process. In some examples, the dielectric fill material 118 is an oxide deposited by a conformal deposition (eg, ALD) or flowable deposition process (eg, flowable CVD (FCVD)).

In FIG. 8, openings 120 are formed through the film stack (eg, through first dielectric layer 102, semiconductor layer 104, and second dielectric layer 106). As can be appreciated, each opening 120 is used in the formation of a capacitor that will be electrically connected to a respective transistor of which gate electrode fill material 116 and gate barrier/adjustment layer 114 are part. Each opening 120 is disposed at a certain lateral distance from the corresponding gate electrode filling material 116 and gate barrier/adjustment layer 114 , and the corresponding gate electrode filling material 116 and gate barrier/adjustment layer 114 Disposed laterally between respective openings 120 and where openings 108 are formed (eg, filled with dielectric fill material 118 ). The openings 120 can be formed using anisotropic etching, such as reactive ion etching (RIE), or the like.

In FIG. 9 , the semiconductor layers 104 are pulled back from the respective openings 120 and the lateral recesses 122 are formed from the respective openings 120 . The pullback process can be any suitable isotropic etch that selectively etches the semiconductor layer 104 . For example, when the semiconductor layer 104 is silicon, a tetramethylammonium hydroxide (TMAH) etch process or a dry plasma isotropic etch can be used to pull back the semiconductor layer 104 .

At the respective lateral recesses 122 , the semiconductor layer 104 is doped at the vertical sidewall surfaces of the semiconductor layer 104 to form source regions 124 . The source region 124 can be doped with an n-type dopant. Doping can be performed by using gas-phase dopants and/or plasma-assisted doping processes.

In FIG. 10 , the lateral concave portion 122 is expanded to form an enlarged lateral concave portion 126 . The extension can include an isotropic etch that selectively etches the second dielectric layer 106 and an isotropic etch that selectively etches the first dielectric layer 102 . The isotropic etching can be a wet or dry process. In some examples in which the first dielectric layer 102 is silicon oxide and the second dielectric layer 106 is silicon nitride, the second dielectric layer 106 can be etched using a hot phosphoric acid etch process or a dry plasma etch process, and can use A hydrofluoric acid based process (eg, wet diluted hydrofluoric acid (dHF) or dry HF process) etches the first dielectric layer 102 .

FIG. 11 shows the formation of capacitors in enlarged lateral recesses 126 . Each capacitor includes an outer plate 130 , a capacitor dielectric layer 132 , and an inner plate 134 . The outer plate 130 is formed conformally along the surface of the enlarged lateral recess 126 . In some examples, the outer plate 130 is formed using a conformal deposition process such as ALD. The conformal deposition process enables conformal layers to be formed on surfaces defining openings 120 and enlarged lateral recesses 126 (eg, including respective sidewall surfaces of semiconductor layer 104 where corresponding source regions 124 are disposed). A node separation process is performed to remove some of the conformal layers on the vertical sidewalls defining the openings 120 and to form the outer plates 130 in the respective enlarged lateral recesses 126 . The node separation process can include filling the openings 120 and the enlarged lateral recesses 126 with a fill material, and performing suitable anisotropic and isotropic etching processes to remove vertical sidewalls (eg, the first dielectric layer 102 ) that define the openings 120 and vertical sidewalls of the second dielectric layer 106 ) remove portions of the conformal layer and remove the fill material.

Then, capacitor dielectric layers 132 are formed on the inner surfaces of the respective outer plates 130 . The capacitor dielectric layers 132 can be formed by conformal deposition (eg, ALD) that forms the conformal capacitor dielectric layers 132 in the respective openings 120 (eg, along the second dielectric layer 106 defining the openings 120 ). and the vertical sidewalls of the first dielectric layer 102 ) and the inner surfaces of the respective outer plates 130 .

Then, the inner plate 134 is formed on the outer plate 130 . The inner plate 134 can be formed by conformal deposition (eg, ALD) that forms the inner plate 134 on the capacitor dielectric layer 132 . In the example shown, the inner panel 134 fills the remaining unfilled portion of the enlarged lateral recess 126 , however, in some examples, the inner panel 134 may not fill the remaining unfilled portion of the enlarged lateral recess 126 . As shown, the inner plate 134 can be formed from a continuous material deposited in the respective openings 120 and enlarged lateral recesses 126 . Since the inner plate 134 forms the terminals of the respective DRAM cells and the terminals are electrically connected to power supply nodes (eg, ground nodes) (as described with respect to FIG. 1 ), the inner plate 134 is able to penetrate through the continuous material from which the inner plate 134 is formed electrically connected together. In the example shown, the material of the inner plate 134 does not fill the openings 120 , and a conductive fill material 136 is formed in the unfilled portions of the openings 120 . In some examples, the material of inner panel 134 fills the remaining unfilled portion of opening 120 . The inner plates 134 and/or the conductive fill material 136 , which are electrically connected together, eg, through the material of the inner plates 134 , form a power supply node (eg, a ground node) that connects between the plurality of DRAM cells. In examples in which conductive fill material 136 is used, conductive fill material 136 can be deposited by any suitable deposition process (eg, CVD, PVD, etc.).

In some examples, the material of the outer plate 130 and the material of the inner plate 134 can be any conductive material, such as a metal or metal-containing material (such as TiN). In some examples, the material of capacitor dielectric layer 132 can be any dielectric material, and further can be any high-k dielectric material (eg, having a k value greater than 4.0). In some examples, the conductive fill material 136 can be any conductive material, such as silicon germanium (eg, doped silicon germanium).

In FIG. 12, drain region 138, barrier layer 140, and conductive fill material 142 are formed. Openings are formed through the dielectric fill material 118 . The openings expose vertical sidewalls of the semiconductor layer 104 . The openings can be formed and exposed vertical sidewalls of the semiconductor layer 104 using an etching process. For example, the etching process can include anisotropic etching and/or isotropic etching. The gate dielectric layer 112 previously formed on the vertical sidewalls of the semiconductor layer 104 is removed by an etching process to expose the vertical sidewalls of the semiconductor layer 104 .

Lateral portions of semiconductor layer 104 at respective vertical sidewalls exposed by the openings are doped to form drain regions 138 . The drain region 138 can be doped with an n-type dopant. The doping can be performed using gas-phase dopants and/or plasma-assisted doping processes. With the formation of the drain region 138, individual transistors are formed for the DRAM cells. For each DRAM cell, the transistor includes source region 124 in semiconductor layer 104 , drain region 138 in semiconductor layer 104 , channels in semiconductor layer 104 between source region 124 and drain region 138 region, and a gate structure disposed on the semiconductor layer 104 in alignment over the channel region. The gate structure includes a gate dielectric layer 112 and a gate electrode filling material 116 . This approach can allow very thin sections of the semiconductor layer 104 to be implemented for the channel region of the transistor.

Then, a barrier layer 140 is formed in the opening. The barrier layer 140 is conformally formed along the surface of the opening, including along the exposed vertical sidewalls of the semiconductor layer 104 where the drain region 138 is disposed. In some examples, barrier layer 140 is formed using a conformal deposition process such as ALD. Then, conductive fill material 142 can be deposited on barrier layer 140 by any suitable deposition process. In some examples, barrier layer 140 can be any suitable diffusion barrier material, such as TiN or the like. In some examples, the conductive fill material 142 can be any conductive material, such as a metal such as tungsten. Barrier layer 140 and conductive fill material 142 generally form a contact, which may be a bit line node of a DRAM cell. The contacts are along a vertical axis about which the mirrored DRAM pair is mirrored.

13-27 are cross-sectional views of intermediate structures during a second method of forming a 3D DRAM cell according to some examples of the present disclosure. A 3D DRAM cell formed according to the second method of FIGS. 13-27 can be similar to that shown in FIG. 3 .

Referring to FIG. 13 , a film stack is deposited on the substrate 100 . The film stack includes multiple cell stacks (eg, two cell stacks in the example shown) that are partially utilized sacrificially to form 3D DRAM cells. As can be seen, this method forms a two-layer 3D DRAM cell. In other examples, cell stacks of repeated film stacks can form additional layers of 3D DRAM cells. Also, an example of using a cell stack in a film stack enables the formation of a one-layer 3D DRAM cell.

The film stack includes a plurality of cell stacks, where the cell stack includes a sacrificial layer 202 and a dielectric layer 204 . The unit stack of the film stack is the sacrificial layer 202 and the dielectric layer 204 on the sacrificial layer 202, or consists of both. Two examples of this cell stack are stacked on substrate 100 in FIG. 13 . The sacrificial layers 202 can each be of the same material, and the dielectric layers 204 can each be of the same dielectric material, which is different from the material of the sacrificial layer 202 and has an etch selectivity between the materials of the sacrificial layer. As can be appreciated, the substantially different layers of material allow for selective etching of the target layer during processing. The film stack serves as a mold for forming DRAM cells. In some examples, sacrificial layer 202 is silicon, silicon germanium, doped silicon oxide, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or silicon nitride, and dielectric layer 204 is silicon oxide . Each of the sacrificial layer 202 and the dielectric layer 204 can be deposited by any suitable deposition technique (eg, CVD, PVD, etc.).

In FIG. 14, openings 206 are formed through the film stack (eg, through sacrificial layer 202 and dielectric layer 204). The openings 206 can be formed by using anisotropic etching (eg, RIE, etc.).

In FIG. 15 , the dielectric layer 204 is pulled back from the opening 206 and a lateral recess 208 is formed from the opening 206 . The pullback process can be any suitable isotropic etch that selectively etches the dielectric layer 204 . For example, when the dielectric layer 204 is silicon oxide, the dielectric layer 204 can be etched using a hydrofluoric acid based process (eg, a wet dHF or dry HF process).

In FIG. 16 , semiconductor layer 210 is formed to fill lateral recess 208 . The semiconductor layer 210 can be formed by using a conformal deposition (eg, ALD) that conformally deposits the material of the semiconductor layer 210 along the surface defining the opening 206 and the lateral recess 208 . The material of the semiconductor layer 210 can be removed from between the sidewalls of the sacrificial layer 202 that define the openings 206 using anisotropic etching. The semiconductor layer 210 can be any semiconductor material. In some examples, the semiconductor layer 210 is silicon (eg, may be amorphous or polycrystalline, which may be p-type doped) or InGaZnO.

In FIG. 17 , the sacrificial layer 202 is pulled back from the opening 206 and a lateral recess 212 is formed from the opening 206 . In some examples, the sacrificial layer 202 is pulled back or beyond a corresponding vertical sidewall of the semiconductor layer 210 remote from the opening 206 . The pullback process can be any suitable isotropic etch that selectively etches the sacrificial layer 202 . For example, when the sacrificial layer 202 is silicon nitride, the sacrificial layer 202 can be pulled back using a thermal phosphoric acid etch process.

FIG. 18 illustrates the conformal sacrificial material 214 and the dielectric fill material 216 . The conformal sacrificial material 214 can be formed by using a conformal deposition (eg, ALD) that is co-formed along the surfaces defining the openings 206 and the lateral recesses 212 (eg, vertical sidewalls of the sacrificial layer 202 and exposed surfaces of the semiconductor layer 210 ). The material of the conformal sacrificial material 214 is deposited. Dielectric fill material 216 can be deposited over the conformal deposition material of conformal sacrificial material 214 by any suitable deposition (eg, by ALD, FCV, etc.) to fill the remaining unfilled portions of openings 206 and lateral recesses 212 . Anisotropic etching can be used to remove materials such as the conformal sacrificial material 214 and the dielectric fill material 216 from between the sidewalls of the semiconductor layer 210 that define the openings 206 . The conformal sacrificial material 214 can be any sacrificial material, such as a sacrificial dielectric material, and the dielectric fill material 216 can be any dielectric material. In some examples, the conformal sacrificial material 214 is silicon nitride and the dielectric fill material 216 is silicon oxide.

In FIG. 19 , lateral portions of the conformal sacrificial material 214 are pulled back from the openings 206 and lateral recesses 218 are formed from the openings 206 . The dielectric fill material 216 formed on the respective conformal sacrificial material 214 can remain vertically disposed between the lateral recesses 218 formed by pulling back the respective conformal sacrificial material 214. The pullback process can be any suitable isotropic etch that selectively etches the conformal sacrificial material 214 . For example, when the conformal sacrificial material 214 is silicon nitride, a thermal phosphoric acid etch process can be used to pull back the conformal sacrificial material 214 .

FIG. 20 illustrates gate dielectric layer 220 , gate barrier/adjustment layer 222 , gate electrode fill material 224 , and dielectric fill material 226 . Gate dielectric layers 220 are formed on the surfaces of the respective semiconductor layers 210 exposed by the openings 206 and the lateral recesses 218 . The gate dielectric layer 220 can be any suitable dielectric material formed by any suitable process. In some examples, the gate dielectric layer 220 is an oxide formed through an oxidation process (eg, by oxidizing the exposed surface of the semiconductor layer 210 ). In some examples, gate dielectric layer 220 can be another material formed through a conformal deposition process (eg, ALD).

Then, a gate barrier/adjustment layer 222 is conformally formed along the surface of the lateral recess 218 , and a gate electrode fill material 224 is formed on the gate barrier/adjustment layer 222 . In some examples, gate barrier/adjustment layer 222 is formed using a conformal deposition process (eg, ALD). The conformal deposition process can form a conformal layer on the surface defining the opening 206 and the lateral recess 218 (eg, including the gate dielectric layer 220 ). The conductive material of gate electrode fill material 224 can then be deposited on the conformal layer by any suitable deposition process. A node separation process is performed to remove some of the conductive material of the gate electrode fill material 224 and some of the conformal layers of the gate barrier/adjustment layer 222 and the gate barrier/adjustment layer formed in the respective lateral recesses 208 222 and gate electrode fill material 224. The node separation process can include performing an anisotropic etch (eg, RIE) followed by a selective isotropic etch of the gate barrier/adjustment layer 222 and gate electrode fill material 224 materials. The anisotropic etch may remove, for example, the conformal layer of gate barrier/adjustment layer 222 and the gate electrode fill material 224 between the semiconductor layer 210 that defines the opening 206 and the vertical sidewall surfaces of the dielectric fill material 216 . conductive material. The isotropic etch laterally recesses the gate electrode fill material 224 and the gate barrier/adjustment layer 222 to have vertical sidewalls that are offset from the semiconductor layer 210 and the dielectric fill material 216 defining the opening 206 . vertical surface. In some examples, gate barrier/adjustment layer 222 can be any suitable diffusion barrier material and/or can be any work function adjusting material, such as TiN or the like, to adjust the threshold voltage of the transistor. In some examples, gate electrode fill material 224 can be any conductive material, such as a metal such as tungsten.

Then, a dielectric fill material 226 is formed in the remaining unfilled portions of the lateral recesses 208 and openings 206 . The dielectric fill material 226 can be any suitable dielectric material deposited by any suitable deposition process. In some examples, the dielectric fill material 226 is an oxide deposited by a conformal deposition (eg, ALD) or flowable deposition process (eg, FCVD).

In FIG. 21, openings 228 are formed through the film stack (eg, through sacrificial layer 202 and dielectric layer 204). As can be appreciated, each opening 228 is used in the formation of a capacitor that will be electrically connected to a respective transistor of which gate electrode fill material 224 and gate barrier/adjustment layer 222 are part. Each opening 228 is disposed at a certain lateral distance from the corresponding gate electrode filling material 224 and gate barrier/adjustment layer 222 , and the corresponding gate electrode filling material 224 and gate barrier/adjustment layer 222 Disposed laterally between respective openings 228 and where openings 206 are formed (eg, filled with dielectric fill material 226). The openings 228 can be formed by using anisotropic etching (eg, RIE) or the like.

In FIG. 22 , the sacrificial layer 202 is pulled back from the respective openings 228 and the lateral recesses 230 are formed from the respective openings 228 . In some examples, the sacrificial layer 202 is removed through a pullback process. In some examples, such as shown, the pullback process can also remove the conformal sacrificial material 214, such as when the sacrificial layer 202 and the conformal sacrificial material 214 are the same material. The pullback process can be any suitable isotropic etch that selectively etches the sacrificial layer 202 . For example, when the sacrificial layer 202 is silicon nitride, a thermal phosphoric acid etch process can be used to pull back the sacrificial layer 202, and possibly the conformal sacrificial material 214 as well.

FIG. 23 illustrates a conformal dielectric material 232 and a dielectric fill material 234 . Conformal dielectric material 232 can be formed by using conformal deposition (eg, ALD) along the surfaces (eg, dielectric layer 204 , dielectric fill material 216 , and gate resistors) that define opening 228 and lateral recess 230 exposed surface of barrier/adjustment layer 222) conformally deposit the material of conformal dielectric material 232. Dielectric fill material 234 can be deposited over the conformal deposition material of conformal dielectric material 232 by any suitable deposition (eg, by ALD, FCV, etc.) to fill openings 228 and remaining unfilled portions of lateral recesses 230 . The material of the conformal dielectric material 232 and the dielectric fill material 234 can be removed from, for example, between the sidewalls of the dielectric layer 204 defining the openings 228 using anisotropic etching. The conformal dielectric material 232 and the dielectric fill material 234 can be any dielectric material that can be selectively etched relative to each other (eg, the material of the conformal dielectric material 232 and the material of the dielectric fill material 234 ) different). In some examples, the conformal dielectric material 232 is silicon nitride and the dielectric fill material 234 is silicon oxide.

In FIG. 24 , the dielectric layers 204 are pulled back from the openings 228 to the respective semiconductor layers 210 , and lateral recesses 236 are formed from the openings 228 . The pullback process can be any suitable isotropic etch 204 that selectively etches the dielectric layer. For example, when the dielectric layer 204 is silicon oxide, the dielectric layer 204 may be etched using a hydrofluoric acid based process (eg, wet dHF or dry HF process).

At respective lateral recesses 236 , the semiconductor layer 210 is doped at the vertical sidewall surfaces of the semiconductor layer 210 to form source regions 238 . The source region 238 can be doped with an n-type dopant. The doping can be performed using gas-phase dopants and/or plasma-assisted doping processes.

In FIG. 25 , the lateral recess 236 is expanded to form an enlarged lateral recess 240 . Extensions can include isotropic etching that selectively etches the conformal dielectric material 232 . Isotropic etching can be a wet or dry process. In some examples where the conformal dielectric material 232 is silicon nitride, the conformal dielectric material 232 can be etched using a hot phosphoric acid etch process or a dry plasma etch process.

FIG. 26 shows the formation of capacitors in enlarged lateral recesses 240 . Each capacitor includes an outer plate 130 , a capacitor dielectric layer 132 , and an inner plate 134 , as described above with respect to FIG. 11 .

In Figure 27, drain region 242, barrier layer 140 and conductive fill material 142 are formed. Openings are formed through the dielectric fill material 226 . The openings expose vertical sidewalls of the semiconductor layer 210 . The openings can be formed and exposed vertical sidewalls of the semiconductor layer 210 using an etching process. For example, the etching process can include anisotropic etching and/or isotropic etching. The gate dielectric layer 220 previously formed on the vertical sidewalls of the semiconductor layer 210 is removed by an etching process to expose the vertical sidewalls of the semiconductor layer 210 .

Lateral portions of semiconductor layer 210 at respective vertical sidewalls exposed by the openings are doped to form drain regions 242 . The drain region 242 can be doped with an n-type dopant. The doping can be performed using gas-phase dopants and/or plasma-assisted doping processes. With the formation of the drain region 242, individual transistors are formed for the DRAM cells. For each DRAM cell, the transistor includes a source region 238 in semiconductor layer 210 , a drain region 242 in semiconductor layer 210 , a channel region in semiconductor layer 210 between source region 238 and drain region 242 , a first (eg, top) gate structure disposed on the semiconductor layer 210 and positioned above and aligned over the channel region, and a second (eg, top) gate structure positioned on the semiconductor layer 210 and positioned below and aligned above the channel region Bottom) gate structure. Each of the first gate structure and the second gate structure includes a respective gate dielectric layer 220 and a respective gate electrode fill material 224 .

Then, a barrier layer 140 and conductive fill material 142 are formed in the openings, as described for FIG. 12 . Barrier layer 140 and conductive fill material 142 generally form a contact, which may be a bit line node of a DRAM cell. The contacts are along a vertical axis about which the mirrored DRAM pair is mirrored.

28-40 are cross-sectional views of intermediate structures during a second method of forming a 3D DRAM cell according to some examples of the present disclosure. The 3D DRAM cell formed according to the third method of FIGS. 28 to 40 can be as shown in FIG. 3 .

Referring to FIG. 28 , the film stack is deposited on the substrate 100 . The film stack includes multiple cell stacks (eg, two cell stacks in the example shown) that are partially utilized sacrificially to form 3D DRAM cells. As can be seen, this method forms a two-layer 3D DRAM cell. In other examples, cell stacks of repeated film stacks can form additional layers of 3D DRAM cells. Also, an example of using a cell stack in a film stack enables the formation of a one-layer 3D DRAM cell.

The film stack includes a plurality of cell stacks, where the cell stack includes a sacrificial layer 302 and a semiconductor layer 304 . The unit stack of the film stack is the sacrificial layer 302 and the semiconductor layer 304 on the sacrificial layer 302, or consists of both. Two examples of this cell stack are stacked on substrate 100 in FIG. 28 . The sacrificial layers 302 can each be of the same material, and the semiconductor layers 304 can each be of the same material, which is different from the material of the sacrificial layer 302 and has an etch selectivity between the materials of the sacrificial layer 302 . In general, being able to understand the materials of the different layers allows the target layer to be selectively etched during processing. The film stack serves as a mold for forming DRAM cells. In some examples, sacrificial layer 302 is silicon germanium, doped silicon oxide, BPSG, (BSG), PSG, or silicon nitride, and semiconductor layer 304 is silicon (eg, amorphous, polycrystalline, or single crystal, which may be doped) or InGaZnO. In some specific examples, the sacrificial layer 302 is amorphous or crystalline silicon germanium, and the semiconductor layer 304 is amorphous or crystalline silicon. Each of sacrificial layer 302 and semiconductor layer 304 can be deposited by any suitable deposition technique (eg, CVD, PVD, etc.).

In some examples, sacrificial layer 302 and semiconductor layer 304 are semiconductor materials, and further, epitaxial or crystalline (eg, single crystal) semiconductor materials. In some examples, the film stack can be formed by epitaxially growing sacrificial layer 302 on substrate 100, epitaxially growing semiconductor layer 304 on the sacrificial layer, and repeating epitaxially growing sacrificial layer 302 and semiconductor layer 304 to The number of layers to achieve the target in the membrane stack. The use of epitaxial or crystalline (eg, single crystal) materials such as silicon germanium as the sacrificial layer 302 can allow deposition of the sacrificial layer 302 and the semiconductor layer 304 by epitaxial growth, which allows the semiconductor layer 304 (and clearly, including the transistor's Source/drain regions and active regions of the channel region) can be crystalline (eg, single crystal). In some specific examples, the sacrificial layer 302 is epitaxial or crystalline (eg, single crystal) silicon germanium, and the semiconductor layer 304 is epitaxial or crystalline (eg, single crystal) silicon.

In FIG. 29, openings 306 are formed through the film stack (eg, through sacrificial layer 302 and semiconductor layer 304). The openings 306 can be formed by using anisotropic etching (eg, RIE, etc.).

In FIG. 30 , the sacrificial layer 302 is pulled back from the opening 306 and a lateral recess 308 is formed from the opening 306 . The pullback process can be any suitable isotropic etch that selectively etches the sacrificial layer 302 . For example, when the sacrificial layer 302 is silicon germanium, hydrofluoric acid (HF), hydrogen peroxide (H ₂ O ₂ ), and acetic acid (CH ₃ COOH) can be used in 1:2:3 (HF:H ₂ O ₂ :CH ) The sacrificial layer 302 is etched with a mixture of ₃ COOH).

FIG. 31 illustrates a conformal sacrificial material 310 and a dielectric fill material 312 . The conformal sacrificial material 310 can be formed by using a conformal deposition (eg, ALD) that is in common with the surface of the lateral recess 308 (eg, the vertical sidewalls of the sacrificial layer 302 and the exposed surface of the semiconductor layer 304 ) along the defining opening 306 The material of the conformal sacrificial material 310 is formed to be deposited. Dielectric fill material 312 can be deposited over the conformal deposition material of conformal sacrificial material 310 by any suitable deposition (eg, by ALD, FCV, etc.) to fill the remaining unfilled portions of openings 306 and lateral recesses 308 . Materials such as the conformal sacrificial material 310 and the dielectric fill material 312 can be removed from, for example, between the sidewalls of the semiconductor layer 304 that define the openings 306 using anisotropic etching. The conformal sacrificial material 310 can be any sacrificial material, such as a sacrificial dielectric material, and the dielectric fill material 312 can be any dielectric material. In some examples, the conformal sacrificial material 310 is silicon nitride and the dielectric fill material 312 is silicon oxide.

In FIG. 32 , lateral portions of the conformal sacrificial material 310 are pulled back from the openings 306 and lateral recesses 314 are formed from the openings 306 . The dielectric fill material 312 formed on the respective conformal sacrificial material 310 can remain vertically disposed between the lateral recesses 314 formed by pulling back the respective conformal sacrificial material 310 . The pullback process can be any suitable isotropic etch that selectively etches the conformal sacrificial material 310 . For example, when the conformal sacrificial material 310 is silicon nitride, a thermal phosphoric acid etch process can be used to pull back the conformal sacrificial material 310 .

FIG. 33 illustrates gate dielectric layer 220 , gate barrier/adjustment layer 222 , gate electrode fill material 224 and dielectric fill material 226 . Gate dielectric layer 220, gate barrier/adjustment layer 222, and gate electrode fill material 224 are formed in lateral recess 314, as described above for FIG. 20, and dielectric fill material 226 is formed in opening 306, as above The text is described for Figure 20.

In FIG. 34 , openings 315 are formed through the film stack (eg, through sacrificial layer 302 and semiconductor layer 304 ), as described above with respect to FIG. 21 . As can be appreciated, each opening 315 is used in the formation of a capacitor to be electrically connected to a respective transistor of which gate electrode fill material 224 and gate barrier/adjustment layer 222 are part. Each opening 315 is disposed at a certain lateral distance from the corresponding gate electrode filling material 224 and gate barrier/adjustment layer 222 , and the corresponding gate electrode filling material 224 and gate barrier/adjustment layer 222 Disposed laterally between respective openings 315 and where openings 206 are formed (eg, filled with dielectric fill material 226).

In FIG. 35 , the sacrificial layer 302 is pulled back from the respective openings 315 and lateral recesses 316 are formed from the respective openings 315 . In some examples, the sacrificial layer 302 is removed through a pullback process. In some examples, such as shown, the pullback process can also remove the conformal sacrificial material 310, such as when the sacrificial layer 302 and the conformal sacrificial material 310 are the same material. The pullback process can be any suitable isotropic etch that selectively etches the sacrificial layer 302 . For example, when the sacrificial layer 302 is silicon germanium, a mixture of HF, H2O2, and _CH3COOH in a ratio of ₁ : ₂ : ₃ ( _HF :H2O2: _CH3COOH ) can be used to pull back the sacrificial layer 302.

FIG. 36 illustrates conformal dielectric material 232 and dielectric fill material 234 formed in lateral recess 316 . Conformal dielectric material 232 and dielectric fill material 234 can be formed as described above for FIG. 23 .

In FIG. 37 , semiconductor layer 304 is pulled back from opening 315 while lateral recesses 318 are formed from opening 315 . The pullback process can be any suitable isotropic etch that selectively etches the semiconductor layer 304 . For example, when the semiconductor layer 304 is silicon, the semiconductor layer 304 can be pulled back using a TMAH etch process or a dry plasma isotropic etch.

At respective lateral recesses 318, semiconductor layer 304 is doped at vertical sidewall surfaces of semiconductor layer 304 to form source regions 238, as described with respect to FIG.

In FIG. 38 , lateral recess 318 is expanded to form enlarged lateral recess 240 , as described with respect to FIG. 25 . FIG. 39 shows the formation of capacitors in enlarged lateral recesses 240 . Each capacitor includes an outer plate 130 , a capacitor dielectric layer 132 , and an inner plate 134 , as described above with respect to FIG. 11 . In FIG. 40 , drain region 242 , barrier layer 140 and conductive fill material 142 are formed as described for FIG. 27 .

With the formation of the drain region 242, individual transistors are formed for the DRAM cells. For each DRAM cell, the transistor includes source region 238 in semiconductor layer 304 , drain region 242 in semiconductor layer 304 , channel regions in semiconductor layer 304 between source region 238 and drain region 242 , a first (eg, top) gate structure disposed on the semiconductor layer 304 and positioned above and aligned over the channel region, and a second (eg, top) gate structure positioned on the semiconductor layer 304 and positioned below and aligned above the channel region Bottom) gate structure. Each of the first gate structure and the second gate structure includes a gate dielectric layer 220 and a gate electrode filling material 224 . Barrier layer 140 and conductive fill material 142 generally form a contact, which may be a bit line node of a DRAM cell. The contacts are along a vertical axis about which the mirrored DRAM pair is mirrored.

While the foregoing is directed to various exemplars of the present disclosure, other and further exemplars may be devised without departing from the essential scope of the present case, the scope of which is determined by the appended claims.

2: n-type transistor 4: Capacitor 6: Drain node 8: bit line node 10: Source node 12: Gate node 22: n-type transistor 24: Capacitor 26: Semiconductor Materials 28: Drain area 30: source region 32: gate dielectric layer 34: Gate electrode 36: Outer panel 38: Capacitor Dielectric Layer 40: inner panel 42: Bit Wire Contacts 44: Power supply contacts 52: n-type transistor 54: Semiconductor Materials 56: Drain area 58: source region 60: Top gate dielectric layer 62: Bottom gate dielectric layer 64: Top gate electrode 66: Bottom gate electrode 100: Substrate 102: first dielectric layer 104: Semiconductor layer 106: Second Dielectric Layer 108: Opening 110: Transverse recess 112: gate dielectric layer 114: Barrier/Adjustment Layer 116: Gate electrode filling material 118: Dielectric Filler 120: Opening 122: Lateral recess 124: source region 126: Enlarged Lateral Recess 130: outer panel 132: capacitor dielectric layer 134: Inner board 136: Conductive filler material 138: Drain area 140: Barrier Layer 142: Conductive filler material 202: Sacrificial Layer 204: Dielectric Layer 206: Opening 208: Lateral recess 210: Semiconductor layer 212: Transverse recess 214: Conformal Sacrificial Materials 216: Dielectric Filler Materials 218: Lateral recess 220: gate dielectric layer 222: Barrier/Adjustment Layer 224: Gate electrode filling material 226: Dielectric Filler 228: Opening 230: Lateral recess 232: Conformal Dielectric Materials 234: Dielectric Filler Materials 236: Lateral recess 238: source region 240: Enlarged lateral recess 242: Drain area 302: Sacrificial Layer 304: Semiconductor layer 306: Opening 308: Lateral recess 310: Conformal Sacrificial Materials 312: Dielectric Filler Materials 314: Lateral recess 315: Opening 316: Lateral recess 318: Lateral recess

In order that the manner in which the above-described features of the present disclosure can be understood in detail, a more specific description briefly summarized above can be made by reference to examples, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only some examples and should not be construed as limiting the scope of the present disclosure, which may admit to other equivalent examples.

1 is a schematic circuit diagram of a dynamic random access memory (DRAM) cell according to some examples of the present disclosure.

2 is a perspective view of a mirrored DRAM pair according to some examples of the present disclosure.

3 is a perspective view of a mirrored DRAM pair according to some examples of the present disclosure.

4-12 are cross-sectional views of intermediate structures during a first method of forming a 3D DRAM cell according to some examples of the present disclosure.

13-27 are cross-sectional views of intermediate structures during a second method of forming a 3D DRAM cell according to some examples of the present disclosure.

28-40 are cross-sectional views of intermediate structures during a second method of forming a 3D DRAM cell, according to some examples of the present disclosure.

To aid understanding, the same reference numerals have been used, where possible, to designate the same elements that are common to the drawings.

Domestic storage information (please note in the order of storage institution, date and number) none Foreign deposit information (please note in the order of deposit country, institution, date and number) none

100: Substrate

102: first dielectric layer

104: Semiconductor layer

106: Second Dielectric Layer

112: gate dielectric layer

114: Barrier/Adjustment Layer

116: Gate electrode filling material

118: Dielectric Filler

124: source region

130: outer panel

132: capacitor dielectric layer

134: Inner board

136: Conductive filler material

138: Drain area

140: Barrier Layer

142: Conductive filler material

Claims (20)

A method for semiconductor processing, the method comprising: A film stack is formed on a substrate, the film stack includes a plurality of unit stacks, and each unit stack has a first dielectric layer, a semiconductor layer disposed on the first dielectric layer, and a semiconductor layer disposed on the semiconductor layer a second dielectric layer on the layer; forming a first opening through the film stack; pulling the second dielectric layer back from the first opening to form a first lateral recess; forming a gate structure in the first lateral recess and disposed on a portion of the semiconductor layer; A second opening is formed through the film stack, the second opening is laterally arranged from the place where the first opening is formed, and the gate structure is laterally arranged between the second opening and the place where the first opening is formed; pulling the portion of the semiconductor layer back from the second opening to form a second lateral recess; and A capacitor is formed in a region where the second lateral recess is provided, the capacitor contacts the portion of the semiconductor layer. The method of claim 1, further comprising: Extending the second lateral recess includes removing at least some of the first dielectric layer below the second lateral recess and at least some of the second dielectric layer above the second lateral recess, the capacitor being formed in the extended in the second lateral recess. The method of claim 2, wherein forming the capacitor comprises: conformally depositing a first plate along surfaces of the expanded second lateral recess; conformally depositing a capacitor dielectric layer along the first plate; and A second plate is deposited on the capacitor dielectric layer. The method of claim 1, further comprising forming a source/drain region in the portion of the semiconductor layer, comprising: doping the portion of the semiconductor layer through the second lateral recess, wherein a portion of the capacitor A plate is formed to contact the source/drain regions in the portion of the semiconductor layer. The method of claim 1, further comprising: forming a source/drain region in the portion of the semiconductor layer, comprising: doping the portion of the semiconductor layer; and A contact is formed that extends through the film stack and contacts the source/drain region. A method for semiconductor processing, the method comprising: forming a film stack on a substrate, the film stack including a plurality of unit stacks, each unit stack having a first layer and a second layer disposed on the first layer; forming a first opening through the film stack; pulling the first layer back from the first opening to form a first lateral recess; forming a first conformal layer in the first lateral recess; forming a first filler material on the first conformal layer and in the first lateral recess; pulling the first conformal layer back from the first opening to form a second lateral recess; forming a gate structure in the second lateral recess and disposed on and below a semiconductor layer, the semiconductor layer being horizontally aligned with the second layer; A second opening is formed through the film stack, the second opening is laterally arranged from the place where the first opening is formed, and the gate structure is laterally arranged between the second opening and the place where the first opening is formed; pulling the second layer back from the second opening to form a third lateral recess into the semiconductor layer; and A capacitor is formed in a region where the third lateral recess is provided, the capacitor being in contact with the semiconductor layer. The method of claim 6, further comprising: pulling the second layer back from the first opening to form a fourth lateral recess; and The semiconductor layer is formed in the fourth lateral recess. The method of claim 6, wherein the second layer is a semiconductor material and the semiconductor layer is part of the second layer. The method of claim 6, wherein the first layer is a first dielectric material, the second layer is a second dielectric material, the first dielectric material and the second dielectric material relative to each other Optionally removed. The method of claim 6, wherein the first layer is a first dielectric material, and the second layer is a second dielectric material different from the first dielectric material, the first dielectric material and the second dielectric material is selected from the group consisting of silicon nitride, silicon oxide, doped silicon oxide, borophosphosilicate glass (BPSG), and phosphosilicate Glass (PSG). The method of claim 6, wherein the first layer is a first semiconductor material and the second layer is a second semiconductor material different from the first semiconductor material. The method of claim 11, wherein the first semiconductor material and the second semiconductor material are amorphous. The method of claim 11, wherein the first semiconductor material and the second semiconductor material are epitaxial or monocrystalline. The method of claim 6, wherein forming the film stack comprises: epitaxially growing the first layer; and The second layer is epitaxially grown on the first layer. The method of claim 6, wherein the first layer is silicon germanium and the second layer is silicon. The method of claim 6, wherein the first layer is epitaxial silicon germanium, and the second layer is epitaxial silicon. The method of claim 6, wherein the first layer is amorphous silicon germanium, and the second layer is amorphous silicon. The method of claim 6, further comprising: Pulling back the first layer from the second opening to form a fourth lateral recess; forming a second conformal layer in the fourth lateral recess; and A second filler material is formed on the second conformal layer and in the fourth lateral recess. The method of claim 18, further comprising expanding the third lateral recess, including removing at least some of the second conformal layer, the capacitor formed in the expanded third lateral recess. A method for semiconductor processing, the method comprising: forming a film stack on a substrate, the film stack including at least five layers, each of the at least five layers being formed from a material selected from the group of materials including no more than three different materials; and Using the film stack as a mold, pairs of vertically stacked mirrored DRAM pairs are formed on the substrate, each of the vertically stacked mirrored DRAM pairs including: a contact; a first transistor including a first gate structure, a first source/drain region and a second source/drain region, the first source/drain region contacting the contact; a second transistor including a second gate structure, a third source/drain region and a fourth source/drain region, the third source/drain region contacts the contact, the first The second transistor mirrors the first transistor around the contact; a first capacitor having a first outer plate, a first capacitor dielectric layer and a first inner plate, the first outer plate contacting the second source/drain region; and A second capacitor has a second outer plate, a second capacitor dielectric layer and a second inner plate, the second outer plate contacts the fourth source/drain region.

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