TW202324679A - 具有三維小晶片結構的系統晶片以及包括所述系統晶片的電子裝置 - Google Patents

具有三維小晶片結構的系統晶片以及包括所述系統晶片的電子裝置 Download PDF

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Publication number
TW202324679A
TW202324679A TW111136169A TW111136169A TW202324679A TW 202324679 A TW202324679 A TW 202324679A TW 111136169 A TW111136169 A TW 111136169A TW 111136169 A TW111136169 A TW 111136169A TW 202324679 A TW202324679 A TW 202324679A
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Taiwan
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die
system chip
electronic device
memory device
substrate
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TW111136169A
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English (en)
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尹隊瀚
李慶民
許峻豪
李稀裼
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南韓商三星電子股份有限公司
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Publication of TW202324679A publication Critical patent/TW202324679A/zh

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Abstract

本揭露提供一種具有三維（3D）小晶片結構的系統晶片 （SoC）以及電子裝置。所述電子裝置包含：印刷電路板、在印刷電路板上的系統晶片以及在系統晶片上的記憶體裝置，其中系統晶片包含：系統晶片封裝基板、設置在系統晶片封裝基板上且其上具有邏輯電路的第一晶粒以及設置在第一晶粒上且其上具有邏輯電路的第二晶粒。

Description

具有三維小晶片結構的系統晶片以及包括所述系統晶片的電子裝置
[ 相關申請的交叉引用 ]
本申請基於2021年9月24日在韓國智慧財產局提交的韓國專利申請第10-2021-0126724號並主張此申請的優先權，所述申請的揭露內容以全文引用的方式併入本文中。
本發明構思是關於積體電路（integrated circuit IC），更具體地，是關於具有三維（3D）小晶片結構的系統晶片，以及包含系統晶片的電子裝置。
在半導體工業中，對半導體元件及使用該半導體元件的電子產品的高容量化、薄型化及小型化的需求增加，並且與此相關的各種封裝技術不斷出現。電子裝置的半導體封裝是藉由使用適合在電子產品中使用的形式的IC晶片來實施。通常，在半導體封裝中，半導體晶片安裝在印刷電路板（printed circuit board，PCB）上，並藉由接合線或凸塊電連接到PCB。由於電子工業的進步，已增加對電子裝置的高功能、高速及小型化的需求。
本發明構思提供一種例如，尺寸減小、功耗降低等性能得到改進的系統晶片（system on chip，SoC），以及一種包含所述系統晶片的電子裝置。
根據本發明構思的一些示例實施例，提供一種電子裝置，所述電子裝置包含：印刷電路板；設置在所述印刷電路板上的系統晶片；以及在所述系統晶片上的記憶體裝置，其中所述系統晶片包含：系統晶片封裝基板； 在系統晶片封裝基板上且其上具有邏輯電路的第一晶粒；以及在第一晶粒上且其上具有邏輯電路的第二晶粒。
根據本發明構思的一些示例實施例，提供一種電子裝置，所述電子裝置包含：印刷電路板；在印刷電路板上且包含至少一個其上具有邏輯電路的邏輯晶粒的系統晶片；在所述系統晶片上的記憶體裝置；以及在從至少一個邏輯晶粒到記憶體裝置的方向上垂直延伸以將至少一個邏輯晶粒電連接到記憶體裝置的互連通孔。
根據本發明構思的一些示例實施例，提供一種具有三維（3D）小晶片結構的系統晶片，所述系統晶片包含：系統晶片封裝基板；第一晶粒，藉由使用第一凸塊在所述系統晶片封裝基板上，且其上具有第一邏輯電路；以及第二晶粒，在所述第一晶粒上，且其上具有第二邏輯電路。其中所述第一邏輯電路及所述第二邏輯電路從在所述系統晶片封裝基板上的電壓調節器經由輸出電壓路徑接收輸出電壓，且多個功能塊在所述第一晶粒及所述第二晶粒中的至少一個上。
在下文中，結合隨附圖式描述本發明構思的各種實施例。
圖1及圖2分別是根據示例實施例的電子裝置10及電子裝置10A的方塊圖。
參照圖1，電子裝置10可包括系統晶片（system on chip，SoC）100、記憶體裝置200、電源管理積體電路（power management integrated circuit，PMIC）300及電壓調節器VR。電子裝置10可包括智慧型手機、智慧型手錶、個人數位助理、數位攝影機、數位相機、網絡系統、計算機、顯示器、平板電腦、膝上型電腦、小筆電、電視、電動遊戲、汽車等。然而，示例實施例不限於此，此外，電子裝置10還可包括處理數據的任意電子裝置。
PMIC 300可通過輸入電壓路徑VIP向電壓調節器VR提供輸入電壓Vin。電容器Cin可連接到輸入電壓路徑VIP，使得輸入電壓Vin藉由PMIC 300穩定地提供給電壓調節器VR。例如，PMIC 300可包括直流（DC）-DC轉換器，例如降壓轉換器、升壓轉換器及降壓-升壓轉換器。
電壓調節器VR可接收輸入電壓Vin，並產生輸出電壓Vout以用於系統晶片100的操作。電壓調節器VR可經由輸出電壓路徑VOP將輸出電壓Vout提供給系統晶片100。例如，可將輸出電壓Vout提供給系統晶片100的記憶體控制器110。
電壓調節器VR可包括諸如低壓差（low-dropout，LDO）調節器的DC線性調節器及高帶寬調節器。輸出電壓Vout在圖1中被示為一電壓，但可包括多於一電壓。
系統晶片100可藉由使用記憶體裝置200來執行電子裝置10支持的應用。系統晶片100也可稱為主機、應用處理器（application processor，AP）等。系統晶片100可控制記憶體裝置200，並且包括連同記憶體裝置200執行數據輸入/輸出的記憶體控制器110。例如，記憶體控制器110可以直接記憶體存取（direct memory access，DMA）方法接近記憶體裝置200。
記憶體控制器110可包括電連接到記憶體裝置200的介面電路210的介面電路111。記憶體控制器110的介面電路111可經由訊號路徑DP將數據輸入/輸出訊號DQ發送到記憶體裝置200或從記憶體裝置200接收數據輸入/輸出訊號DQ，即訊號路徑DP可包括數據路徑。或者，介面電路111可經由訊號路徑DP向記憶體裝置200發送以下中的至少一個：命令（例如，圖11中的CMD）、位址（例如，圖11中的ADD）、時脈（例如，圖11中的CK）及其他控制訊號。
除了記憶體控制器110之外，系統晶片100可更包含處理器等。下面參照圖11描述系統晶片100的詳細示例配置。
在一些示例實施例中，電壓調節器VR可安裝在系統晶片100的系統晶片封裝基板上。因此，在根據本發明構思的電子裝置10中，可減少用於補償輸出電壓路徑VOP的電壓降（或IR降）的電容器的數量，並且可減少將系統晶片100電連接到印刷電路板的凸塊的數量。
記憶體裝置200可經由訊號路徑DP接收數據輸入/輸出訊號DQ或發送數據輸入/輸出訊號DQ，並可接收命令CMD、位址ADD、時脈CK或其他控制訊號。例如，記憶體裝置200可包含諸如動態隨機存取記憶體（RAM）（dynamic random-access memory，DRAM）元件及靜態RAM（static RAM，SRAM）元件的揮發性記憶體元件，以及諸如相變RAM（phase-change RAM，PRAM） 元件、磁阻RAM（magnetoresistive RAM，MRAM）元件、鐵電RAM（ferroelectric RAM，FeRAM）元件及電阻RAM（resistive RAM，RRAM）元件的非揮發性記憶體元件。例如，記憶體裝置200可包含高帶寬記憶體（HBM）DRAM元件。下面參照圖10描述記憶體裝置200的詳細示例配置。
在一些示例實施例中，系統晶片100及記憶體裝置200中的每一個可構成半導體封裝，並且電子裝置10可具有記憶體裝置200設置在系統晶片100上的封裝上封裝（package on package，PoP）結構。
參照圖2，與圖1的電子裝置10相比，電子裝置10A可包含系統晶片100A，系統晶片100A包含電壓調節器VR。在一些示例實施例中，系統晶片100A可包含多個垂直堆疊的晶粒，並且電壓調節器VR可形成在包含在系統晶片100A中的多個晶粒中的至少一個上。因此，在根據本發明構思的電子裝置10A中，可減少用於補償輸出電壓路徑VOP的電壓降（或IR降）的電容器的數量，並且可減少將系統晶片100A電連接到印刷電路板的凸塊的數量。
圖3A是根據一些示例實施例的電子裝置的剖視圖。圖3B是圖3A的區域A的放大剖視圖。
參照圖3A，電子裝置（例如，圖1的10）可包含印刷電路板PSUB，並且系統晶片100及記憶體裝置200可設置在印刷電路板PSUB上。系統晶片100及記憶體裝置200中的每一個可實施為半導體封裝，並且可作為PoP類型的半導體封裝設置在印刷電路板PSUB上。
印刷電路板PSUB可經由外部連接端子SB電連接到母板，並且可電連接到PMIC 300及電容器Cin。外部連接端子SB可包含例如焊球或焊料凸塊。在圖3A中，電容器Cin被示為在印刷電路板PSUB外部電連接到印刷電路板PSUB，但是示例實施例不限於此，電容器Cin也可形成在印刷電路板PSUB內部。
印刷電路板PSUB可在其中包含連接佈線及通孔。印刷電路板PSUB可設置包含在輸入電壓路徑VIP中的連接佈線及通孔，並且可將PMIC 300電連接到電壓調節器VR。連接佈線及通孔中的每一個可包含金屬材料，例如鎢（W）、銅（Cu）、鈦（Ti）、鉭（Ta）、釕（Ru）、錳（Mn）及鈷（Co）、諸如Ti、Ta、Ru、Mn、Co 及W的金屬的氮化物或氧化物、鈷磷化鎢（CoWP）、鈷鎢硼（CoWB）、鈷鎢硼磷化物（CoWBP）或其組合。
印刷電路板PSUB可包含圍繞連接佈線及通孔的佈線絕緣層，並且可包含以下中的至少一個：氧化矽（SiO）、氮化矽（SiN）、碳氮化矽（SiCN）、碳氧化矽（SiOC）、高分子材料及介電常數比SiO低的絕緣材料。
系統晶片100可包含系統晶片封裝基板SSUB，以及安裝在系統晶片封裝基板SSUB上的至少一個邏輯晶粒，例如，第一晶粒DIE1及第二晶粒DIE2。系統晶片封裝基板SSUB可經由內部連接端子BP電連接到印刷電路板PSUB。
多個邏輯晶粒可在垂直於系統晶片封裝基板SSUB的主表面的方向上堆疊在系統晶片封裝基板SSUB上。例如，第二晶粒DIE2可設置在第一晶粒DIE1上，第一晶粒DIE1可通過第一凸塊BP1電連接到系統晶片封裝基板SSUB，並且第二晶粒DIE2可通過第二凸塊BP2電連接到第一晶粒DIE1及系統晶片封裝基板SSUB。在圖3A中，示出兩個邏輯晶粒（即，第一晶粒DIE1及第二晶粒DIE2）依序堆疊在系統晶片封裝基板SSUB上的示例，但是根據本發明構思的電子裝置10不限於此，也可在系統晶片封裝基板SSUB上依序堆疊三個或更多的邏輯晶粒。
當系統晶片100包含多個垂直堆疊的邏輯晶粒時，可減少系統晶片100在印刷電路板PSUB上所佔據的面積，即可減少平台形狀因數（platform form factor）。此外，可減少將系統晶片100電連接到印刷電路板PSUB的內部連接端子BP的數量。
系統晶片100中包含的邏輯電路可實施在第一晶粒DIE1及第二晶粒DIE2上，並且可實施多個智慧財產權（intellectual property，IP）。例如，參照圖11描述的系統晶片1000的每個組件都可實施在第一晶粒DIE1及第二晶粒DIE2上。例如，第一晶粒DIE1及第二晶粒DIE2可包含處理器及記憶體控制器（例如，圖1中的110）。
第一晶粒DIE1可包含第一基板SUB1及第一主動層ACL1。第一邏輯電路可形成在第一主動層ACL1上。例如，第一主動層ACL1可包含多個第一半導體元件，以及在多個第一半導體元件上的佈線層。
第二晶粒DIE2可包含第二基板SUB2及第二主動層ACL2。第二邏輯電路可形成在第二主動層ACL2上。例如，第二主動層ACL2可包含形成在第二基板SUB2上的多個第二半導體元件，以及在多個第二半導體元件上的佈線層。第一主動層ACL1及第二主動層ACL2中的每一個的佈線層可包含金屬佈線層及通孔塞。
第一基板SUB1及第二基板SUB2中的每一個可包含例如矽（Si）。或者，第一基板SUB1及第二基板SUB2中的每一個可包含諸如鍺（Ge）的半導體元素，或者諸如碳化矽（SiC）、砷化鎵（GaAs）、砷化銦（InAs），以及磷化銦（InP）的化合物半導體。
形成在第一主動層ACL1上的第一半導體元件及形成在第二主動層ACL2上的第二半導體元件可包含微電子元件，例如金屬氧化物半導體場效應電晶體（metal-oxide-semiconductor field effect transistor，MOSFET）、系統大型積體電路（large scale integration，LSI）、影像感測器（諸如互補金屬氧化物半導體（CMOS）成像感測器（CIS））、微機電系統（micro-electro-mechanical system，MEMS）、主動元件、被動元件等。
在一些示例實施例中，第一晶粒DIE1的第一主動層ACL1及第二晶粒DIE2的第二主動層ACL2可面對面設置。此外，在一些示例實施例中，相對靠近系統晶片封裝基板SSUB設置的第一晶粒DIE1的尺寸可大於第二晶粒DIE2的尺寸。
系統晶片100可包含圍繞第一晶粒DIE1及第二晶粒DIE2的模製層101。模製層101可保護第一晶粒DIE1及第二晶粒DIE2免受諸如衝擊及污染的外部影響。為了進行保護，模製層101可包含環氧模製化合物或樹脂等。此外，模製層101可藉由諸如壓縮模製、層壓、絲網印刷等程序形成。然而，即使模製層101在圖3A中被示為不圍繞電壓調節器VR，但示例實施例不限於此，模製層101也可形成為圍繞電壓調節器VR。
在一些示例實施例中，電壓調節器VR可包含積體電壓調節器IVR，其安裝在系統晶片封裝基板SSUB上。換句話說，第一晶粒DIE1及電壓調節器VR可在相同的平面上彼此平行地設置。電壓調節器VR可經由第三凸塊BP3電連接到系統晶片封裝基板SSUB。系統晶片封裝基板SSUB可設置包含在電壓調節器VR的輸入電壓路徑VIP中的連接佈線及通孔，此外，可設置包含在電壓調節器VR的輸出電壓路徑VOP中的連接佈線及通孔。儘管電壓調節器VR在圖3A被示為設置在作為參照的第一晶粒DIE1的右側上，示例實施例不限於此，電壓調節器VR也可設置在作為參照的第一晶粒DIE1的左側上。
在根據本發明構思的電子裝置10中，藉由包含安裝在系統晶片封裝基板SSUB上的電壓調節器VR，可縮短電壓調節器VR的輸出電壓路徑VOP的總長度。例如，當預想根據比較示例的電壓調節器VR連接到印刷電路板PSUB的外部連接端子SB時，印刷電路板PSUB內部的電壓傳輸線可形成為使得輸出電壓Vout被傳輸到系統晶片100，並且由於電壓傳輸線的長度，可能會發生電壓降（或IR降）。因此，在根據本發明構思的電子裝置10中，藉由包含安裝在系統晶片封裝基板SSUB上的電壓調節器VR，可減少用於形成輸出電壓路徑VOP的面積，並可減少且用於補償輸出電壓路徑VOP的電壓降的電容器的數量。
中介層基板IS可包含重佈線基板，並且可配置成將系統晶片100電連接到記憶體裝置200。佈線層及將佈線層彼此連接的通孔可形成在中介層基板IS中。中介層基板IS的第一表面可面向系統晶片100，並且面向中介層基板IS的第一表面的第二表面可面向記憶體裝置200。
記憶體裝置200可設置在中介層基板IS上，並且可經由互連端子IM電連接到中介層基板IS。記憶體裝置200可具有堆疊多個記憶體晶粒的結構。例如，記憶體裝置200可具有多個記憶體晶粒堆疊在緩衝晶粒上的結構。
參照圖3A及圖3B，系統晶片100可經由互連通孔IV將數據輸入/輸出訊號（例如，圖1中的DQ）、控制訊號及時脈中的至少一個發送到記憶體裝置200。換句話說，訊號路徑DP可包含互連通孔IV。
在一些示例實施例中，互連通孔IV可包含貫穿中介層基板IS的矽穿孔（TSV）及貫穿模製層101的模穿孔（TMV）。
在一些示例實施例中，包含在系統晶片100的記憶體控制器（例如，圖1中的110）中的介面電路（例如，圖1中的111）可形成在第一晶粒DIE1的第一主動層ACL1上。互連通孔IV可形成為在垂直方向上從第一主動層ACL1延伸到互連端子IM，以將形成在第一主動層ACL1上的介面電路111電連接到記憶體裝置200。然而，與所示出的不同，介面電路111也可形成在第二晶粒DIE2上，並且互連通孔IV也可形成為接觸第二晶粒DIE2的第二主動層ACL2。
互連通孔IV可包含Cu、銅錫（CuSn）、銅鎂（CuMg）、銅鎳（CuNi）、銅鋅（CuZn）、銅鈀（CuPd）、銅金（CuAu）、銅錸（CuRe）、銅鎢（CuW）、W或W合金，但不限於此。互連通孔IV可包含Al、Au、鈹（Be）、鉍（Bi）、鈷（Co）、Cu、鉿（Hf）、銦（In）、Mn、鉬（Mo）、Ni、鉛 （Pb）、Pd、鉑（Pt）、銠（Rh）、Re、Ru、Ta、碲（Te）、Ti、W、Zn 及鋯（Zr），並且可包含一個或兩個以上的堆疊結構。
在根據本發明構思的電子裝置10中，連接到系統晶片100及記憶體裝置200的訊號路徑DP可形成為經由互連通孔IV直接連接到系統晶片100及記憶體裝置200，而不通過系統晶片封裝基板SSUB。因此，當用於形成訊號路徑DP的佈線區域的尺寸減少並且訊號路徑DP的長度減少時，可減少訊號路徑DP中的功耗，並且可減少訊號路徑DP中的電磁干擾（EMI）的發生可能性。換句話說，可改善電子裝置10的特性。
圖4A是根據一些示例實施例的電子裝置的剖視圖。圖4B是圖4A的區域B的放大剖視圖。在參照圖4A的描述中，省略與圖3中相同的元件符號的重複描述。
參照圖4A及圖4B，系統晶片100可經由訊號路徑DP'將數據輸入/輸出訊號（例如，圖1中的DQ）、控制訊號及時脈中的至少一個發送到記憶體裝置200。此外，系統晶片100可經由訊號路徑DP'從記憶體裝置200接收數據輸入/輸出訊號DQ。
訊號路徑DP'可包含互連通孔IV'及中介層基板IS的內部佈線IW。互連通孔IV'可包含貫穿模製層101的模穿孔。
中介層基板IS的內部佈線IW可包含上部接墊P1、下部接墊P2及垂直內部佈線CP。中介層基板IS的上部接墊P1可連接到互連端子IM，及中介層基板IS的下部接墊P2可連接到互連通孔IV'。
可在中介層基板IS中形成至少一個佈線層。垂直內部佈線CP可在中介層基板IS的垂直方向上延伸，以將上部接墊P1連接到至少一個佈線層，或者將下部接墊P2連接到至少一個佈線層。此外，垂直內部佈線CP可在垂直方向上延伸以將不同的佈線彼此連接。在一些示例實施例中，訊號路徑DP'的內部佈線IW可形成在中介層基板IS的至少一個佈線層上，並且可更包含在中介層基板IS的水平方向上延伸的水平內部佈線。
在一些示例實施例中，中介層基板IS的上部接墊P1及下部接墊P2可包含Cu、Ni、不銹鋼及BeCu中的至少一種。在一些示例實施例中，中介層基板IS的垂直內部佈線CP或水平內部佈線可包含金屬，例如Cu、Ni、Au、銀（Ag）、鋁（Al）、W、Ti、Ta、In、Mo、Mn、Co、Sn、Mg、Re、Be、Ga及Ru，或其組合。
圖5及圖6是根據示例實施例的電子裝置的剖視圖。圖5及圖6是電子裝置中的SoC、電壓調節器及記憶體裝置的詳圖，並在參照圖5及圖6給出的描述中省略了與圖3A相同的元件符號的重複描述。圖5中的系統晶片100及圖6中的系統晶片100A可分別以與圖3A中的系統晶片100相同的方式安裝在印刷電路板（圖3A中的PSUB）上。
參照圖5，電壓調節器VR可設置在第一晶粒DIE1上。換句話說，電壓調節器VR可與第二晶粒DIE2平行設置在相同的平面上。電壓調節器VR可經由接觸第一晶粒DIE1的第三凸塊BP3a電連接到第一晶粒DIE1。或者，與圖5所示的不同，電壓調節器VR可與第二晶粒DIE2平行設置，但也可經由接觸系統晶片封裝基板SSUB的凸塊電連接到系統晶片封裝基板SSUB。
參照圖6，系統晶片100A可包含電壓調節器VR。例如，電壓調節器VR也可嵌置在第一晶粒DIE1或第二晶粒DIE2中。因此，輸出電壓路徑VOP的總長度可相對進一步減少。
圖7至圖9是根據示例實施例的電子裝置的剖視圖。圖7至圖9是電子裝置中的系統晶片、電壓調節器及記憶體裝置的詳圖，並且在參照圖7至圖9給出的與圖3中相同的元件符號的重複描述將省略。圖7至圖9中的系統晶片100可以與圖3A中的系統晶片100相同的方式安裝在印刷電路板（圖3A中的PSUB）上。
參照圖7，第一晶粒DIE1可包含第一基板SUB1及第一主動層ACL1，及第二晶粒DIE2可包含第二基板SUB2及第二主動層ACL2。第一晶粒DIE1的第一主動層ACL1及第二晶粒DIE2的第二主動層ACL2可面對背設置。例如，第一晶粒DIE1的第一主動層ACL1可設置為面向系統晶片封裝基板SSUB，並且第二晶粒DIE2的第二主動層ACL2可設置為面向第一晶粒DIE1。
系統晶片100可經由互連通孔IVa將數據輸入/輸出訊號（例如，圖1中的DQ）收發（發送及/或接收）到記憶體裝置200及從記憶體裝置200收發（發送及/或接收）數據輸入/輸出訊號。換句話說，訊號路徑（例如，圖1中的DP）可包含互連通孔IVa。互連通孔IVa可包含貫穿中介層基板IS的矽穿孔、貫穿模製層101的模穿孔、以及貫穿第一晶粒DIE1的第一基板SUB1的矽穿孔。在一些示例實施例中，包含在系統晶片100的記憶體控制器（例如，圖1中的110）中的介面電路（例如，圖1中的111）可形成在第一晶粒DIE1的第一主動層ACL1上。互連通孔IVa可形成為在垂直方向上從第一主動層ACL1延伸到互連端子IM，以將形成在第一主動層ACL1上的介面電路111電連接到記憶體裝置200。或者，如上面參照圖4A及圖4B所描述的，訊號路徑也可包含在中介層基板IS內部的內部佈線。
如上面參照圖3A、圖5及圖6所描述的，電壓調節器VR也可安裝在系統晶片封裝基板SSUB上，或者安裝在第一晶粒DIE1上，或者也可形成在第一晶粒DIE1及第二晶粒DIE2中的至少一個中。
參照圖8，相對靠近系統晶片封裝基板SSUB設置的第一晶粒DIE1的尺寸可小於第二晶粒DIE2的尺寸。第一晶粒DIE1的第一主動層ACL1及第二晶粒DIE2的第二主動層ACL2可面對面設置。
系統晶片100可經由互連通孔IVb將數據輸入/輸出訊號DQ收發到記憶體裝置200及從記憶體裝置200收發數據輸入/輸出訊號DQ。換句話說，訊號路徑DP可包含互連通孔IVb，並且互連通孔IVb可包含貫穿中介層基板IS的矽穿孔、貫穿模製層101的模穿孔以及貫穿第二晶粒DIE2的第二基板SUB2的矽穿孔。或者，如上面參照圖4A及圖4B所描述的，訊號路徑也可包含在中介層基板IS內部的內部佈線。
在一些示例實施例中，包含在系統晶片100的記憶體控制器110中的介面電路111可形成在第二晶粒DIE2的第二主動層ACL2上。互連通孔IVb可形成為在垂直方向上從第二主動層ACL2延伸到互連端子IM，以將形成在第二主動層ACL2上的介面電路111電連接到記憶體裝置200。然而，示例實施例不限於此，介面電路111也可形成在第一晶粒DIE1的第一主動層ACL1上，並且訊號路徑DP也可包含連接到互連通孔IVb的第一主動層ACL1及第二主動層ACL2中的每一個的佈線以及第二凸塊BP2。或者，如上面參照圖4A及圖4B所描述的，訊號路徑也可包含在中介層基板IS內部的內部佈線。
參照圖9，相對靠近系統晶片封裝基板SSUB設置的第一晶粒DIE1的尺寸可小於第二晶粒DIE2的尺寸。第一晶粒DIE1的第一主動層ACL1及第二晶粒DIE2的第二主動層ACL2可面對背設置。例如，第一晶粒DIE1的第一主動層ACL1可設置為面向系統晶片封裝基板SSUB，並且第二晶粒DIE2的第二主動層ACL2可設置為面向第一晶粒DIE1。
系統晶片100可經由互連通孔IVb將數據輸入/輸出訊號DQ收發到記憶體裝置200及從記憶體裝置200收發數據輸入/輸出訊號DQ。換句話說，訊號路徑DP可包含互連通孔IVb。或者，如上面參照圖4A及圖4B所描述的，訊號路徑也可包含在中介層基板IS內部的內部佈線。
在一些示例實施例中，包含在系統晶片100的記憶體控制器110中的介面電路111可形成在第二晶粒DIE2的第二主動層ACL2上。互連通孔IVb可形成為在垂直方向上從第二主動層ACL2延伸到互連端子IM，以將形成在第二主動層ACL2上的介面電路111電連接到記憶體裝置200。然而，示例實施例不限於此，介面電路111也可形成在第一晶粒DIE1的第一主動層ACL1上，並且訊號路徑DP也可包含連接到互連通孔IVb的第一主動層ACL1及第二主動層ACL2中的每一個的佈線、貫穿第一基板SUB1的矽穿孔以及第二凸塊BP2。
圖10是根據一些示例實施例的包括在電子裝置中的記憶體裝置200的剖視圖。
參照圖10，記憶體裝置200可包含三維（3D）堆疊記憶體裝置。記憶體裝置200可包含緩衝晶粒220，以及堆疊在緩衝晶粒220上的多個記憶體晶粒，例如，第一記憶體晶粒230_1至第n記憶體晶粒230_n。n可包含等於或大於3的自然數，例如4或8，或者可為可各樣變化的。緩衝晶粒220及第一記憶體晶粒230_1至第n記憶體晶粒230_n可配置在一個半導體封裝中。
記憶體裝置200可包含貫穿緩衝晶粒220及第一記憶體晶粒230_1至第n記憶體晶粒230_n的貫通孔TV，以及將貫通孔TV彼此電連接的微凸塊MBP。貫通孔TV及微凸塊MBP可提供緩衝晶粒220與記憶體裝置200中的第一記憶體晶粒230_1到第n記憶體晶粒230_n之間的電路徑。貫通孔TV及微凸塊MBP的數量不限於圖10所示，而可進行各種變化。第n記憶體晶粒230_n可不包含貫通孔TV，但不特別限於此。
第一記憶體晶粒230_1至第n記憶體晶粒230_n中的每一個可包含動態隨機存取記憶體（RAM）（DRAM）晶片。例如，第一記憶體晶粒230_1至第n記憶體晶粒230_n中的每一個可包含諸如雙倍數據速率（DDR）同步DRAM（DDR SDRAM）的通用DRAM裝置、諸如低功率（LP）DDR（LPDDR）SDRAM的行動DRAM裝置、諸如圖形DDR（GDDR）同步圖形RAM（SGRAM）的圖形DRAM裝置、提供高容量及高帶寬的寬輸入/輸出（input/output，I/O）、諸如高帶寬記憶體（high bandwidth memory，HBM）的DRAM裝置、HBM2、HBM3及混合記憶體立方體（hybrid memory cube HMC）。然而，示例實施例不限於此，並且第一記憶體晶粒230_1至第n記憶體晶粒230_n中的每一個也可包含沒有DRAM裝置的揮發性記憶體裝置，或者也可包含非揮發性記憶體裝置。
根據一些示例實施例，第一記憶體晶粒230_1至第n記憶體晶粒230_n可具有實質相同的晶片尺寸。換句話說，第一記憶體晶粒230_1到第n記憶體晶粒230_n可具有實質相同的平面形狀及相同的平面尺寸。
緩衝晶粒220可執行以下介面操作：將從記憶體控制器（例如，圖1中的110）接收的數據輸入/輸出訊號、命令、位址、晶片選擇訊號等提供給第一記憶體晶粒230_1至第n記憶體晶粒230_n，或者將從第一記憶體晶粒230_1至第n記憶體晶粒230_n接收的數據輸入/輸出訊號提供給記憶體控制器110。為了執行介面操作，緩衝晶粒220可包含實體層（physical layer，PHY）210或介面電路。實體層210可對應於圖1及圖2中的介面電路210。
圖11是根據一些示例實施例的包含在電子裝置中的系統晶片1000的方塊圖。
參照圖11，系統晶片1000可對應於上述系統晶片（例如，圖1中的100及圖2中的100A）。系統晶片1000可包含處理器1100、快取記憶體1200、記憶體控制器1300及匯流排1500。匯流排1500可提供處理器1100、快取記憶體1200與記憶體控制器1300之間的通訊路徑。處理器1100可執行加載在快取記憶體1200上的各種軟體（應用程式、操作系統、文件系統、裝置驅動器等）。
處理器1100可包含相同類型的多核或不同類型的多核。例如，處理器1100可包含中央處理單元（central processing unit，CPU）、影像訊號處理單元（image signal processing unit，ISP）、數位訊號處理單元（digital signal processing unit，DSP）、圖形處理單元（graphics processing unit，GPU）、視覺處理單元（vision processing unit，VPU）及神經處理單元（neural processing unit，NPU）中的任一個，且處理器1100的數量可為一個或多個。
在快取記憶體1200中，可加載用於驅動電子裝置（例如，圖1的10及圖2的10A）的應用程式、操作系統、文件系統、裝置驅動器等。例如，快取記憶體1200可包含具有比記憶體裝置（例如，圖1中的200）更快的數據輸入/輸出速度的SRAM裝置。
記憶體控制器1300可以直接記憶體存取（direct memory access，DMA）方法存取記憶體裝置200。記憶體控制器1300可包含命令（CMD）佇列1310、命令（CMD）排程器1320、讀取數據佇列1330、寫入數據佇列1340及實體層1400。記憶體控制器1300可對應於圖1及圖2中的記憶體控制器110，且實體層1400可對應於圖1及圖2中的介面電路111。記憶體控制器1300的組件（1310到1340及1400）可藉由使用系統晶片1000中的硬體方法、軟體方法或其組合來實施。
CMD佇列1310可儲存由處理器1100發布或根據處理器1100的控制生成的命令及位址。基於CMD排程器1320的控制，可將儲存在CMD佇列1310中的命令及位址提供給實體層1400。
CMD排程器1320可調整儲存在CMD佇列1310中的命令及位址的序列、命令及位址輸入到CMD佇列1310的時間點、命令及位址由CMD佇列1310輸出的時間點等。
讀取數據佇列1330可儲存藉由使用讀取命令經由實體層1400由記憶體裝置200發送的讀取數據。儲存在讀取數據佇列1330中的讀取數據可提供給快取記憶體1200，並且可由處理器1100處理。
寫入數據佇列1340可儲存要儲存在記憶體裝置200中的寫入數據。藉由使用寫入命令儲存在寫入數據佇列1340中的寫入數據可經由實體層1400被發送到記憶體裝置200。
實體層1400可包含時脈（CK）產生器1410、命令/位址（CMD/ADD）產生器1420、數據接收器1430及數據發送器1440。時脈產生器1410可產生時脈CK以輸出到記憶體裝置200，並且時脈CK的數量可對應於系統晶片1000與記憶體裝置200之間的通道的數量。
CMD/ADD產生器1420可從命令佇列1310接收命令CMD或者位址ADD，並且可將命令CMD或者位址ADD發送到記憶體裝置200。數據接收器1430可基於來自記憶體裝置200的讀取數據選通訊號（RDQS或DQS）接收數據輸入/輸出訊號DQ的讀取數據。數據接收器1430可將接收到的讀取數據提供給讀取數據佇列1330。數據發送器1440可從寫入數據佇列1340接收寫入數據。數據發送器1440可基於寫入數據選通訊號（WDQS或DQS）將接收到的寫入數據發送到記憶體裝置200。如上所述，數據輸入/輸出訊號DQ可經由數據路徑（例如，圖1中的DP）提供給記憶體裝置200。
圖12是具有3D小晶片結構的系統晶片100B的圖。
參照圖12，系統晶片100B可具有包含基礎晶粒BD及堆疊在基礎晶粒BD上的計算晶粒CD的3D小晶片結構。多個功能塊IP可設置在基礎晶粒BD及計算晶粒CD中的至少一個上。在圖12中，多個功能塊IP被示為設置在計算晶粒CD上，但是示例實施例不限於此，多個功能塊IP也可設置在基礎晶粒BD上。在一些示例實施例中，基礎晶粒BD可對應於圖3A等中的第一晶粒DIE1，及計算晶粒CD可對應於圖3A等中的第二晶粒DIE2。
在這種情況下，多個功能塊IP中的每一個可包含被設計為執行指定的特定功能的晶片。例如，多個功能塊IP中的每一個可包含CPU晶片、輸入/輸出介面晶片、其中實施用於人工智慧（AI）操作的電路的晶片、圖形晶片、媒體晶片等。多個功能塊IP中的一些可包含執行相同功能的晶片。
在根據本發明構思的系統晶片100B中，可根據系統晶片100B的用途對設置在基礎晶粒BD及計算晶粒CD上的多個功能塊IP的類型進行各種修改。因此，與將系統晶片實施為一個功能塊的比較示例的系統晶片相比，系統晶片100B可具有改進的可再用性及可擴展性。
系統晶片100B可包含電壓調節器VR，並且電壓調節器VR可設置在包含在系統晶片100B中的多個晶粒中的至少一個上，即，基礎晶粒BD及計算晶粒CD中的一個上。系統晶片100B的多個功能塊IP可從電壓調節器VR接收輸出電壓。或者，在一些示例實施例中，電壓調節器VR可設置在系統晶片100B的外部，並且系統晶片100B可從外部中的電壓調節器VR接收輸出電壓。
記憶體晶粒MD可設置在系統晶片100B的計算晶粒CD上。記憶體晶粒MD可對應於圖3A等中的記憶體裝置200。記憶體晶粒MD可經由互連通孔電連接到系統晶片100B，並且互連通孔可構成訊號路徑。
電子裝置10（或其他電路系統，例如，系統晶片100、電壓調節器VR、記憶體控制器110、介面電路111、記憶體裝置200、介面電路210、PMIC 300、其變體、系統晶片1000、處理器1100、快取記憶體1200、記憶體控制器1300、其子組件或本文討論的其他電路系統）可包含具有邏輯電路的硬體；硬體/軟體組合，諸如處理器執行軟體；或其組合。例如，處理電路系統更具體地可包含（但不限於）中央處理單元（CPU）、算術邏輯單元（arithmetic logic unit，ALU）、數位訊號處理器、微型計算機、場域可程式閘陣列（field programmable gate array，FPGA）、系統晶片（System-on-Chip，SoC）、可程式邏輯單元、微處理器、應用專用積體電路（application-specific integrated circuit，ASIC）等。
雖然已經參照其示例實施例具體地繪示及描述本發明構思，但是應當理解，在不脫離以下申請專利範圍的精神及範圍的情況下，可在形式及細節上進行各種改變。
101:模製層 10、10A:電子裝置 100、100A、100B、1000:系統晶片 110、1300:記憶體控制器 111、210:介面電路 200:記憶體裝置 210、1400:實體層 220:緩衝晶粒 230_1:第一記憶體晶粒 230_2:第二記憶體晶粒 230_n:第n記憶體晶粒 300:電源管理積體電路/PMIC 1100:處理器 1200:快取記憶體 1310:命令佇列/CMD佇列 1320:命令排程器/CMD排程器 1330:讀取數據佇列 1340:寫入數據佇列 1410:時脈產生器 1420:CMD/ADD產生器 1430:數據接收器 1440:數據發送器 1500:匯流排 A、B:區域 ACL1:第一主動層 ACL2:第二主動層 ADD:位址 BD:基礎晶粒 BP:內部連接端子 BP1:第一凸塊 BP2:第二凸塊 BP3、BP3a:第三凸塊 CD:計算晶粒 Cin:電容器 CK:時脈 CMD:命令 CP:垂直內部佈線 DIE1:第一晶粒 DIE2:第二晶粒 DP、DP':訊號路徑 DQ:數據輸入/輸出訊號 IM:互連端子 IP:功能塊 IS:中介層基板 IV、IV'、IVa、IVb:互連通孔 IW:內部佈線 MBP:微凸塊MBP MD:記憶體晶粒 P1:上部接墊 P2:下部接墊 PSUB:印刷電路板 RDQS:讀取數據選通訊號 SB:外部連接端子 SSUB:系統晶片封裝基板 SUB1:第一基板 SUB2:第二基板 TMV:模穿孔 TSV:矽穿孔 TV:貫通孔 Vin:輸入電壓 VIP:輸入電壓路徑 VOP:輸出電壓路徑 Vout:輸出電壓 VR:電壓調節器 WDQS:寫入數據選通訊號
根據結合附圖進行的以下詳細描述將更清晰地理解本發明概念的實施例，其中：
圖1及圖2是根據示例實施例的電子裝置的方塊圖。
圖3A是根據一些示例實施例的電子裝置的剖視圖。
圖3B是圖3A的區域A的放大剖視圖。
圖4A是根據一些示例實施例的電子裝置的剖視圖。
圖4B是圖4A的區域B的放大剖視圖。
圖5及圖6是根據示例實施例的電子裝置的剖視圖。
圖7至圖9是根據示例實施例的電子裝置的剖視圖。
圖10是根據一些示例實施例的包括在電子裝置中的記憶體裝置的剖視圖。
圖11是根據一些示例實施例的包括在電子裝置中的系統晶片的方塊圖。
圖12是具有三維（3D）小晶片結構的系統晶片的圖。
100:系統晶片
101:模製層
200:記憶體裝置
300:電源管理積體電路/PMIC
A:區域
ACL1:第一主動層
ACL2:第二主動層
BP:內部連接端子
BP1:第一凸塊
BP2:第二凸塊
BP3:第三凸塊
Cin:電容器
DIE1:第一晶粒
DIE2:第二晶粒
DP:訊號路徑
IM:互連端子
IS:中介層基板
IV:互連通孔
PSUB:印刷電路板
SB:外部連接端子
SSUB:系統晶片封裝基板
SUB1:第一基板
SUB2:第二基板
VIP:輸入電壓路徑
VOP:輸出電壓路徑
VR:電壓調節器

Claims (20)

  1. 一種電子裝置，包括： 印刷電路板； 系統晶片（system on chip，SoC），在所述印刷電路板上；以及 記憶體裝置，在所述系統晶片上， 其中所述系統晶片包括 系統晶片封裝基板； 第一晶粒，在所述系統晶片封裝基板上，且其上具有邏輯電路；以及 第二晶粒，在所述第一晶粒上，且其上具有邏輯電路。
  2. 如請求項1所述的電子裝置，其中 所述第一晶粒包括第一基板以及在所述第一基板上且其上具有半導體元件的第一主動層， 所述第二晶粒包括第二基板以及在所述第二基板上且其上具有半導體元件的第二主動層，且 所述第一主動層與所述第二主動層面對面設置。
  3. 如請求項1所述的電子裝置，其中 所述第一晶粒包括第一基板以及在所述第一基板上且其上具有半導體元件的第一主動層， 所述第二晶粒包括第二基板以及在所述第二基板上且其上具有半導體元件的第二主動層， 所述第一主動層面向所述系統晶片封裝基板，且 所述第二主動層面向所述第一晶粒。
  4. 如請求項1所述的電子裝置， 其中所述第一晶粒的尺寸大於所述第二晶粒的尺寸。
  5. 如請求項1所述的電子裝置， 其中所述第二晶粒的尺寸大於所述第一晶粒的尺寸。
  6. 如請求項1所述的電子裝置， 更包括電壓調節器，所述電壓調節器配置成接收輸入電壓及產生輸出電壓以被所述系統晶片使用， 其中所述電壓調節器安裝在所述系統晶片封裝基板上。
  7. 如請求項6所述的電子裝置， 其中所述電壓調節器與所述第一晶粒在相同的平面上平行。
  8. 如請求項1所述的電子裝置， 更包括電壓調節器，所述電壓調節器配置成接收輸入電壓且配置成產生輸出電壓以被所述系統晶片使用， 其中所述電壓調節器在所述第一晶粒上。
  9. 如請求項1所述的電子裝置， 更包括電壓調節器，所述電壓調節器配置成接收輸入電壓及產生輸出電壓以被所述系統晶片使用， 其中所述電壓調節器嵌置在所述第一晶粒及所述第二晶粒中的一者中。
  10. 如請求項1所述的電子裝置，其中 所述系統晶片更包括： 記憶體控制器，所述記憶體控制器配置成 將數據輸入/輸出訊號發送到所述記憶體裝置，以及 從所述記憶體裝置接收所述數據輸入/輸出訊號，以及 訊號路徑，將所述記憶體控制器電連接到所述記憶體裝置並配置成發送所述數據輸入/輸出訊號，所述訊號路徑包括在從所述第一晶粒到所述記憶體裝置的方向上垂直延伸的互連通孔。
  11. 如請求項1所述的電子裝置， 其中所述系統晶片更包括： 記憶體控制器，所述記憶體控制器配置成將數據輸入/輸出訊號發送到所述記憶體裝置，以及從所述記憶體裝置接收所述數據輸入/輸出訊號，以及 訊號路徑，所述訊號路徑將所述記憶體控制器電連接到所述記憶體裝置並配置成發送所述數據輸入/輸出訊號，且包括在從所述第二晶粒到所述記憶體裝置的方向上垂直延伸的互連通孔。
  12. 如請求項1所述的電子裝置， 更包括中介層基板，所述中介層基板在所述系統晶片與所述記憶體裝置之間，並將所述系統晶片電連接到所述記憶體裝置。
  13. 一種電子裝置，包括： 印刷電路板； 系統晶片（system on chip，SoC），在所述印刷電路板上，且包括其上具有邏輯電路的至少一個邏輯晶粒； 記憶體裝置，在所述系統晶片上；以及 互連通孔，在從所述至少一個邏輯晶粒到所述記憶體裝置的方向上垂直延伸以將所述至少一個邏輯晶粒電連接到所述記憶體裝置。
  14. 如請求項13所述的電子裝置， 其中所述至少一個邏輯晶粒包括多個垂直堆疊的邏輯晶粒，且 所述互連通孔在從第一晶粒到所述記憶體裝置的方向上垂直延伸，所述第一晶粒是所述多個垂直堆疊的邏輯晶粒中的最下晶粒。
  15. 如請求項13所述的電子裝置， 其中所述至少一個邏輯晶粒包括多個垂直堆疊的邏輯晶粒，且 所述互連通孔在從第二晶粒到所述記憶體裝置的方向上垂直延伸，所述第二晶粒是所述多個垂直堆疊的邏輯晶粒中的最上晶粒。
  16. 如請求項13所述的電子裝置， 其中所述系統晶片更包括圍繞所述至少一個邏輯晶粒的模製層，且 所述互連通孔包括貫穿所述模製層的模穿孔。
  17. 如請求項13所述的電子裝置， 更包括中介層基板，所述中介層基板在所述系統晶片與所述記憶體裝置之間，並將所述系統晶片電連接到所述記憶體裝置， 其中所述互連通孔包括貫穿所述中介層基板的矽穿孔。
  18. 如請求項13所述的電子裝置， 更包括電壓調節器，所述電壓調節器配置成接收輸入電壓及產生輸出電壓以被所述系統晶片使用， 其中所述電壓調節器安裝在所述系統晶片的系統晶片封裝基板上，且與所述至少一個邏輯晶粒在相同的平面上平行。
  19. 如請求項13所述的電子裝置， 更包括電壓調節器，所述電壓調節器配置成接收輸入電壓及產生輸出電壓以被所述系統晶片使用， 其中所述電壓調節器嵌置在所述至少一個邏輯晶粒中。
  20. 一種具有三維（3D）小晶片結構的系統晶片（SoC），所述系統晶片包括： 系統晶片封裝基板； 第一晶粒，藉由使用第一凸塊在所述系統晶片封裝基板上，且其上具有第一邏輯電路；以及 第二晶粒，在所述第一晶粒上，且其上具有第二邏輯電路， 其中所述第一邏輯電路及所述第二邏輯電路從在所述系統晶片封裝基板上的電壓調節器經由輸出電壓路徑接收輸出電壓，且 多個功能塊在所述第一晶粒及所述第二晶粒中的至少一個上。
TW111136169A 2021-09-24 2022-09-23 具有三維小晶片結構的系統晶片以及包括所述系統晶片的電子裝置 TW202324679A (zh)

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