TW202320308A - Ferroelectric memory structure - Google Patents

Ferroelectric memory structure Download PDF

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TW202320308A
TW202320308A TW110140923A TW110140923A TW202320308A TW 202320308 A TW202320308 A TW 202320308A TW 110140923 A TW110140923 A TW 110140923A TW 110140923 A TW110140923 A TW 110140923A TW 202320308 A TW202320308 A TW 202320308A
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electrode
oxide
ferroelectric memory
memory structure
ferroelectric
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TW110140923A
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TWI792658B (en
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張守仁
廖洺漢
陳旻政
吉田宏
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力晶積成電子製造股份有限公司
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Priority to CN202111359112.2A priority patent/CN116096096A/en
Priority to US17/537,519 priority patent/US20230137738A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/10—Arrangements for interconnecting storage elements electrically, e.g. by wiring for interconnecting capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5657—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using ferroelectric storage elements

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Abstract

A ferroelectric memory structure including a substrate, a ferroelectric capacitor structure and a switch device is provided. The ferroelectric capacitor structure is disposed on the substrate. The ferroelectric capacitor structure includes at least one first electrode, first dielectric layers, a second electrode, and a ferroelectric material layer. The at least one first electrode and the first dielectric layers are alternately stacked. The second electrode penetrates through the first electrode. The ferroelectric material layer is disposed between the first electrode and the second electrode. The switch device is electrically connected to the ferroelectric capacitor structure.

Description

鐵電記憶體結構ferroelectric memory structure

本發明實施例是有關於一種記憶體結構，且特別是有關於一種鐵電記憶體(ferroelectric memory)結構。Embodiments of the present invention relate to a memory structure, and more particularly to a ferroelectric memory structure.

鐵電記憶體為一種非揮發性記憶體，且具有存入的資料在斷電後也不會消失的優點。此外，相較於其他非揮發性記憶體，鐵電記憶體具有可靠度高與操作速度快等特點。然而，如何在不增加鐵電記憶胞(ferroelectric memory cell)的面積的情況下，使得單一個鐵電記憶胞具有多種儲存狀態為目前持續努力的目標。Ferroelectric memory is a kind of non-volatile memory, and has the advantage that the stored data will not disappear after power off. In addition, compared with other non-volatile memories, ferroelectric memories have the characteristics of high reliability and fast operation speed. However, how to make a single ferroelectric memory cell have multiple storage states without increasing the area of the ferroelectric memory cell is an ongoing goal.

本發明提供一種鐵電記憶體結構，其可在不增加鐵電記憶胞的面積的情況下，使得單一個鐵電記憶胞具有多種儲存狀態。The invention provides a ferroelectric memory structure, which can enable a single ferroelectric memory cell to have multiple storage states without increasing the area of the ferroelectric memory cell.

本發明提出一種鐵電記憶體結構，包括基底、鐵電電容器結構與開關元件。鐵電電容器結構設置在基底上。鐵電電容器結構包括至少一個第一電極、多個第一介電層、第二電極與鐵電材料層。至少一個第一電極與多個第一介電層交替堆疊。第二電極穿過第一電極。鐵電材料層設置在第一電極與第二電極之間。開關元件電性連接至鐵電電容器結構。The invention proposes a ferroelectric memory structure, including a substrate, a ferroelectric capacitor structure and a switch element. A ferroelectric capacitor structure is disposed on the substrate. The ferroelectric capacitor structure includes at least one first electrode, a plurality of first dielectric layers, a second electrode and a ferroelectric material layer. At least one first electrode is alternately stacked with a plurality of first dielectric layers. The second electrode passes through the first electrode. A layer of ferroelectric material is disposed between the first electrode and the second electrode. The switching element is electrically connected to the ferroelectric capacitor structure.

依照本發明的一實施例所述，在上述鐵電記憶體結構中，鐵電電容器結構可設置在開關元件與基底之間。According to an embodiment of the present invention, in the above ferroelectric memory structure, the ferroelectric capacitor structure may be disposed between the switch element and the substrate.

依照本發明的一實施例所述，在上述鐵電記憶體結構中，開關元件可為電晶體。開關元件可包括通道層、第三電極、第四電極、第五電極與第二介電層。通道層設置在鐵電電容器結構上。第三電極與第四電極設置在鐵電電容器結構上，且位在通道層的兩側。第五電極設置在通道層上。第二介電層設置在第五電極與通道層之間。According to an embodiment of the present invention, in the above ferroelectric memory structure, the switching element may be a transistor. The switching element may include a channel layer, a third electrode, a fourth electrode, a fifth electrode and a second dielectric layer. A channel layer is disposed on the ferroelectric capacitor structure. The third electrode and the fourth electrode are disposed on the ferroelectric capacitor structure and located on two sides of the channel layer. The fifth electrode is disposed on the channel layer. The second dielectric layer is disposed between the fifth electrode and the channel layer.

依照本發明的一實施例所述，在上述鐵電記憶體結構中，開關元件的通道層可電性連接至鐵電電容器結構的第二電極。According to an embodiment of the present invention, in the above ferroelectric memory structure, the channel layer of the switch element can be electrically connected to the second electrode of the ferroelectric capacitor structure.

依照本發明的一實施例所述，在上述鐵電記憶體結構中，開關元件的第三電極可電性連接至鐵電電容器結構的第二電極。According to an embodiment of the present invention, in the above ferroelectric memory structure, the third electrode of the switch element can be electrically connected to the second electrode of the ferroelectric capacitor structure.

依照本發明的一實施例所述，在上述鐵電記憶體結構中，通道層的材料可為氧化物半導體。According to an embodiment of the present invention, in the above ferroelectric memory structure, the material of the channel layer may be an oxide semiconductor.

依照本發明的一實施例所述，在上述鐵電記憶體結構中，氧化物半導體可包括氧化銦鎵鋅(IGZO)、氧化鋅(ZnO)、銦鋅氧化物(IZO)、氧化鈷(CoO x)、氧化鎳(NiO x)、鍶銅氧化物(SrCu 2O x)、銅鋁氧化物(CuAlO 2)、銅銦氧化物(CuInO 2)或銅鎵氧化物(CuGaO 2)。 According to an embodiment of the present invention, in the above ferroelectric memory structure, the oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), cobalt oxide (CoO x ), nickel oxide (NiO x ), strontium copper oxide (SrCu 2 O x ), copper aluminum oxide (CuAlO 2 ), copper indium oxide (CuInO 2 ), or copper gallium oxide (CuGaO 2 ).

依照本發明的一實施例所述，在上述鐵電記憶體結構中，第三電極的材料與第四電極的材料可為N型氧化物半導體或P型氧化物半導體。According to an embodiment of the present invention, in the above ferroelectric memory structure, the material of the third electrode and the material of the fourth electrode can be N-type oxide semiconductor or P-type oxide semiconductor.

依照本發明的一實施例所述，在上述鐵電記憶體結構中，N型氧化物半導體可包括氧化銦鎵鋅(IGZO)、氧化鋅(ZnO)或銦鋅氧化物(IZO)，且N型氧化物半導體可具有N型摻質。According to an embodiment of the present invention, in the above ferroelectric memory structure, the N-type oxide semiconductor may include Indium Gallium Zinc Oxide (IGZO), Zinc Oxide (ZnO) or Indium Zinc Oxide (IZO), and N The N-type oxide semiconductor may have N-type dopants.

依照本發明的一實施例所述，在上述鐵電記憶體結構中，P型氧化物半導體包括氧化鈷(CoO x)、氧化鎳(NiO x)、鍶銅氧化物(SrCu 2O x)、銅鋁氧化物(CuAlO 2)、銅銦氧化物(CuInO 2)或銅鎵氧化物(CuGaO 2)，且P型氧化物半導體可具有P型摻質。 According to an embodiment of the present invention, in the ferroelectric memory structure, the P-type oxide semiconductor includes cobalt oxide (CoO x ), nickel oxide (NiO x ), strontium copper oxide (SrCu 2 O x ), copper aluminum oxide (CuAlO 2 ), copper indium oxide (CuInO 2 ) or copper gallium oxide (CuGaO 2 ), and the P-type oxide semiconductor may have a P-type dopant.

依照本發明的一實施例所述，在上述鐵電記憶體結構中，開關元件可設置在鐵電電容器結構與基底之間。According to an embodiment of the present invention, in the above ferroelectric memory structure, the switch element can be disposed between the ferroelectric capacitor structure and the substrate.

依照本發明的一實施例所述，在上述鐵電記憶體結構中，開關元件可為電晶體。開關元件可包括第三電極、第二介電層、通道層、第四電極與第五電極。第三電極設置在基底上。第二介電層設置在第三電極與基底上。通道層設置在第二介電層上，且位在第三電極上方。第四電極與第五電極設置在第二介電層上，且位在通道層的兩側。According to an embodiment of the present invention, in the above ferroelectric memory structure, the switching element may be a transistor. The switching element may include a third electrode, a second dielectric layer, a channel layer, a fourth electrode and a fifth electrode. The third electrode is disposed on the substrate. The second dielectric layer is disposed on the third electrode and the substrate. The channel layer is disposed on the second dielectric layer and located above the third electrode. The fourth electrode and the fifth electrode are disposed on the second dielectric layer and located on two sides of the channel layer.

依照本發明的一實施例所述，在上述鐵電記憶體結構中，開關元件的通道層可電性連接至鐵電電容器結構的第二電極。According to an embodiment of the present invention, in the above ferroelectric memory structure, the channel layer of the switch element can be electrically connected to the second electrode of the ferroelectric capacitor structure.

依照本發明的一實施例所述，在上述鐵電記憶體結構中，開關元件的第四電極電性可連接至鐵電電容器結構的第二電極。According to an embodiment of the present invention, in the above ferroelectric memory structure, the fourth electrode of the switch element can be electrically connected to the second electrode of the ferroelectric capacitor structure.

依照本發明的一實施例所述，在上述鐵電記憶體結構中，第四電極與第五電極可部分覆蓋通道層。According to an embodiment of the present invention, in the above ferroelectric memory structure, the fourth electrode and the fifth electrode may partially cover the channel layer.

依照本發明的一實施例所述，在上述鐵電記憶體結構中，通道層的材料可為氧化物半導體。According to an embodiment of the present invention, in the above ferroelectric memory structure, the material of the channel layer may be an oxide semiconductor.

依照本發明的一實施例所述，在上述鐵電記憶體結構中，氧化物半導體可包括氧化銦鎵鋅(IGZO)、氧化鋅(ZnO)、銦鋅氧化物(IZO)、氧化鈷(CoO x)、氧化鎳(NiO x)、鍶銅氧化物(SrCu 2O x)、銅鋁氧化物(CuAlO 2)、銅銦氧化物(CuInO 2)或銅鎵氧化物(CuGaO 2)。 According to an embodiment of the present invention, in the above ferroelectric memory structure, the oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), cobalt oxide (CoO x ), nickel oxide (NiO x ), strontium copper oxide (SrCu 2 O x ), copper aluminum oxide (CuAlO 2 ), copper indium oxide (CuInO 2 ), or copper gallium oxide (CuGaO 2 ).

依照本發明的一實施例所述，在上述鐵電記憶體結構中，第四電極的材料與第五電極的材料可為N型氧化物半導體或P型氧化物半導體。According to an embodiment of the present invention, in the above ferroelectric memory structure, the material of the fourth electrode and the material of the fifth electrode can be N-type oxide semiconductor or P-type oxide semiconductor.

依照本發明的一實施例所述，在上述鐵電記憶體結構中，N型氧化物半導體可包括氧化銦鎵鋅(IGZO)、氧化鋅(ZnO)或銦鋅氧化物(IZO)，且N型氧化物半導體可具有N型摻質。According to an embodiment of the present invention, in the above ferroelectric memory structure, the N-type oxide semiconductor may include Indium Gallium Zinc Oxide (IGZO), Zinc Oxide (ZnO) or Indium Zinc Oxide (IZO), and N The N-type oxide semiconductor may have N-type dopants.

依照本發明的一實施例所述，在上述鐵電記憶體結構中，P型氧化物半導體可包括氧化鈷(CoO x)、氧化鎳(NiO x)、鍶銅氧化物(SrCu 2O x)、銅鋁氧化物(CuAlO 2)、銅銦氧化物(CuInO 2)或銅鎵氧化物(CuGaO 2)，且P型氧化物半導體可具有P型摻質。 According to an embodiment of the present invention, in the above ferroelectric memory structure, the P-type oxide semiconductor may include cobalt oxide (CoO x ), nickel oxide (NiO x ), strontium copper oxide (SrCu 2 O x ) , copper aluminum oxide (CuAlO 2 ), copper indium oxide (CuInO 2 ) or copper gallium oxide (CuGaO 2 ), and the P-type oxide semiconductor may have a P-type dopant.

基於上述，在本發明所提出的鐵電記憶體結構中，鐵電電容器結構包括交替堆疊的至少一個第一電極與多個第一介電層，第二電極穿過第一電極，且鐵電材料層設置在第一電極與第二電極之間。此外，第一電極可用以作為加權狀態電極(weighting state electrode)。因此，在對鐵電記憶體結構進行操作時，可藉由分別對第一電極與第二電極施加電壓來調整鐵電電容器結構的阻抗(如，電容)。如此一來，可在不增加鐵電記憶胞面積的情況下，使得單一個鐵電記憶胞具有多種儲存狀態。Based on the above, in the ferroelectric memory structure proposed by the present invention, the ferroelectric capacitor structure includes at least one first electrode and a plurality of first dielectric layers stacked alternately, the second electrode passes through the first electrode, and the ferroelectric The material layer is disposed between the first electrode and the second electrode. In addition, the first electrode can be used as a weighting state electrode. Therefore, when operating the ferroelectric memory structure, the impedance (eg, capacitance) of the ferroelectric capacitor structure can be adjusted by applying voltages to the first electrode and the second electrode respectively. In this way, a single ferroelectric memory cell can have multiple storage states without increasing the area of the ferroelectric memory cell.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

下文列舉實施例並配合附圖來進行詳細地說明，但所提供的實施例並非用以限制本發明所涵蓋的範圍。為了方便理解，在下述說明中，相同的構件將以相同的符號標示來說明。此外，附圖僅以說明為目的，並未依照原尺寸作圖。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。Embodiments are listed below and described in detail with accompanying drawings, but the provided embodiments are not intended to limit the scope of the present invention. In order to facilitate understanding, in the following description, the same components will be described with the same symbols. In addition, the drawings are for illustration purposes only and are not drawn to original scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

圖1為根據本發明一些實施例的鐵電記憶體結構的剖面圖。圖2為圖1中的鐵電電容器結構的立體示意圖。圖3為根據本發明一些實施例的鐵電記憶體結構的剖面圖。FIG. 1 is a cross-sectional view of a ferroelectric memory structure according to some embodiments of the present invention. FIG. 2 is a schematic perspective view of the structure of the ferroelectric capacitor in FIG. 1 . 3 is a cross-sectional view of a ferroelectric memory structure according to some embodiments of the present invention.

請參照圖1與圖2，鐵電記憶體結構10包括基底100、鐵電電容器結構102與開關元件104。基底100可為半導體基底，如矽基底。在本實施例中，鐵電電容器結構102可設置在開關元件104與基底100之間，但本發明並不以此為限。Referring to FIG. 1 and FIG. 2 , the ferroelectric memory structure 10 includes a substrate 100 , a ferroelectric capacitor structure 102 and a switch element 104 . The substrate 100 can be a semiconductor substrate, such as a silicon substrate. In this embodiment, the ferroelectric capacitor structure 102 can be disposed between the switch element 104 and the substrate 100 , but the invention is not limited thereto.

鐵電電容器結構102設置在基底100上。鐵電電容器結構102包括至少一個電極106、多個介電層108、電極110與鐵電材料層112。至少一個電極106與多個介電層108交替堆疊。電極106可用以作為加權狀態電極。電極106的材料例如是鉬、鈦、鉭、鎢、鋁、銅、鉻或其合金。介電層108的材料例如是氧化矽、氮化矽、氮化鉿等介電材料。在本實施例中，電極106的數量是以多個為例，但電極106的數量並不限於圖中所示的數量。只要電極106的數量為至少一個，即屬於本發明所涵蓋的範圍。The ferroelectric capacitor structure 102 is disposed on the substrate 100 . The ferroelectric capacitor structure 102 includes at least one electrode 106 , a plurality of dielectric layers 108 , an electrode 110 and a layer 112 of ferroelectric material. At least one electrode 106 is alternately stacked with a plurality of dielectric layers 108 . Electrode 106 may be used as a weighted state electrode. The material of the electrode 106 is, for example, molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium or alloys thereof. The material of the dielectric layer 108 is, for example, silicon oxide, silicon nitride, hafnium nitride and other dielectric materials. In this embodiment, the number of electrodes 106 is multiple as an example, but the number of electrodes 106 is not limited to the number shown in the figure. As long as the number of electrodes 106 is at least one, it falls within the scope of the present invention.

電極110穿過電極106。此外，電極110可穿過多個介電層108的至少一部份。電極110可用以作為主體電極(bulk electrode)。電極110的材料例如是鉬、鈦、鉭、鎢、鋁、銅、鉻或其合金。Electrode 110 passes through electrode 106 . Additionally, the electrode 110 may pass through at least a portion of the plurality of dielectric layers 108 . The electrode 110 can be used as a bulk electrode. The material of the electrode 110 is, for example, molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium or alloys thereof.

鐵電材料層112設置在電極106與電極110之間。鐵電材料層112的材料可包括氧化鉿鋯(HfZrO x，HZO)、鋯鈦酸鉛(Pb[Zr xTi 1-x]O 3，PZT)、鈦酸鍶(SrTiO 3，STO)、鈦酸鋇(BaTiO 3，BTO)或鐵酸鉍(BiFeO 3，BFO)。 A layer 112 of ferroelectric material is disposed between the electrode 106 and the electrode 110 . The material of the ferroelectric material layer 112 may include hafnium zirconium oxide (HfZrO x , HZO), lead zirconate titanate (Pb[Zr x Ti 1-x ]O 3 , PZT), strontium titanate (SrTiO 3 , STO), titanium barium oxide (BaTiO 3 , BTO) or bismuth ferrite (BiFeO 3 , BFO).

此外，鐵電電容器結構102可包括至少一個鐵電電容器FC，其中每個鐵電電容器FC可包括一個電極106、電極110與鐵電材料層112。在本實施例中，鐵電電容器結構102是以包括彼此電性連接的多個鐵電電容器FC為例，但本發明並不以此為限。在一些實施例中，多個鐵電電容器FC可共用電極110與鐵電材料層112。此外，鐵電電容器FC的數量不限於圖中所示的數量。只要鐵電電容器FC的數量為至少一個，即屬於本發明所涵蓋的範圍。In addition, the ferroelectric capacitor structure 102 may include at least one ferroelectric capacitor FC, wherein each ferroelectric capacitor FC may include an electrode 106 , an electrode 110 and a ferroelectric material layer 112 . In this embodiment, the ferroelectric capacitor structure 102 is exemplified by including a plurality of ferroelectric capacitors FC electrically connected to each other, but the invention is not limited thereto. In some embodiments, a plurality of ferroelectric capacitors FC may share the electrode 110 and the ferroelectric material layer 112 . In addition, the number of ferroelectric capacitors FC is not limited to the number shown in the figure. As long as there is at least one ferroelectric capacitor FC, it falls within the scope of the present invention.

開關元件104電性連接至鐵電電容器結構102。在本實施例中，開關元件104可設置在鐵電電容器結構102上。在本實施例中，開關元件104可為電晶體，但本發明並不以此為限。開關元件104可包括通道層114、電極116、電極118、電極120與介電層122。通道層114設置在鐵電電容器結構102上。通道層114的材料可為氧化物半導體。在一些實施例中，上述氧化物半導體可包括氧化銦鎵鋅(IGZO)、氧化鋅(ZnO)、銦鋅氧化物(IZO)、氧化鈷(CoO x)、氧化鎳(NiO x)、鍶銅氧化物(SrCu 2O x)、銅鋁氧化物(CuAlO 2)、銅銦氧化物(CuInO 2)或銅鎵氧化物(CuGaO 2)。 The switch element 104 is electrically connected to the ferroelectric capacitor structure 102 . In this embodiment, the switching element 104 may be disposed on the ferroelectric capacitor structure 102 . In this embodiment, the switching element 104 can be a transistor, but the invention is not limited thereto. The switch element 104 may include a channel layer 114 , an electrode 116 , an electrode 118 , an electrode 120 and a dielectric layer 122 . A channel layer 114 is disposed on the ferroelectric capacitor structure 102 . The material of the channel layer 114 may be an oxide semiconductor. In some embodiments, the aforementioned oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), cobalt oxide (CoO x ), nickel oxide (NiO x ), strontium copper oxide (SrCu 2 O x ), copper aluminum oxide (CuAlO 2 ), copper indium oxide (CuInO 2 ), or copper gallium oxide (CuGaO 2 ).

電極116與電極118設置在鐵電電容器結構102上，且位在通道層114的兩側。電極116與電極118分別可用以作為源極與汲極中的一者與另一者。在本實施例中，電極116可用以作為源極，且電極118可用以作為汲極。電極116的材料與電極118的材料可為N型氧化物半導體或P型氧化物半導體。在一些實施例中，上述N型氧化物半導體可包括氧化銦鎵鋅(IGZO)、氧化鋅(ZnO)或銦鋅氧化物(IZO)，且N型氧化物半導體可具有N型摻質。在一些實施例中，上述P型氧化物半導體包括氧化鈷(CoO x)、氧化鎳(NiO x)、鍶銅氧化物(SrCu 2O x)、銅鋁氧化物(CuAlO 2)、銅銦氧化物(CuInO 2)或銅鎵氧化物(CuGaO 2)，且所述P型氧化物半導體可具有P型摻質。 The electrodes 116 and 118 are disposed on the ferroelectric capacitor structure 102 and located on two sides of the channel layer 114 . The electrodes 116 and 118 can be used as one and the other of a source and a drain, respectively. In this embodiment, the electrode 116 can be used as a source, and the electrode 118 can be used as a drain. The material of the electrode 116 and the material of the electrode 118 can be N-type oxide semiconductor or P-type oxide semiconductor. In some embodiments, the N-type oxide semiconductor may include Indium Gallium Zinc Oxide (IGZO), Zinc Oxide (ZnO) or Indium Zinc Oxide (IZO), and the N-type oxide semiconductor may have N-type dopants. In some embodiments, the above-mentioned P-type oxide semiconductor includes cobalt oxide (CoO x ), nickel oxide (NiO x ), strontium copper oxide (SrCu 2 O x ), copper aluminum oxide (CuAlO 2 ), copper indium oxide compound (CuInO 2 ) or copper gallium oxide (CuGaO 2 ), and the P-type oxide semiconductor may have a P-type dopant.

電極120設置在通道層114上。電極120可用以作為閘極。電極120的材料例如是鉬、鈦、鉭、鎢、鋁、銅、鉻或其合金。The electrode 120 is disposed on the channel layer 114 . The electrode 120 can be used as a gate. The material of the electrode 120 is, for example, molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium or alloys thereof.

介電層122設置在電極120與通道層114之間。在一些實施例中，介電層122更可設置在電極120與電極116之間以及電極120與電極118之間。介電層122可用以作為閘介電層。介電層122的材料例如是氧化矽、氮化矽、氮化鉿等介電材料。The dielectric layer 122 is disposed between the electrode 120 and the channel layer 114 . In some embodiments, the dielectric layer 122 can be further disposed between the electrode 120 and the electrode 116 and between the electrode 120 and the electrode 118 . The dielectric layer 122 can be used as a gate dielectric layer. The material of the dielectric layer 122 is, for example, silicon oxide, silicon nitride, hafnium nitride and other dielectric materials.

在本實施例中，如圖1所示，開關元件104的通道層114可電性連接至鐵電電容器結構102的電極110，藉此開關元件104可電性連接至鐵電電容器結構102，但本發明並不以此為限。在另一些實施例中，如圖3所示，開關元件104的電極116可電性連接至鐵電電容器結構102的電極110，藉此開關元件104可電性連接至鐵電電容器結構102。In this embodiment, as shown in FIG. 1 , the channel layer 114 of the switching element 104 can be electrically connected to the electrode 110 of the ferroelectric capacitor structure 102, whereby the switching element 104 can be electrically connected to the ferroelectric capacitor structure 102, but The present invention is not limited thereto. In other embodiments, as shown in FIG. 3 , the electrode 116 of the switch element 104 can be electrically connected to the electrode 110 of the ferroelectric capacitor structure 102 , whereby the switch element 104 can be electrically connected to the ferroelectric capacitor structure 102 .

此外，鐵電記憶體結構10更可包括其他所需的介電層(用以進行隔離)及/或其他所需的內連線結構(用於進行電性連接)，於此省略其說明。In addition, the ferroelectric memory structure 10 may further include other required dielectric layers (for isolation) and/or other required interconnection structures (for electrical connection), the description of which is omitted here.

以下，藉由表1來說明鐵電記憶體結構10的鐵電記憶胞MC的各種儲存狀態。鐵電記憶體結構10的鐵電記憶胞MC可包括彼此電性連接的鐵電電容器結構102與開關元件104。藉由控制施加在電極106與電極110的電壓，可使得鐵電電容器FC具有“正(+)方向”的極化狀態或“負(-)方向”的極化狀態。當鐵電電容器FC具有“正(+)方向”的極化狀態時，鐵電電容器FC可具有低阻抗(如，低電容C L)。當鐵電電容器FC具有“負(-)方向”的極化狀態時，鐵電電容器FC可具有高阻抗(如，高電容C H)。因此，每個鐵電電容器FC的阻抗(如，電容)可藉由施加在電極106與電極110的電壓來進行調整。如此一來，在對鐵電記憶胞MC進行操作時，電極106可用以作為加權狀態電極，且可藉由分別對電極106與電極110施加電壓來調整鐵電電容器結構102的阻抗(如，電容)，藉此單一個鐵電記憶胞MC可具有多種儲存狀態。在本實施例中，阻抗是以電容為例，但本發明並不以此為限。 Hereinafter, various storage states of the ferroelectric memory cells MC of the ferroelectric memory structure 10 will be described with Table 1. The ferroelectric memory cell MC of the ferroelectric memory structure 10 may include a ferroelectric capacitor structure 102 and a switch element 104 electrically connected to each other. By controlling the voltage applied to the electrodes 106 and 110 , the ferroelectric capacitor FC can have a polarization state of “positive (+) direction” or a polarization state of “negative (-) direction”. When the ferroelectric capacitor FC has a "positive (+) direction" polarization state, the ferroelectric capacitor FC may have a low impedance (eg, low capacitance C L ). When the ferroelectric capacitor FC has a polarization state of "negative (-) direction", the ferroelectric capacitor FC may have a high impedance (eg, a high capacitance CH ). Therefore, the impedance (eg, capacitance) of each ferroelectric capacitor FC can be adjusted by the voltage applied to the electrodes 106 and 110 . In this way, when operating the ferroelectric memory cell MC, the electrode 106 can be used as a weighted state electrode, and the impedance (e.g., capacitance) of the ferroelectric capacitor structure 102 can be adjusted by applying voltages to the electrode 106 and the electrode 110, respectively. ), whereby a single ferroelectric memory cell MC can have multiple storage states. In this embodiment, the impedance is a capacitor as an example, but the present invention is not limited thereto.

舉例來說，鐵電電容器結構102可包括n個電極106，且n可為大於或等於1的整數。如表1所示，在鐵電電容器結構102包括n個電極106(如，表1中的加權狀態電極WE1~加權狀態電極WEn)的情況下，鐵電電容器結構102可包括彼此電性連接的n個鐵電電容器FC。藉此，鐵電記憶體結構10的鐵電記憶胞MC可具有“n+1”種儲存狀態(即，表1中的“儲存狀態0”~“儲存狀態n”)。For example, the ferroelectric capacitor structure 102 may include n electrodes 106 , and n may be an integer greater than or equal to one. As shown in Table 1, in the case that the ferroelectric capacitor structure 102 includes n electrodes 106 (such as the weighted state electrodes WE1~weighted state electrodes WEn in Table 1), the ferroelectric capacitor structure 102 may include n electrodes 106 that are electrically connected to each other. n ferroelectric capacitors FC. Thereby, the ferroelectric memory cell MC of the ferroelectric memory structure 10 can have “n+1” storage states (ie, “storage state 0”˜“storage state n” in Table 1).

表1 加權狀態電極 WE1 WE2 WE3 …WEn 儲存狀態0： nC L C L C L C L ...C L 儲存狀態1： 1C H+(n-1)C L C H C L C L ...C L 儲存狀態2： 2C H+(n-2)C L C H C H C L …C L 儲存狀態3： 3C H+(n-3)C L C H C H C H …C L …   …   …   …   …   儲存狀態n： nC H C H C H C H …C H Table 1 weighted state electrodes WE1 WE2 WE3 …WEn Storage state 0: nC L C L C L C L ... C L Storage state 1: 1C H +(n-1)C L CH C L C L ... C L Storage state 2: 2C H +(n-2)C L CH CH C L …C L Storage state 3: 3C H +(n-3)C L CH CH CH …C L … … … … … Storage state n: nCH CH CH CH …C H

基於上述實施例可知，在鐵電記憶體結構10中，鐵電電容器結構102包括交替堆疊的至少一個電極106與多個介電層108，電極110穿過電極106，且鐵電材料層112設置在電極106與電極110之間。此外，電極106可用以作為加權狀態電極。因此，在對鐵電記憶體結構10進行操作時，可藉由分別對電極106與電極110施加電壓來調整鐵電電容器結構102的阻抗(如，電容)。如此一來，可在不增加鐵電記憶胞MC的面積的情況下，使得單一個鐵電記憶胞MC具有多種儲存狀態。Based on the above embodiments, it can be seen that in the ferroelectric memory structure 10, the ferroelectric capacitor structure 102 includes at least one electrode 106 and a plurality of dielectric layers 108 stacked alternately, the electrode 110 passes through the electrode 106, and the ferroelectric material layer 112 is arranged Between the electrode 106 and the electrode 110 . Additionally, the electrodes 106 can be used as weighted state electrodes. Therefore, when operating the ferroelectric memory structure 10 , the impedance (eg, capacitance) of the ferroelectric capacitor structure 102 can be adjusted by applying voltages to the electrodes 106 and 110 respectively. In this way, a single ferroelectric memory cell MC can have multiple storage states without increasing the area of the ferroelectric memory cell MC.

圖4為根據本發明一些實施例的鐵電記憶體結構的剖面圖。圖5為根據本發明一些實施例的鐵電記憶體結構的剖面圖。4 is a cross-sectional view of a ferroelectric memory structure according to some embodiments of the present invention. 5 is a cross-sectional view of a ferroelectric memory structure according to some embodiments of the present invention.

請參照圖1與圖4，圖4的鐵電記憶體結構20與圖1的鐵電記憶體結構10的差異如下。在圖4的鐵電記憶體結構20中，開關元件204可設置在鐵電電容器結構102與基底100之間。在本實施例中，開關元件204可設置在基底100上，且鐵電電容器結構102可設置在開關元件204上。Please refer to FIG. 1 and FIG. 4 , the differences between the ferroelectric memory structure 20 in FIG. 4 and the ferroelectric memory structure 10 in FIG. 1 are as follows. In the ferroelectric memory structure 20 of FIG. 4 , the switch element 204 may be disposed between the ferroelectric capacitor structure 102 and the substrate 100 . In this embodiment, the switch element 204 can be disposed on the substrate 100 , and the ferroelectric capacitor structure 102 can be disposed on the switch element 204 .

開關元件204電性連接至鐵電電容器結構102。在本實施例中，開關元件204可為電晶體。開關元件204可包括電極220、介電層222、通道層214、電極216與電極218。電極220設置在基底100上。電極220可用以作為閘極。電極220的材料例如是鉬、鈦、鉭、鎢、鋁、銅、鉻或其合金。The switch element 204 is electrically connected to the ferroelectric capacitor structure 102 . In this embodiment, the switching element 204 can be a transistor. The switch element 204 may include an electrode 220 , a dielectric layer 222 , a channel layer 214 , an electrode 216 and an electrode 218 . The electrode 220 is disposed on the substrate 100 . The electrode 220 can be used as a gate. The material of the electrode 220 is, for example, molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium or alloys thereof.

介電層222設置在電極220與基底100上。介電層222可用以作為閘介電層。介電層222的材料例如是氧化矽、氮化矽、氮化鉿等介電材料。The dielectric layer 222 is disposed on the electrode 220 and the substrate 100 . The dielectric layer 222 can be used as a gate dielectric layer. The material of the dielectric layer 222 is, for example, silicon oxide, silicon nitride, hafnium nitride and other dielectric materials.

通道層214設置在介電層222上，且位在電極220上方。通道層214的材料可為氧化物半導體。在一些實施例中，上述氧化物半導體可包括氧化銦鎵鋅(IGZO)、氧化鋅(ZnO)、銦鋅氧化物(IZO)、氧化鈷(CoO x)、氧化鎳(NiO x)、鍶銅氧化物(SrCu 2O x)、銅鋁氧化物(CuAlO 2)、銅銦氧化物(CuInO 2)或銅鎵氧化物(CuGaO 2)。 The channel layer 214 is disposed on the dielectric layer 222 and above the electrode 220 . The material of the channel layer 214 may be an oxide semiconductor. In some embodiments, the aforementioned oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), cobalt oxide (CoO x ), nickel oxide (NiO x ), strontium copper oxide (SrCu 2 O x ), copper aluminum oxide (CuAlO 2 ), copper indium oxide (CuInO 2 ), or copper gallium oxide (CuGaO 2 ).

電極216與電極218設置在介電層222上，且位在通道層214的兩側。在一些實施例中，電極216與電極218可部分覆蓋通道層214。電極216與電極218分別可用以作為源極與汲極中的一者與另一者。在本實施例中，電極216可用以作為源極，且電極218可用以作為汲極。電極216的材料與電極218的材料可為N型氧化物半導體或P型氧化物半導體。在一些實施例中，上述N型氧化物半導體可包括氧化銦鎵鋅(IGZO)、氧化鋅(ZnO)或銦鋅氧化物(IZO)，且N型氧化物半導體可具有N型摻質。在一些實施例中，上述P型氧化物半導體包括氧化鈷(CoO x)、氧化鎳(NiO x)、鍶銅氧化物(SrCu 2O x)、銅鋁氧化物(CuAlO 2)、銅銦氧化物(CuInO 2)或銅鎵氧化物(CuGaO 2)，且所述P型氧化物半導體可具有P型摻質。 The electrodes 216 and 218 are disposed on the dielectric layer 222 and located on two sides of the channel layer 214 . In some embodiments, the electrodes 216 and 218 may partially cover the channel layer 214 . The electrode 216 and the electrode 218 can be used as one and the other of the source and the drain, respectively. In this embodiment, the electrode 216 can be used as a source, and the electrode 218 can be used as a drain. The material of the electrode 216 and the material of the electrode 218 can be N-type oxide semiconductor or P-type oxide semiconductor. In some embodiments, the N-type oxide semiconductor may include Indium Gallium Zinc Oxide (IGZO), Zinc Oxide (ZnO) or Indium Zinc Oxide (IZO), and the N-type oxide semiconductor may have N-type dopants. In some embodiments, the above-mentioned P-type oxide semiconductor includes cobalt oxide (CoO x ), nickel oxide (NiO x ), strontium copper oxide (SrCu 2 O x ), copper aluminum oxide (CuAlO 2 ), copper indium oxide (CuInO 2 ) or copper gallium oxide (CuGaO 2 ), and the P-type oxide semiconductor may have a P-type dopant.

在本實施例中，如圖4所示，開關元件204的通道層214可電性連接至鐵電電容器結構102的電極110，藉此開關元件204可電性連接至鐵電電容器結構102，但本發明並不以此為限。舉例來說，如圖4所示，電極110可穿過電極106與介電層108而電性連接至通道層214。在另一些實施例中，如圖5所示，開關元件204的電極216可電性連接至鐵電電容器結構102的電極110，藉此開關元件204可電性連接至鐵電電容器結構102。舉例來說，如圖5所示，電極110可穿過電極106與介電層108而電性連接至電極216。In this embodiment, as shown in FIG. 4 , the channel layer 214 of the switching element 204 can be electrically connected to the electrode 110 of the ferroelectric capacitor structure 102, whereby the switching element 204 can be electrically connected to the ferroelectric capacitor structure 102, but The present invention is not limited thereto. For example, as shown in FIG. 4 , the electrode 110 can be electrically connected to the channel layer 214 through the electrode 106 and the dielectric layer 108 . In other embodiments, as shown in FIG. 5 , the electrode 216 of the switch element 204 can be electrically connected to the electrode 110 of the ferroelectric capacitor structure 102 , whereby the switch element 204 can be electrically connected to the ferroelectric capacitor structure 102 . For example, as shown in FIG. 5 , the electrode 110 can be electrically connected to the electrode 216 through the electrode 106 and the dielectric layer 108 .

此外，鐵電記憶體結構20與鐵電記憶體結構10中的相同或相似的構件使用相同或相似的符號表示，且鐵電記憶體結構20與鐵電記憶體結構10中相同或相似的內容(如，操作方法)，可參考上述實施例對鐵電記憶體結構10的說明，於此不再說明。另外，鐵電記憶體結構20更可包括其他所需的介電層(用以進行隔離)及/或其他所需的內連線結構(用於進行電性連接)，於此省略其說明。In addition, the same or similar components in the ferroelectric memory structure 20 and the ferroelectric memory structure 10 are represented by the same or similar symbols, and the same or similar contents in the ferroelectric memory structure 20 and the ferroelectric memory structure 10 (For example, the operation method), reference can be made to the description of the ferroelectric memory structure 10 in the above-mentioned embodiments, and no further description is given here. In addition, the ferroelectric memory structure 20 may further include other required dielectric layers (for isolation) and/or other required interconnection structures (for electrical connection), and the description thereof is omitted here.

基於上述實施例可知，在鐵電記憶體結構20中，鐵電電容器結構102包括交替堆疊的至少一個電極106與多個介電層108，電極110穿過電極106，且鐵電材料層112設置在電極106與電極110之間。此外，電極106可用以作為加權狀態電極。因此，在對鐵電記憶體結構20進行操作時，可藉由分別對電極106與電極110施加電壓來調整鐵電電容器結構102的阻抗(如，電容)。如此一來，可在不增加鐵電記憶胞MC的面積的情況下，使得單一個鐵電記憶胞MC具有多種儲存狀態。Based on the above embodiments, it can be seen that in the ferroelectric memory structure 20, the ferroelectric capacitor structure 102 includes at least one electrode 106 and a plurality of dielectric layers 108 stacked alternately, the electrode 110 passes through the electrode 106, and the ferroelectric material layer 112 is arranged Between the electrode 106 and the electrode 110 . Additionally, the electrodes 106 can be used as weighted state electrodes. Therefore, when operating the ferroelectric memory structure 20 , the impedance (eg, capacitance) of the ferroelectric capacitor structure 102 can be adjusted by applying voltages to the electrodes 106 and 110 respectively. In this way, a single ferroelectric memory cell MC can have multiple storage states without increasing the area of the ferroelectric memory cell MC.

綜上所述，在上述實施例的鐵電記憶體結構中，鐵電電容器結構包括交替堆疊的至少一個加權狀態電極與多個介電層，且加權狀態電極可用以調整鐵電電容器結構的阻抗(如，電容)。因此，可在不增加鐵電記憶胞面積的情況下，使得單一個鐵電記憶胞具有多種儲存狀態。In summary, in the ferroelectric memory structure of the above embodiment, the ferroelectric capacitor structure includes at least one weighted state electrode and a plurality of dielectric layers stacked alternately, and the weighted state electrode can be used to adjust the impedance of the ferroelectric capacitor structure (eg, capacitance). Therefore, a single ferroelectric memory cell can have multiple storage states without increasing the area of the ferroelectric memory cell.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10,20:鐵電記憶體結構 100:基底 102:鐵電電容器結構 104,204:開關元件 106,110,116,118,120,216,218,220:電極 108,122,222:介電層 112:鐵電材料層 114,214:通道層 FC:鐵電電容器 MC:鐵電記憶胞 10,20: Ferroelectric memory structure 100: base 102: Ferroelectric capacitor structure 104, 204: switching elements 106,110,116,118,120,216,218,220: electrodes 108,122,222: dielectric layer 112: ferroelectric material layer 114,214: channel layer FC: ferroelectric capacitor MC: ferroelectric memory cell

圖1為根據本發明一些實施例的鐵電記憶體結構的剖面圖。 圖2為圖1中的鐵電電容器結構的立體示意圖。 圖3為根據本發明一些實施例的鐵電記憶體結構的剖面圖。 圖4為根據本發明一些實施例的鐵電記憶體結構的剖面圖。 圖5為根據本發明一些實施例的鐵電記憶體結構的剖面圖。 FIG. 1 is a cross-sectional view of a ferroelectric memory structure according to some embodiments of the present invention. FIG. 2 is a schematic perspective view of the structure of the ferroelectric capacitor in FIG. 1 . 3 is a cross-sectional view of a ferroelectric memory structure according to some embodiments of the present invention. 4 is a cross-sectional view of a ferroelectric memory structure according to some embodiments of the present invention. 5 is a cross-sectional view of a ferroelectric memory structure according to some embodiments of the present invention.

10:鐵電記憶體結構 10: Ferroelectric memory structure

100:基底 100: base

102:鐵電電容器結構 102: Ferroelectric capacitor structure

104:開關元件 104: switch element

106,110,116,118,120,122:電極 106,110,116,118,120,122: electrodes

108:介電層 108: Dielectric layer

112:鐵電材料層 112: ferroelectric material layer

114:通道層 114: Channel layer

FC:鐵電電容器 FC: ferroelectric capacitor

MC:鐵電記憶胞 MC: ferroelectric memory cell

Claims (20)

一種鐵電記憶體結構，包括： 基底； 鐵電電容器結構，設置在所述基底上，且包括： 交替堆疊的至少一個第一電極與多個第一介電層； 第二電極，穿過所述第一電極；以及 鐵電材料層，設置在所述第一電極與所述第二電極之間；以及 開關元件，電性連接至所述鐵電電容器結構。 A ferroelectric memory structure comprising: base; A ferroelectric capacitor structure disposed on the substrate and comprising: alternately stacking at least one first electrode and a plurality of first dielectric layers; a second electrode passing through the first electrode; and a layer of ferroelectric material disposed between the first electrode and the second electrode; and The switching element is electrically connected to the ferroelectric capacitor structure. 如請求項1所述的鐵電記憶體結構，其中所述鐵電電容器結構設置在所述開關元件與所述基底之間。The ferroelectric memory structure as claimed in claim 1, wherein the ferroelectric capacitor structure is disposed between the switching element and the substrate. 如請求項2所述的鐵電記憶體結構，其中所述開關元件為電晶體，且包括： 通道層，設置在所述鐵電電容器結構上； 第三電極與第四電極，設置在所述鐵電電容器結構上，且位在所述通道層的兩側； 第五電極，設置在所述通道層上；以及 第二介電層，設置在所述第五電極與所述通道層之間。 The ferroelectric memory structure according to claim 2, wherein the switching element is a transistor, and includes: a channel layer disposed on the ferroelectric capacitor structure; The third electrode and the fourth electrode are arranged on the ferroelectric capacitor structure and located on both sides of the channel layer; a fifth electrode disposed on the channel layer; and The second dielectric layer is arranged between the fifth electrode and the channel layer. 如請求項3所述的鐵電記憶體結構，其中所述開關元件的所述通道層電性連接至所述鐵電電容器結構的所述第二電極。The ferroelectric memory structure as claimed in claim 3, wherein the channel layer of the switch element is electrically connected to the second electrode of the ferroelectric capacitor structure. 如請求項3所述的鐵電記憶體結構，其中所述開關元件的所述第三電極電性連接至所述鐵電電容器結構的所述第二電極。The ferroelectric memory structure of claim 3, wherein the third electrode of the switching element is electrically connected to the second electrode of the ferroelectric capacitor structure. 如請求項3所述的鐵電記憶體結構，其中所述通道層的材料包括氧化物半導體。The ferroelectric memory structure as claimed in claim 3, wherein the material of the channel layer includes oxide semiconductor. 如請求項6所述的鐵電記憶體結構，其中所述氧化物半導體包括氧化銦鎵鋅、氧化鋅、銦鋅氧化物、氧化鈷、氧化鎳、鍶銅氧化物、銅鋁氧化物、銅銦氧化物或銅鎵氧化物。The ferroelectric memory structure according to claim 6, wherein the oxide semiconductor includes indium gallium zinc oxide, zinc oxide, indium zinc oxide, cobalt oxide, nickel oxide, strontium copper oxide, copper aluminum oxide, copper indium oxide or copper gallium oxide. 如請求項3所述的鐵電記憶體結構，其中所述第三電極的材料與所述第四電極的材料包括N型氧化物半導體或P型氧化物半導體。The ferroelectric memory structure according to claim 3, wherein the material of the third electrode and the material of the fourth electrode include N-type oxide semiconductor or P-type oxide semiconductor. 如請求項8所述的鐵電記憶體結構，其中所述N型氧化物半導體包括氧化銦鎵鋅、氧化鋅或銦鋅氧化物，且所述N型氧化物半導體具有N型摻質。The ferroelectric memory structure according to claim 8, wherein the N-type oxide semiconductor includes InGaZnO, ZnO or IZnO, and the N-type oxide semiconductor has N-type dopant. 如請求項8所述的鐵電記憶體結構，其中所述P型氧化物半導體包括氧化鈷、氧化鎳、鍶銅氧化物、銅鋁氧化物、銅銦氧化物或銅鎵氧化物，且所述P型氧化物半導體具有P型摻質。The ferroelectric memory structure according to claim 8, wherein the P-type oxide semiconductor includes cobalt oxide, nickel oxide, strontium copper oxide, copper aluminum oxide, copper indium oxide or copper gallium oxide, and the The P-type oxide semiconductor has P-type dopants. 如請求項1所述的鐵電記憶體結構，其中所述開關元件設置在所述鐵電電容器結構與所述基底之間。The ferroelectric memory structure of claim 1, wherein the switching element is disposed between the ferroelectric capacitor structure and the substrate. 如請求項11所述的鐵電記憶體結構，其中所述開關元件為電晶體，且包括： 第三電極，設置在所述基底上； 第二介電層，設置在所述第三電極與所述基底上； 通道層，設置在所述第二介電層上，且位在所述第三電極上方；以及 第四電極與第五電極，設置在所述第二介電層上，且位在所述通道層的兩側。 The ferroelectric memory structure according to claim 11, wherein the switching element is a transistor, and includes: a third electrode disposed on the substrate; a second dielectric layer disposed on the third electrode and the substrate; a channel layer disposed on the second dielectric layer and above the third electrode; and The fourth electrode and the fifth electrode are disposed on the second dielectric layer and located on two sides of the channel layer. 如請求項12所述的鐵電記憶體結構，其中所述開關元件的所述通道層電性連接至所述鐵電電容器結構的所述第二電極。The ferroelectric memory structure of claim 12, wherein the channel layer of the switching element is electrically connected to the second electrode of the ferroelectric capacitor structure. 如請求項12所述的鐵電記憶體結構，其中所述開關元件的所述第四電極電性連接至所述鐵電電容器結構的所述第二電極。The ferroelectric memory structure of claim 12, wherein the fourth electrode of the switching element is electrically connected to the second electrode of the ferroelectric capacitor structure. 如請求項12所述的鐵電記憶體結構，其中所述第四電極與所述第五電極部分覆蓋所述通道層。The ferroelectric memory structure according to claim 12, wherein the fourth electrode and the fifth electrode partially cover the channel layer. 如請求項12所述的鐵電記憶體結構，其中所述通道層的材料包括氧化物半導體。The ferroelectric memory structure as claimed in claim 12, wherein the material of the channel layer includes oxide semiconductor. 如請求項16所述的鐵電記憶體結構，其中所述氧化物半導體包括氧化銦鎵鋅、氧化鋅、銦鋅氧化物、氧化鈷、氧化鎳、鍶銅氧化物、銅鋁氧化物、銅銦氧化物或銅鎵氧化物。The ferroelectric memory structure according to claim 16, wherein the oxide semiconductor includes indium gallium zinc oxide, zinc oxide, indium zinc oxide, cobalt oxide, nickel oxide, strontium copper oxide, copper aluminum oxide, copper indium oxide or copper gallium oxide. 如請求項12所述的鐵電記憶體結構，其中所述第四電極的材料與所述第五電極的材料包括N型氧化物半導體或P型氧化物半導體。The ferroelectric memory structure according to claim 12, wherein the material of the fourth electrode and the material of the fifth electrode include N-type oxide semiconductor or P-type oxide semiconductor. 如請求項18所述的鐵電記憶體結構，其中所述N型氧化物半導體包括氧化銦鎵鋅、氧化鋅或銦鋅氧化物，且所述N型氧化物半導體具有N型摻質。The ferroelectric memory structure according to claim 18, wherein the N-type oxide semiconductor includes InGaZnO, ZnO or IZnO, and the N-type oxide semiconductor has N-type dopant. 如請求項18所述的鐵電記憶體結構，其中所述P型氧化物半導體包括氧化鈷、氧化鎳、鍶銅氧化物、銅鋁氧化物、銅銦氧化物或銅鎵氧化物，且所述P型氧化物半導體具有P型摻質。The ferroelectric memory structure according to claim 18, wherein the P-type oxide semiconductor includes cobalt oxide, nickel oxide, strontium copper oxide, copper aluminum oxide, copper indium oxide or copper gallium oxide, and the The P-type oxide semiconductor has P-type dopants.
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