TW202318480A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H—ELECTRICITY
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
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Abstract
Description
本揭露是有關於一種半導體裝置及其製造方法。The present disclosure relates to a semiconductor device and a manufacturing method thereof.
縮小半導體元件的尺寸和提高半導體元件的整合度是目前半導體元件製造中的其中兩個主要趨勢。由於這些趨勢的結果,形成半導體元件的單元之密度不斷增加。半導體元件縮小到次微米的尺寸需要的是半導體元件單元的例行製造也在次微米等級上進行。Reducing the size of semiconductor devices and improving the integration of semiconductor devices are two major trends in semiconductor device manufacturing. As a result of these trends, the density of cells forming semiconductor devices is increasing. The shrinking of semiconductor components to sub-micron dimensions requires that routine fabrication of semiconductor component units also take place on the sub-micron scale.
通常情況下,晶片是使用許多的薄膜層製成。這些層中的每一層都可以使用決定該層圖案的遮罩(例如光阻)來形成。這個圖案的精確度在製造晶片中十分關鍵。隨著晶片的導電凸塊之間的間距需求越來越小,用以形成此小間距的導電凸塊的光阻之深寬比也會越來越大,意即,用以定義導電凸塊的光阻牆的厚度會越來越薄也因而越來越脆弱,因而在後續的電鍍製程中,容易因熱應力而產生光阻剝離的現象。如此,由於在後續製程(例如電鍍製程)期間無法保持光阻的完整性,從而對半導體裝置製造中關鍵圖案的精確度產生不利的影響,進而影響製程良率。Typically, wafers are made using many thin film layers. Each of these layers can be formed using a mask (such as a photoresist) that determines the pattern of that layer. The accuracy of this pattern is critical in fabricating the wafer. As the spacing between the conductive bumps of the chip becomes smaller and smaller, the aspect ratio of the photoresist used to form the small-pitch conductive bumps will also become larger, that is, to define the conductive bumps The thickness of the photoresist wall will become thinner and more fragile, so in the subsequent electroplating process, it is easy to cause photoresist peeling due to thermal stress. In this way, since the integrity of the photoresist cannot be maintained during the subsequent process (such as the electroplating process), the accuracy of key patterns in semiconductor device manufacturing is adversely affected, thereby affecting the process yield.
本發明提供一種半導體裝置及其製造方法,其能減少光阻剝離的問題,並提升製程良率。The invention provides a semiconductor device and a manufacturing method thereof, which can reduce the problem of photoresist stripping and improve the process yield.
本發明的一實施例提供一種半導體裝置,其包括基板、多個接墊、鈍化層、介電層以及多個導電凸塊。接墊設置於基板上。鈍化層設置於基板上,且鈍化層暴露接墊。介電層覆蓋部分鈍化層並包括多個介電層開口以暴露接墊,其中介電層的材料包括有機材料。導電凸塊設置於介電層開口內並連接接墊,其中導電凸塊之間的間距實質上等於或小於20微米。An embodiment of the present invention provides a semiconductor device, which includes a substrate, a plurality of pads, a passivation layer, a dielectric layer, and a plurality of conductive bumps. The pads are disposed on the substrate. The passivation layer is disposed on the substrate, and the passivation layer exposes the pads. The dielectric layer covers part of the passivation layer and includes a plurality of openings in the dielectric layer to expose the pads, wherein the material of the dielectric layer includes organic materials. The conductive bumps are disposed in the opening of the dielectric layer and connected to the pads, wherein the distance between the conductive bumps is substantially equal to or less than 20 microns.
本發明的另一實施例提供一種半導體裝置的製造方法,其包括下列步驟。形成多個第一接墊於一基板上;形成鈍化層於基板上,其中鈍化層暴露多個接墊;形成介電層於鈍化層上,其中介電層包括多個介電層開口以暴露多個接墊;設置一光阻層於介電層上,其中光阻層包括對應多個介電層開口的多個光阻開口;進行電鍍製程以形成多個導電凸塊於多個光阻開口以及對應的多個介電層開口內;以及移除光阻層。Another embodiment of the present invention provides a method of manufacturing a semiconductor device, which includes the following steps. Forming a plurality of first contact pads on a substrate; forming a passivation layer on the substrate, wherein the passivation layer exposes the plurality of contact pads; forming a dielectric layer on the passivation layer, wherein the dielectric layer includes a plurality of dielectric layer openings to expose A plurality of contact pads; a photoresist layer is arranged on the dielectric layer, wherein the photoresist layer includes a plurality of photoresist openings corresponding to the plurality of dielectric layer openings; an electroplating process is performed to form a plurality of conductive bumps on the plurality of photoresist openings and the corresponding plurality of dielectric layer openings; and removing the photoresist layer.
基於上述,本揭露的半導體裝置及其製造方法透過增設介電層於鈍化層與光阻層之間,可大幅降低用以形成導電凸塊的光阻層的厚度,因而可降低光阻層的深寬比,減少因光阻層的深寬比過大而導致結構強度不足的問題,因此,本揭露的半導體裝置可有效減少光阻層容易在後續的熱製程(例如電鍍製程)中因熱應力而產生光阻剝離的現象,因而能提升製程良率。Based on the above, by adding a dielectric layer between the passivation layer and the photoresist layer, the semiconductor device and its manufacturing method of the present disclosure can greatly reduce the thickness of the photoresist layer used to form the conductive bumps, thereby reducing the thickness of the photoresist layer. The aspect ratio can reduce the problem of insufficient structural strength caused by the excessive aspect ratio of the photoresist layer. Therefore, the semiconductor device disclosed in the present disclosure can effectively reduce the thermal stress of the photoresist layer in subsequent thermal processes (such as electroplating processes). The phenomenon of photoresist stripping occurs, thereby improving the process yield.
有關本發明之前述及其他技術內容、特點與功效,在以下配合參考圖式之各實施例的詳細說明中,將可清楚的呈現。以下實施例中所提到的方向用語,例如:「上」、「下」、「前」、「後」、「左」、「右」等,僅是參考附加圖式的方向。因此,使用的方向用語是用來說明,而並非用來限制本發明。並且,在下列各實施例中,相同或相似的元件將採用相同或相似的標號。The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed descriptions of the embodiments with reference to the drawings. The directional terms mentioned in the following embodiments, such as "upper", "lower", "front", "rear", "left", "right", etc., are only referring to the directions of the attached drawings. Accordingly, the directional terms used are illustrative, not limiting, of the invention. Also, in the following embodiments, the same or similar components will be given the same or similar symbols.
圖1至圖6是依照本發明的一實施例的一種半導體裝置的製造流程的剖面示意圖。在本實施例中,半導體裝置100(如圖6所示)的製造方法可包括下列步驟。請先參照圖1,可形成多個接墊120於基板110上。為了圖面簡潔,圖1至圖6省略繪示了基板110上的元件,惟本領域具有通常知識者應了解,基板110更可包括例如一或多個主動裝置及重配置線路層等元件。在一實施例中,接墊120可包括多個第一接墊120a以及多個第二接墊120b,其中,第一接墊120a之間的間距P1小於第二接墊120b之間的間距(可參照圖7的間距P2)。換句話說,基板110可包括形成有第一接墊120a的第一區R1以及形成有第二接墊120b的第二區R2,其中,位在第一區R1的第一接墊120a的間距P1較小,而位在第二區R2的第二接墊120b的間距P2較大。在本實施例中,相鄰兩個第一接墊120a之間的間距P1可實質上等於或小於20微米。1 to 6 are schematic cross-sectional views of a manufacturing process of a semiconductor device according to an embodiment of the present invention. In this embodiment, the manufacturing method of the semiconductor device 100 (as shown in FIG. 6 ) may include the following steps. Referring to FIG. 1 first, a plurality of
接著,形成鈍化層130於基板110上,其中,鈍化層130可包括多個鈍化層開口132,分別用以暴露接墊120。在本實施例中,鈍化層130覆蓋第一區R1及第二區R2並透過鈍化層開口132暴露第一接墊120a以及第二接墊120b。詳細而言,鈍化層130可環繞並覆蓋第一接墊120a以及第二接墊120b的周緣部份,並包括分別暴露第一接墊120a以及第二接墊120b的鈍化層開口132。鈍化層130的材料可包括氮化矽、氧氮化矽、二氧化矽、二氧化鈦或其他適合的(無機)介電材料。在本實施例中,鈍化層130可例如使用化學氣相沉積(Chemical Vapor Deposition, CVD)、物理氣相沉積(Physical Vapor Deposition, PVD)、原子層沉積(Atomic layer deposition, ALD)或其他適合的製程而形成。在本實施例中,鈍化層130的厚度約小於1微米(µm)。舉例而言,鈍化層130可具有介於約0.4µm至約0.8µm之間的厚度,但不以此為限。Next, a
圖7是依照本發明的一實施例的一種半導體裝置的俯視示意圖。請接續參照圖2及圖7,形成介電層140於鈍化層130上,其中,介電層140包括多個介電層開口142以暴露第一接墊120a。在某些實施例中,介電層140可覆蓋形成有第一接墊120a的第一區R1上,並透過介電層開口142分別暴露第一接墊120a。因此,介電層140至少覆蓋位於第一接墊120a之間的部分鈍化層130,並且,介電層開口142可分別對應暴露第一接墊120a的鈍化層開口132。在本實施例中,如圖2所示,介電層140並未覆蓋(即,暴露)形成有第二接墊120b的第二區R2,也就是說,介電層140會暴露位於第二接墊120b之間的部分鈍化層130。在一替代性的實施例中,介電層140也可同時覆蓋第一區R1以及第二區R2,並包括分別暴露第一接墊120a以及第二接墊120b的多個介電層開口142。在一實施例中,介電層140的材料包括可通過合適的製作技術(例如旋轉塗布等)形成的有機材料,例如聚醯亞胺(Polyimide,PI)、苯並環丁烯(Benzocyclobutene,BCB)、聚苯噁唑(Polybenzoxazole,PBO)或其他適合的有機介電材料。由於介電層140包括分子較大的有機材料,介電層140的厚度T2可實質上大於鈍化層130的厚度T1。舉例而言,介電層140可具有介於約3µm至約15µm之間的厚度。因此,在接墊120a的間距P1較小的第一區R1設置介電層140,可減少後續形成的光阻層160的厚度,因而可降低光阻層160的深寬比(aspect ratio),進而增強光阻層160的結構強度。FIG. 7 is a schematic top view of a semiconductor device according to an embodiment of the present invention. Referring to FIG. 2 and FIG. 7 , a
之後,請參照圖3,形成凸塊底金屬層(Under Bump Metallization)150於介電層140以及被介電層140所暴露的接墊120上。在本實施例中,凸塊底金屬層150先是毯覆式地全面覆蓋如圖2所示的結構的上表面,例如共形地覆蓋介電層140、被介電層140暴露的部分鈍化層130以及被介電層140與鈍化層130所暴露的接墊120a、120b,並且,凸塊底金屬層150可覆蓋介電層開口以及鈍化層開口的側壁。凸塊底金屬層150可例如以濺鍍或電鍍的方式而形成。在本實施例中,凸塊底金屬層150可為單一金屬層也可為複合金屬層,也就是由多層金屬層所組成,本揭露並不以此為限。After that, referring to FIG. 3 , an under bump metallization layer (Under Bump Metallization) 150 is formed on the
請接續參照圖4,形成光阻層160於介電層140上,其中,光阻層160可包括對應介電層開口的多個光阻開口162。詳細而言,光阻層160可先毯覆式地全面覆蓋如圖3所示的結構的上表面,之後再透過曝光、顯影等步驟,將圖案轉移至光阻層160,使得光阻層160形成多個光阻開口162,而光阻開口162可以暴露出位在接墊120a、120b上的凸塊底金屬層150。在本實施例中,光阻開口162的側壁可與介電層開口142的側壁對齊。也就是說,至少在第一區R1中,用以形成導電凸塊(如圖5所示的導電凸塊170)的開口是由光阻開口162與介電層開口142所共同定義出來的。如此,由於增設了介電層140於鈍化層130與光阻層160之間,光阻層160的厚度D1可因此減少,進而可降低光阻層160的深寬比,提升光阻層160的結構強度。舉例來說,位於第一區R1的相鄰兩光阻開口162之間的間距W1可介於約6微米至約20微米之間,並且,至少在第一區R1中,光阻層160的厚度與相鄰兩光阻開口162之間的間距W1的比值實質上等於或小於1。Referring to FIG. 4 , a
請參照圖5,接著進行塡入金屬製程,其例如以電鍍的方式形成多個導電凸塊170於光阻層160之光阻開口162及對應的介電層開口142內,且導電凸塊170覆蓋凸塊底金屬層150。也就是說,凸塊底金屬層150位於接墊120a、120b以及導電凸塊170之間,且導電凸塊170經由凸塊底金屬層150與接墊120a、120b連接。在本實施例中,導電凸塊170包括位於第一區R1中與第一接墊120a連接的第一導電凸塊170a以及位於第二區R2中與第二接墊120b連接的第二導電凸塊170b,並且,第二導電凸塊170b之間的間距大於第一導電凸塊170a之間的間距。在本實施例中,位在第一區R1的第一導電凸塊170a受介電層140所圍繞,而位於第二區R2的第二導電凸塊170b設置於鈍化層130上,且未被介電層140所圍繞。當然,在介電層140同時設置於第一區R1及第二區R2的實施例中,第二導電凸塊170b也可受介電層140所圍繞。特別一提的是,導電凸塊170之材料可選用下列材質,例如金、銀、銅、銅/鎳/金或其它適合之導電材質等均可適用。Please refer to FIG. 5 , and then perform an implantation metal process, which for example forms a plurality of
接著,請參照圖6及圖7,進行移除光阻製程,以將光阻層160移除。之後,進行移除凸塊底金屬層150製程,例如以蝕刻的方式移除被導電凸塊170a、170b所暴露的部分凸塊底金屬層150。如此,殘留的凸塊底金屬層150位在導電凸塊170a、170b的下方,並可暴露出下方的鈍化層130及介電層140。至此,本實施例的半導體裝置100可大致形成。就結構而言,第一導電凸塊170a之間的最短距離W2實質上等於或小於20微米。進一步來說,第一導電凸塊170a之間的最短距離W2實質上介於約6微米至約20微米之間。在此,第一導電凸塊170a之間的最短距離W2是指相鄰兩第一導電凸塊170a中最靠近彼此的外側面之間的距離。在本實施例中,導電凸塊170的厚度T3實質上介於約5微米至約20微米之間,而介電層140的厚度T2實質上介於約3微米至約15微米之間。導電凸塊170的厚度T3扣除掉介電層140的厚度T2即為第一導電凸塊170a的頂表面至介電層140的頂表面的距離D2,在本實施例中,此距離D2與相鄰兩第一導電凸塊170a之間的最短距離W2的比值實質上等於或小於1。Next, referring to FIG. 6 and FIG. 7 , a photoresist removal process is performed to remove the
綜上所述,本揭露的半導體裝置及其製造方法透過增設介電層於鈍化層與光阻層之間,可大幅降低用以形成導電凸塊的光阻層的厚度,因而可降低光阻層的深寬比,減少因光阻層的深寬比過大而導致結構強度不足的問題,因此,本揭露的半導體裝置可有效減少光阻層容易在後續的熱製程(例如電鍍製程)中因熱應力而產生光阻剝離的現象,因而能提升製程良率。In summary, the disclosed semiconductor device and its manufacturing method can greatly reduce the thickness of the photoresist layer used to form the conductive bumps by adding a dielectric layer between the passivation layer and the photoresist layer, thereby reducing the photoresist The aspect ratio of the layer reduces the problem of insufficient structural strength caused by the excessively large aspect ratio of the photoresist layer. The phenomenon of photoresist peeling due to thermal stress can improve the process yield.
此外,由於光阻層的深寬比過大的問題在導電凸塊間距較小的區域影響較為嚴重,故本揭露可僅將介電層設置在導電凸塊的間距較小的區域內,以降低在導電凸塊間距較小的區域內的光阻層的厚度,使光阻層的深寬比在半導體裝置的各區域間較為相似,提升製程良率。In addition, since the problem of too large aspect ratio of the photoresist layer is more serious in the area where the pitch of the conductive bumps is smaller, the present disclosure can only arrange the dielectric layer in the area of the smaller pitch of the conductive bumps to reduce the The thickness of the photoresist layer in the area where the distance between the conductive bumps is small makes the aspect ratio of the photoresist layer relatively similar among the regions of the semiconductor device, thereby improving the process yield.
100:半導體裝置
110:基板
120:接墊
120a:第一接墊、接墊
120b:第二接墊、接墊
130:鈍化層
132:鈍化層開口
140:介電層
142:介電層開口
150:凸塊底金屬層
160:光阻層
162:光阻層開口
170:導電凸塊
170a:第一導電凸塊、導電凸塊
170b:第二導電凸塊、導電凸塊
D1、D2:距離
R1:第一區
R2:第二區
T1、T2、T3:厚度
W1、W2:間距
100: Semiconductor device
110: Substrate
120:
圖1至圖6是依照本發明的一實施例的一種半導體裝置的製造流程的剖面示意圖。 圖7是依照本發明的一實施例的一種半導體裝置的俯視示意圖。 1 to 6 are schematic cross-sectional views of a manufacturing process of a semiconductor device according to an embodiment of the present invention. FIG. 7 is a schematic top view of a semiconductor device according to an embodiment of the present invention.
110:基板 110: Substrate
120a:第一接墊、接墊 120a: first pad, pad
120b:第二接墊、接墊 120b: second pad, pad
130:鈍化層 130: passivation layer
140:介電層 140: dielectric layer
142:介電層開口 142: dielectric layer opening
150:凸塊底金屬層 150: Under bump metal layer
160:光阻層 160: photoresist layer
162:光阻層開口 162: photoresist layer opening
D1:距離 D1: distance
R1:第一區 R1: Region 1
R2:第二區 R2: second area
W1:間距 W1: Spacing
Claims (15)
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